JP2014220465A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014220465A JP2014220465A JP2013100429A JP2013100429A JP2014220465A JP 2014220465 A JP2014220465 A JP 2014220465A JP 2013100429 A JP2013100429 A JP 2013100429A JP 2013100429 A JP2013100429 A JP 2013100429A JP 2014220465 A JP2014220465 A JP 2014220465A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 159
- 238000009792 diffusion process Methods 0.000 claims abstract description 216
- 239000000758 substrate Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 167
- 229910052710 silicon Inorganic materials 0.000 claims description 167
- 239000010703 silicon Substances 0.000 claims description 167
- 238000002955 isolation Methods 0.000 claims description 60
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- 239000012535 impurity Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 description 2
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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Abstract
Description
第1活性領域は、中間素子分離領域に隣接する第1半導体ピラーと、第1半導体ピラーの上部に位置する第1上部拡散層と、第1半導体ピラーに対して第1方向に隣接する第2半導体ピラーと、第2半導体ピラーの上部に位置する第2上部拡散層と、第1半導体ピラーと第2半導体ピラーの周囲を囲んで連続する第1ゲート電極と、を備え、
第2活性領域は、中間素子分離領域に隣接する第3半導体ピラーと、第3半導体ピラーの上部に位置する第3上部拡散層と、第3半導体ピラーに対して第1方向に隣接する第4半導体ピラーと、第4半導体ピラーの上部に位置する第4上部拡散層と、第3半導体ピラーと第4半導体ピラーの周囲を囲んで連続する第2ゲート電極と、を備え、
中間素子分離領域は、第1活性領域と第2活性領域に跨って第1方向に延在するダミーピラーと、ダミーピラーの周囲を囲む給電用ゲート電極と、を備え、
第1ゲート電極と第2ゲート電極とは給電用ゲート電極に各々接続され、
第1上部拡散層および第2上部拡散層は一つの第1上部コンタクトプラグに接続され、
第3上部拡散層および第4上部拡散層は一つの第2上部コンタクトプラグに接続される構成となる。
本発明の第1の実施形態について、図面に基づき詳細に説明する。以下の図面においては、各構成をわかりやすくするために、実際の構成と各構成における縮尺や数等が異なっている。また、X-Y-Z座標系を設定し、各構成の配置を説明する。この座標系において、Z方向(第3方向)はシリコン基板の主面に垂直な方向であり、X方向(第2方向)はシリコン基板の主面と水平な面においてZ方向と直交する方向であって、Y方向(第1方向)はシリコン基板の主面と水平な面においてX方向と直交する方向である。他の実施形態においても同じ構成となる。
図1から図4を参照して、本発明の第1の実施形態に係る半導体装置100の構成を説明する。
次に、第1の実施形態に係る半導体装置100の製造方法について、図9から図21を参照しながら詳細に説明する。
第1上部コンタクトプラグ30Aに接続する第1上部プラグ配線33A、第2上部コンタクトプラグ30Bに接続する第2上部プラグ配線33B、第1下部コンタクトプラグ31Aに接続する第1下部プラグ配線34A、第2下部コンタクトプラグ31Bに接続する第2下部プラグ配線34B、ゲート給電プラグ41に接続するゲート給電配線42が各々同時に形成される。
第1実施形態では、上部コンタクトプラグ30を縦型トランジスタ50の配置方向に延在させてから、その上面にメタル配線(上部プラグ配線)33を配置したが、メタルコンタクトプラグ(上部コンタクトプラグ)30の配置、並びにメタルコンタクトプラグ30とメタル配線33の接続構成は、種々変更可能であるので、以下詳細に説明する。
第1実施形態および第2実施形態では、一つの活性領域内に配置された複数の縦型トランジスタの各々の上部拡散層を一つのコンタクトプラグに接続する構成について説明した。
本第4実施形態では、第3実施形態の構成を基に、上部コンタクトプラグ30の上面に接続する上部プラグ配線33をさらに付加して構成するC−MOSインバータ回路について説明する。
1A 第1活性領域
1B 第2活性領域
2 素子分離領域(STI)
2a 溝
2b 絶縁膜
2A 中間素子分離領域
3 パッド絶縁膜
4 マスク膜
5 シリコンピラー
5A シリコンピラー
5A1 第1シリコンピラー
5A2 第2シリコンピラー
5B1 第3シリコンピラー
5B2 第4シリコンピラー
6 ダミーピラー
6A 第1ダミーシリコンピラー
6B 第2ダミーシリコンピラー
6C ダミー絶縁膜ピラー
8 絶縁膜
9a 第1下部拡散層
9b 第2下部拡散層
10 ゲート絶縁膜
11a 第1ゲート電極
11b 給電用ゲート電極
11c 第2ゲート電極
12 第1層間絶縁膜
13 マスク膜
14 第1開口部
15 第2開口部
16aa 第1拡散層
16ab 第2拡散層
16ba 第3拡散層
16bb 第4拡散層
17 絶縁膜
18 サイドウォール膜
19Aa 第1シリコンプラグ
19AA 第1上部拡散層
19Ab 第2シリコンプラグ
19AB 第2上部拡散層
19Ba 第3シリコンプラグ
19BA 第3上部拡散層
19Bb 第4シリコンプラグ
19BB 第4上部拡散層
20 第2層間絶縁膜
21 ストッパー膜
24 第3層間絶縁膜
28a 第1コンタクトホール(第1上部コンタクトホール)
28b 第2コンタクトホール(第2上部コンタクトホール)
28c 第3コンタクトホール(ゲートコンタクトホール)
29a 第4コンタクトホール(第1下部コンタクトホール)
29b 第5コンタクトホール(第2下部コンタクトホール)
30 上部コンタクトプラグ
30A 第1上部拡散層コンタクトプラグ(第1上部コンタクトプラグ)
30B 第2上部拡散層コンタクトプラグ(第2上部コンタクトプラグ)
31A 第1下部拡散層コンタクトプラグ(第1下部コンタクトプラグ)
31B 第2下部拡散層コンタクトプラグ(第2下部コンタクトプラグ)
32A 第3上部コンタクトプラグ
32B 第4上部コンタクトプラグ
33 上部プラグ配線
33A 第1上部プラグ配線
33B 第2上部プラグ配線
34A 第1下部プラグ配線
34B 第2下部プラグ配線
35 第2ゲート給電プラグ
36A 第3下部コンタクトプラグ
36B 第4下部コンタクトプラグ
41 ゲート給電コンタクトプラグ(ゲート給電プラグ)
42 ゲート給電配線
50A 第1並列トランジスタ
50A1 第1トランジスタ
50A2 第2トランジスタ
50B 第2並列トランジスタ
50B1 第3トランジスタ
50B2 第4トランジスタ
100 半導体装置
200 半導体装置
300 半導体装置
X X方向(第2方向、第1方向)
Y Y方向(第1方向、第2方向)
Z Z方向(第3方向)
Claims (15)
- 半導体基板上の活性領域に配置される複数の縦型トランジスタを並列に接続する一つの並列トランジスタを有する半導体装置であって、
前記並列トランジスタは、
前記半導体基板の主面に垂直な方向に突き出す複数の半導体ピラーと、
前記複数の半導体ピラーの下方に配置される下部拡散層と、
前記複数の半導体ピラーの上部にそれぞれ配置される複数の上部拡散層と、
前記複数の半導体ピラーの側面全体にゲート絶縁膜を介して配置されるゲート電極と、
で構成され、
前記複数の上部拡散層は、当該複数の上部拡散層の上に配置される一つの上部コンタクトプラグに接続される半導体装置。 - 前記複数の上部拡散層の各々は、
前記半導体ピラーの上部に配置される拡散層と、
該拡散層の上面に接続されたシリコンプラグと、
から構成される請求項1に記載の半導体装置。 - 前記複数の半導体ピラーの周囲に設けられた絶縁膜を更に有し、該絶縁膜によって前記下部拡散層と前記ゲート電極とが電気的に絶縁されている、請求項1又は2に記載の半導体装置。
- 前記下部拡散層は、下部コンタクトプラグに接続される、請求項1乃至3のいずれか1つに記載の半導体装置。
- 半導体基板の主面に配置される素子分離領域と、前記素子分離領域に囲まれ第1方向に隣接する第1活性領域および第2活性領域と、前記第1活性領域および前記第2活性領域に挟まれる中間素子分離領域と、を有する半導体装置であって、
前記第1活性領域は、
前記中間素子分離領域に隣接する第1半導体ピラーと、
前記第1半導体ピラーの上部に位置する第1上部拡散層と、
前記第1半導体ピラーに対して第1方向に隣接する第2半導体ピラーと、
前記第2半導体ピラーの上部に位置する第2上部拡散層と、
前記第1半導体ピラーと前記第2半導体ピラーの周囲を囲んで連続する第1ゲート電極と、を備え、
前記第2活性領域は、
前記中間素子分離領域に隣接する第3半導体ピラーと、
前記第3半導体ピラーの上部に位置する第3上部拡散層と、
前記第3半導体ピラーに対して第1方向に隣接する第4半導体ピラーと、
前記第4半導体ピラーの上部に位置する第4上部拡散層と、
前記第3半導体ピラーと前記第4半導体ピラーの周囲を囲んで連続する第2ゲート電極と、を備え、
前記中間素子分離領域は、
前記第1活性領域と前記第2活性領域とに跨って第1方向に延在するダミーピラーと、
前記ダミーピラーの周囲を囲む給電用ゲート電極と、を備え、
前記第1ゲート電極と前記第2ゲート電極とは前記給電用ゲート電極に各々接続され、
前記第1上部拡散層および前記第2上部拡散層は一つの第1上部コンタクトプラグに接続され、
前記第3上部拡散層および前記第4上部拡散層は一つの第2上部コンタクトプラグに接続される半導体装置。 - 前記第1活性領域は、前記第1および第2半導体ピラーの下方に配置される第1下部拡散層を備え、
前記第2活性領域は、前記第3および第4半導体ピラーの下方に配置される第2下部拡散層を備え、
前記第1乃至第4半導体ピラーの周囲に設けられた絶縁膜を更に有し、該該絶縁膜によって、前記第1下部拡散層と前記第1ゲート電極とが電気的に絶縁されると共に、前記第2下部拡散層と前記第2ゲート電極とが電気的に絶縁される、請求項5に記載の半導体装置。 - 前記第1および第2下部拡散層は、それぞれ、第1および第2下部コンタクトプラグに接続される、請求項5又は6に記載の半導体装置。
- 半導体基板の主面に配置される素子分離領域と、前記素子分離領域に囲まれ中間素子分離領域を介して第1方向に互いに隣接する第1活性領域および第2活性領域と、を有する半導体装置であって、
前記第1活性領域は、
前記中間素子分離領域に隣接し、かつ互いに第1方向と直交する第2方向に隣接する第1および第2半導体ピラーと、
前記第1および第2半導体ピラーの上部にそれぞれ位置する第1および第2上部拡散層と、
前記第1半導体ピラーと前記第2半導体ピラーの周囲を囲んで連続する第1ゲート電極と、を備え、
前記第2活性領域は、
前記中間素子分離領域に隣接し、かつ互いに第1方向と直交する第2方向に隣接する第3および第4半導体ピラーと、
前記第3および第4半導体ピラーの上部にそれぞれ位置する第3および第4上部拡散層と、
前記第3半導体ピラーと前記第4半導体ピラーの周囲を囲んで連続する第2ゲート電極と、を備え、
前記中間素子分離領域は、
前記第1活性領域と前記第2活性領域とに跨って第1方向に延在するダミーピラーと、
前記ダミーピラーの周囲を囲む給電用ゲート電極と、を備え、
前記第1ゲート電極と前記第2ゲート電極とは前記給電用ゲート電極に各々接続され、
前記第1上部拡散層乃至前記第4上部拡散層は一つの上部コンタクトプラグに接続される半導体装置。 - 前記第1活性領域および第2活性領域は、同一導電型半導体領域で構成されている、請求項8に記載の半導体装置。
- 前記第1活性領域は、前記第1および第2半導体ピラーの下方に配置される第1下部拡散層を備え、
前記第2活性領域は、前記第3および第4半導体ピラーの下方に配置される第2下部拡散層を備え、
前記第1乃至第4半導体ピラーの周囲に設けられた絶縁膜を更に有し、該該絶縁膜によって、前記第1下部拡散層と前記第1ゲート電極とが電気的に絶縁されると共に、前記第2下部拡散層と前記第2ゲート電極とが電気的に絶縁される、請求項9に記載の半導体装置。 - 前記第1および第2下部拡散層は、それぞれ、第1および第2下部コンタクトプラグに接続される、請求項10に記載の半導体装置。
- 前記第1活性領域および第2活性領域は、互いに異なる導電型半導体領域で構成されている、請求項8に記載の半導体装置。
- 前記第1活性領域は、前記第1および第2半導体ピラーの下方に配置される第1下部拡散層を備え、
前記第2活性領域は、前記第3および第4半導体ピラーの下方に配置される第2下部拡散層を備え、
前記第1乃至第4半導体ピラーの周囲に設けられた絶縁膜を更に有し、該該絶縁膜によって、前記第1下部拡散層と前記第1ゲート電極とが電気的に絶縁されると共に、前記第2下部拡散層と前記第2ゲート電極とが電気的に絶縁される、請求項12に記載の半導体装置。 - 前記第1および第2下部拡散層は、それぞれ、第1および第2下部コンタクトプラグに接続される、請求項13に記載の半導体装置。
- 前記第1活性領域は第1導電型半導体領域で構成され、
前記第2活性領域は第1導電型と異なる第2導電型半導体領域で構成され、
前記第1および第2上部拡散層および前記第1下部拡散層は第2導電型拡散層で構成され、
前記第3および第4上部拡散層および前記第2下部拡散層は第1導電型拡散層で構成される、
請求項13又は14に記載の半導体装置。
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