JP2014112606A - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

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Publication number
JP2014112606A
JP2014112606A JP2012266524A JP2012266524A JP2014112606A JP 2014112606 A JP2014112606 A JP 2014112606A JP 2012266524 A JP2012266524 A JP 2012266524A JP 2012266524 A JP2012266524 A JP 2012266524A JP 2014112606 A JP2014112606 A JP 2014112606A
Authority
JP
Japan
Prior art keywords
substrate
connection
semiconductor chips
wiring board
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012266524A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014112606A5 (https=
Inventor
Akihito Takano
昭仁 高野
Mitsuhiro Aizawa
光浩 相澤
Koji Hara
浩児 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012266524A priority Critical patent/JP2014112606A/ja
Priority to US14/087,461 priority patent/US20140151891A1/en
Publication of JP2014112606A publication Critical patent/JP2014112606A/ja
Publication of JP2014112606A5 publication Critical patent/JP2014112606A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2012266524A 2012-12-05 2012-12-05 半導体パッケージ Pending JP2014112606A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012266524A JP2014112606A (ja) 2012-12-05 2012-12-05 半導体パッケージ
US14/087,461 US20140151891A1 (en) 2012-12-05 2013-11-22 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012266524A JP2014112606A (ja) 2012-12-05 2012-12-05 半導体パッケージ

Publications (2)

Publication Number Publication Date
JP2014112606A true JP2014112606A (ja) 2014-06-19
JP2014112606A5 JP2014112606A5 (https=) 2015-12-10

Family

ID=50824666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012266524A Pending JP2014112606A (ja) 2012-12-05 2012-12-05 半導体パッケージ

Country Status (2)

Country Link
US (1) US20140151891A1 (https=)
JP (1) JP2014112606A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018043129A1 (ja) * 2016-08-31 2018-03-08 株式会社村田製作所 回路モジュールおよびその製造方法

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* Cited by examiner, † Cited by third party
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US9070653B2 (en) * 2013-01-15 2015-06-30 Freescale Semiconductor, Inc. Microelectronic assembly having a heat spreader for a plurality of die
US10141201B2 (en) * 2014-06-13 2018-11-27 Taiwan Semiconductor Manufacturing Company Integrated circuit packages and methods of forming same
US9721881B1 (en) 2016-04-29 2017-08-01 Nxp Usa, Inc. Apparatus and methods for multi-die packaging
JP7289719B2 (ja) * 2019-05-17 2023-06-12 新光電気工業株式会社 半導体装置、半導体装置アレイ
US10993325B2 (en) 2019-07-31 2021-04-27 Abb Power Electronics Inc. Interposer printed circuit boards for power modules
US11490517B2 (en) * 2019-07-31 2022-11-01 ABB Power Electronics, Inc. Interposer printed circuit boards for power modules
CN110461090B (zh) * 2019-08-05 2021-07-16 华为技术有限公司 电路组件以及电子设备
CN116133847A (zh) * 2020-08-06 2023-05-16 Ａｇｃ株式会社 层叠体的制造方法、层叠体和半导体封装的制造方法
US11469219B1 (en) * 2021-04-28 2022-10-11 Nanya Technology Corporation Dual die semiconductor package and manufacturing method thereof
US20240282715A1 (en) * 2023-02-17 2024-08-22 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (9)

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JP2001210954A (ja) * 2000-01-24 2001-08-03 Ibiden Co Ltd 多層基板
JP2003060153A (ja) * 2001-07-27 2003-02-28 Nokia Corp 半導体パッケージ
US20030042587A1 (en) * 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods
US20060113653A1 (en) * 2004-12-01 2006-06-01 Sherry Xiaoqi Stack package for high density integrated circuits
JP2009252893A (ja) * 2008-04-03 2009-10-29 Elpida Memory Inc 半導体装置
JP2010283349A (ja) * 2009-06-03 2010-12-16 Honeywell Internatl Inc 熱的および電気的伝導のパッケージのふたを含む集積回路パッケージ
US20110096506A1 (en) * 2009-10-28 2011-04-28 National Chip Implementation Center National Applied Research Laboratories Multi-layer soc module structure
US20120043669A1 (en) * 2010-08-20 2012-02-23 Gamal Refai-Ahmed Stacked semiconductor chip device with thermal management circuit board
JP2012212832A (ja) * 2011-03-31 2012-11-01 Kyocer Slc Technologies Corp 複合配線基板の製造方法

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US6750551B1 (en) * 1999-12-28 2004-06-15 Intel Corporation Direct BGA attachment without solder reflow
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
WO2006082620A1 (ja) * 2005-01-31 2006-08-10 Spansion Llc 積層型半導体装置及び積層型半導体装置の製造方法
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
KR100809691B1 (ko) * 2006-07-28 2008-03-06 삼성전자주식회사 수동 소자를 구비한 반도체 패키지 및 이것으로 구성되는반도체 메모리 모듈
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
US8241955B2 (en) * 2009-06-19 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with mountable inward and outward interconnects and method of manufacture thereof
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8334171B2 (en) * 2009-12-02 2012-12-18 Stats Chippac Ltd. Package system with a shielded inverted internal stacking module and method of manufacture thereof
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US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8587132B2 (en) * 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US10008475B2 (en) * 2012-09-27 2018-06-26 Intel Corporation Stacked-die including a die in a package substrate
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures

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JP2001210954A (ja) * 2000-01-24 2001-08-03 Ibiden Co Ltd 多層基板
JP2003060153A (ja) * 2001-07-27 2003-02-28 Nokia Corp 半導体パッケージ
US20030042587A1 (en) * 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods
US20060113653A1 (en) * 2004-12-01 2006-06-01 Sherry Xiaoqi Stack package for high density integrated circuits
JP2009252893A (ja) * 2008-04-03 2009-10-29 Elpida Memory Inc 半導体装置
JP2010283349A (ja) * 2009-06-03 2010-12-16 Honeywell Internatl Inc 熱的および電気的伝導のパッケージのふたを含む集積回路パッケージ
US20110096506A1 (en) * 2009-10-28 2011-04-28 National Chip Implementation Center National Applied Research Laboratories Multi-layer soc module structure
US20120043669A1 (en) * 2010-08-20 2012-02-23 Gamal Refai-Ahmed Stacked semiconductor chip device with thermal management circuit board
JP2012212832A (ja) * 2011-03-31 2012-11-01 Kyocer Slc Technologies Corp 複合配線基板の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018043129A1 (ja) * 2016-08-31 2018-03-08 株式会社村田製作所 回路モジュールおよびその製造方法
KR20190032536A (ko) * 2016-08-31 2019-03-27 가부시키가이샤 무라타 세이사쿠쇼 회로모듈 및 그 제조 방법
JPWO2018043129A1 (ja) * 2016-08-31 2019-06-24 株式会社村田製作所 回路モジュールおよびその製造方法
KR102123252B1 (ko) 2016-08-31 2020-06-16 가부시키가이샤 무라타 세이사쿠쇼 회로모듈 및 그 제조 방법
US10930573B2 (en) 2016-08-31 2021-02-23 Murata Manufacturing Co., Ltd. Circuit module and manufacturing method therefor

Also Published As

Publication number Publication date
US20140151891A1 (en) 2014-06-05

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