JP2014092813A5 - - Google Patents

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Publication number
JP2014092813A5
JP2014092813A5 JP2012241103A JP2012241103A JP2014092813A5 JP 2014092813 A5 JP2014092813 A5 JP 2014092813A5 JP 2012241103 A JP2012241103 A JP 2012241103A JP 2012241103 A JP2012241103 A JP 2012241103A JP 2014092813 A5 JP2014092813 A5 JP 2014092813A5
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JP
Japan
Prior art keywords
command
transfer request
precharge
column address
transfer
Prior art date
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Application number
JP2012241103A
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English (en)
Japanese (ja)
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JP2014092813A (ja
JP6062714B2 (ja
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Priority to JP2012241103A priority Critical patent/JP6062714B2/ja
Priority claimed from JP2012241103A external-priority patent/JP6062714B2/ja
Priority to US14/018,855 priority patent/US9336163B2/en
Publication of JP2014092813A publication Critical patent/JP2014092813A/ja
Publication of JP2014092813A5 publication Critical patent/JP2014092813A5/ja
Application granted granted Critical
Publication of JP6062714B2 publication Critical patent/JP6062714B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2012241103A 2012-10-31 2012-10-31 メモリ制御装置、メモリ制御方法およびプログラム Expired - Fee Related JP6062714B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012241103A JP6062714B2 (ja) 2012-10-31 2012-10-31 メモリ制御装置、メモリ制御方法およびプログラム
US14/018,855 US9336163B2 (en) 2012-10-31 2013-09-05 Precharge control for memory bank commands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012241103A JP6062714B2 (ja) 2012-10-31 2012-10-31 メモリ制御装置、メモリ制御方法およびプログラム

Publications (3)

Publication Number Publication Date
JP2014092813A JP2014092813A (ja) 2014-05-19
JP2014092813A5 true JP2014092813A5 (enExample) 2015-11-19
JP6062714B2 JP6062714B2 (ja) 2017-01-18

Family

ID=50548538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012241103A Expired - Fee Related JP6062714B2 (ja) 2012-10-31 2012-10-31 メモリ制御装置、メモリ制御方法およびプログラム

Country Status (2)

Country Link
US (1) US9336163B2 (enExample)
JP (1) JP6062714B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160002106A (ko) * 2014-06-30 2016-01-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작방법
JP2021157604A (ja) * 2020-03-27 2021-10-07 株式会社村田製作所 データ通信装置、データ通信モジュール
US12073114B2 (en) * 2021-09-30 2024-08-27 Advanced Micro Devices, Inc. Stacked command queue

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3506175B2 (ja) * 2000-10-05 2004-03-15 日本電気株式会社 メモリ制御回路とメモリ制御方法
JP2002334050A (ja) * 2001-05-10 2002-11-22 Canon Inc メモリ制御回路およびメモリ制御方法
JP2004310394A (ja) * 2003-04-07 2004-11-04 Sharp Corp Ｓｄｒａｍアクセス制御装置
JP4069078B2 (ja) * 2004-01-07 2008-03-26 松下電器産業株式会社 Ｄｒａｍ制御装置およびｄｒａｍ制御方法
US7280428B2 (en) * 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) * 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
JP4229958B2 (ja) * 2005-08-26 2009-02-25 Ｎｅｃエレクトロニクス株式会社 メモリ制御システムおよびメモリ制御回路
JP2007249837A (ja) * 2006-03-17 2007-09-27 Nec Electronics Corp メモリ制御装置、メモリ制御方法及び携帯機器
US8307190B2 (en) * 2006-12-25 2012-11-06 Panasonic Corporation Memory control device, memory device, and memory control method
US9015399B2 (en) * 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8918589B2 (en) * 2008-04-22 2014-12-23 Panasonic Corporation Memory controller, memory system, semiconductor integrated circuit, and memory control method
US20110238870A1 (en) * 2008-12-03 2011-09-29 Rambus Inc. Memory System With Command Filtering
JP5428687B2 (ja) * 2009-09-14 2014-02-26 株式会社リコー メモリ制御装置
US8572322B2 (en) * 2010-03-29 2013-10-29 Freescale Semiconductor, Inc. Asynchronously scheduling memory access requests

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