JP2014021859A5 - - Google Patents

Download PDF

Info

Publication number
JP2014021859A5
JP2014021859A5 JP2012161964A JP2012161964A JP2014021859A5 JP 2014021859 A5 JP2014021859 A5 JP 2014021859A5 JP 2012161964 A JP2012161964 A JP 2012161964A JP 2012161964 A JP2012161964 A JP 2012161964A JP 2014021859 A5 JP2014021859 A5 JP 2014021859A5
Authority
JP
Japan
Prior art keywords
area
bank
control device
memory
banks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012161964A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014021859A (ja
JP6000708B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2012161964A priority Critical patent/JP6000708B2/ja
Priority claimed from JP2012161964A external-priority patent/JP6000708B2/ja
Priority to US13/942,039 priority patent/US9424174B2/en
Publication of JP2014021859A publication Critical patent/JP2014021859A/ja
Publication of JP2014021859A5 publication Critical patent/JP2014021859A5/ja
Application granted granted Critical
Publication of JP6000708B2 publication Critical patent/JP6000708B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

JP2012161964A 2012-07-20 2012-07-20 メモリ制御装置および方法 Expired - Fee Related JP6000708B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012161964A JP6000708B2 (ja) 2012-07-20 2012-07-20 メモリ制御装置および方法
US13/942,039 US9424174B2 (en) 2012-07-20 2013-07-15 Control apparatus and method for controlling a memory having a plurality of banks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012161964A JP6000708B2 (ja) 2012-07-20 2012-07-20 メモリ制御装置および方法

Publications (3)

Publication Number Publication Date
JP2014021859A JP2014021859A (ja) 2014-02-03
JP2014021859A5 true JP2014021859A5 (enExample) 2015-09-03
JP6000708B2 JP6000708B2 (ja) 2016-10-05

Family

ID=49947539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012161964A Expired - Fee Related JP6000708B2 (ja) 2012-07-20 2012-07-20 メモリ制御装置および方法

Country Status (2)

Country Link
US (1) US9424174B2 (enExample)
JP (1) JP6000708B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256531B2 (en) * 2012-06-19 2016-02-09 Samsung Electronics Co., Ltd. Memory system and SoC including linear addresss remapping logic
JP6030987B2 (ja) * 2013-04-02 2016-11-24 ルネサスエレクトロニクス株式会社 メモリ制御回路
US9612648B2 (en) * 2013-08-08 2017-04-04 Qualcomm Incorporated System and method for memory channel interleaving with selective power or performance optimization
KR102355573B1 (ko) 2014-10-29 2022-01-27 삼성전자주식회사 선형 리맵퍼 및 액세스 윈도우를 포함하는 메모리 시스템 및 시스템 온 칩
US9680570B2 (en) * 2015-04-30 2017-06-13 Nistica, Inc. Optical channel monitor for a wavelength selective switch employing a single photodiode
US20170109090A1 (en) * 2015-10-16 2017-04-20 Qualcomm Incorporated System and method for page-by-page memory channel interleaving
JP2017151911A (ja) * 2016-02-26 2017-08-31 東芝メモリ株式会社 半導体装置及び制御方法
KR102589410B1 (ko) * 2017-11-10 2023-10-13 삼성전자주식회사 메모리 장치 및 그의 파워 제어 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5268331A (en) * 1975-12-05 1977-06-07 Hitachi Ltd Interleaving control system of shared memory
US5375250A (en) * 1992-07-13 1994-12-20 Van Den Heuvel; Raymond C. Method of intelligent computing and neural-like processing of time and space functions
JPH09212416A (ja) * 1995-11-30 1997-08-15 Toshiba Corp 計算機システムおよび計算機システムの電力管理方法
US5960462A (en) * 1996-09-26 1999-09-28 Intel Corporation Method and apparatus for analyzing a main memory configuration to program a memory controller
JP2000267986A (ja) * 1999-03-17 2000-09-29 Canon Inc メモリ制御装置およびメモリ制御方法
JP3963457B2 (ja) 2003-06-30 2007-08-22 株式会社東芝 無線装置
US7165165B2 (en) * 2004-03-16 2007-01-16 Intel Corporation Anticipatory power control of memory
JP2008152687A (ja) * 2006-12-20 2008-07-03 Matsushita Electric Ind Co Ltd メモリコントローラ
JP4643729B2 (ja) * 2009-07-09 2011-03-02 株式会社東芝 インタリーブ制御装置、インタリーブ制御方法及びメモリシステム
US8245060B2 (en) * 2009-10-15 2012-08-14 Microsoft Corporation Memory object relocation for power savings

Similar Documents

Publication Publication Date Title
JP2014021859A5 (enExample)
WO2014105829A3 (en) Method and system for asynchronous die operations in a non-volatile memory
JP2016529618A5 (enExample)
JP2014199583A5 (enExample)
JP2016515231A5 (enExample)
JP2014232525A5 (enExample)
WO2014150727A3 (en) Method, apparatuses and program product to save and store system memory management unit contexts
JP2014197333A5 (enExample)
WO2006006084A3 (en) Establishing command order in an out of order dma command queue
JP2014523046A5 (enExample)
WO2016145328A3 (en) High performance non-volatile memory module
JP2013200702A5 (enExample)
WO2011087283A3 (ko) 다양한 종류의 반도체 메모리 장치들을 구비하는 반도체 메모리 시스템 및 이의 제어 방법
JP2012524353A5 (enExample)
WO2014182314A3 (en) Acceleration of memory access
GB2525831A (en) Prefetching for parent core in multi-core chip
JP2017510890A5 (enExample)
WO2017151588A3 (en) A system and method for programming data transfer within a microcontroller
JP2013248526A5 (enExample)
JP2009093227A5 (enExample)
JP2018523235A5 (enExample)
TW200735099A (en) Semiconductor memory, memory system, and operation method of semiconductor memory
JP2010191818A5 (enExample)
JP2012128846A5 (enExample)
WO2012064463A8 (en) Memory controller and system for storing blocks of data in non-volatile memory devices for high speed sequential reading