JP2009093227A5 - - Google Patents

Download PDF

Info

Publication number
JP2009093227A5
JP2009093227A5 JP2007260357A JP2007260357A JP2009093227A5 JP 2009093227 A5 JP2009093227 A5 JP 2009093227A5 JP 2007260357 A JP2007260357 A JP 2007260357A JP 2007260357 A JP2007260357 A JP 2007260357A JP 2009093227 A5 JP2009093227 A5 JP 2009093227A5
Authority
JP
Japan
Prior art keywords
command
information
access control
memory access
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007260357A
Other languages
English (en)
Japanese (ja)
Other versions
JP5188134B2 (ja
JP2009093227A (ja
Filing date
Publication date
Priority claimed from JP2007260357A external-priority patent/JP5188134B2/ja
Priority to JP2007260357A priority Critical patent/JP5188134B2/ja
Application filed filed Critical
Priority to US12/208,001 priority patent/US8516214B2/en
Priority to CN201210233110.3A priority patent/CN102841879A/zh
Priority to CN200810148861.9A priority patent/CN101403958A/zh
Publication of JP2009093227A publication Critical patent/JP2009093227A/ja
Publication of JP2009093227A5 publication Critical patent/JP2009093227A5/ja
Publication of JP5188134B2 publication Critical patent/JP5188134B2/ja
Application granted granted Critical
Priority to US13/939,099 priority patent/US8762676B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2007260357A 2007-10-03 2007-10-03 メモリアクセス制御装置及びメモリアクセス制御方法 Expired - Fee Related JP5188134B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007260357A JP5188134B2 (ja) 2007-10-03 2007-10-03 メモリアクセス制御装置及びメモリアクセス制御方法
US12/208,001 US8516214B2 (en) 2007-10-03 2008-09-10 Memory access control device, command issuing device, and method
CN201210233110.3A CN102841879A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、存储器系统和存储器访问控制方法
CN200810148861.9A CN101403958A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、命令发出装置和方法
US13/939,099 US8762676B2 (en) 2007-10-03 2013-07-10 Memory access control device, command issuing device, and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007260357A JP5188134B2 (ja) 2007-10-03 2007-10-03 メモリアクセス制御装置及びメモリアクセス制御方法

Publications (3)

Publication Number Publication Date
JP2009093227A JP2009093227A (ja) 2009-04-30
JP2009093227A5 true JP2009093227A5 (enExample) 2010-08-26
JP5188134B2 JP5188134B2 (ja) 2013-04-24

Family

ID=40524307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007260357A Expired - Fee Related JP5188134B2 (ja) 2007-10-03 2007-10-03 メモリアクセス制御装置及びメモリアクセス制御方法

Country Status (3)

Country Link
US (2) US8516214B2 (enExample)
JP (1) JP5188134B2 (enExample)
CN (2) CN101403958A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256384B2 (en) * 2013-02-04 2016-02-09 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for reducing write latency in a data storage system by using a command-push model
JP6700739B2 (ja) * 2015-11-24 2020-05-27 キヤノン株式会社 コントローラおよび制御方法
US10146681B2 (en) * 2015-12-24 2018-12-04 Intel Corporation Non-uniform memory access latency adaptations to achieve bandwidth quality of service
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
KR102655360B1 (ko) * 2018-12-13 2024-04-05 에스케이하이닉스 주식회사 컨트롤러, 데이터 저장 장치 및 그것의 동작 방법
KR20220105890A (ko) * 2021-01-21 2022-07-28 삼성전자주식회사 커맨드가 삽입된 데이터를 공유된 채널 양방향으로 전송할 수 있는 스토리지 장치 및 그것의 동작 방법
US11977465B2 (en) 2022-05-26 2024-05-07 Changxin Memory Technologies, Inc. Method for testing a command, an apparatus for testing a command and a readable storage medium
CN117174160A (zh) * 2022-05-26 2023-12-05 长鑫存储技术有限公司 指令的测试方法、装置、测试平台及可读存储介质
WO2025032645A1 (ja) * 2023-08-04 2025-02-13 三菱電機株式会社 遅延装置、メモリ制御システム、遅延方法及びプログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821736B2 (ja) * 1977-08-10 1983-05-02 沖電気工業株式会社 メモリ制御方式
JP2972214B2 (ja) * 1988-10-24 1999-11-08 日本電気株式会社 情報処理装置
US6697926B2 (en) * 2001-06-06 2004-02-24 Micron Technology, Inc. Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
JP2003173290A (ja) * 2001-12-06 2003-06-20 Ricoh Co Ltd メモリ制御装置
US6819599B2 (en) * 2002-08-01 2004-11-16 Micron Technology, Inc. Programmable DQS preamble
WO2004025478A1 (ja) * 2002-09-11 2004-03-25 Fujitsu Limited メモリブロック間のレイテンシ差を活用するデータ処理装置および方法
US6963516B2 (en) * 2002-11-27 2005-11-08 International Business Machines Corporation Dynamic optimization of latency and bandwidth on DRAM interfaces
US7222224B2 (en) 2004-05-21 2007-05-22 Rambus Inc. System and method for improving performance in computer memory systems supporting multiple memory access latencies

Similar Documents

Publication Publication Date Title
JP2009093227A5 (enExample)
TW200739354A (en) Method and device for reduced read latency of non-volatile memory
EP2763047A3 (en) Method and system for reducing write latency in a data storage system by using a command-push model
JP2013025795A5 (enExample)
WO2014105829A3 (en) Method and system for asynchronous die operations in a non-volatile memory
WO2010080142A3 (en) Modifying commands
WO2009072100A3 (en) Systems and methods for temporarily retiring memory portions
WO2010085340A3 (en) Host controller
JP2010231495A (ja) メモリ制御装置
JP2011118893A5 (enExample)
JP2014021859A5 (enExample)
WO2016135744A3 (en) A system and method for multi-cycle write leveling
JP2011018427A5 (enExample)
JP2010198327A5 (ja) マイクロコントローラ
JP2010191818A5 (enExample)
JP2009064360A5 (enExample)
TW200735099A (en) Semiconductor memory, memory system, and operation method of semiconductor memory
WO2009001514A1 (ja) メモリコントローラ、不揮発性記憶装置、ファイルシステム、不揮発性記憶システム、データ書き込み方法及びデータ書き込みプログラム
JP2012223911A5 (enExample)
JP2009033439A5 (enExample)
JP2010198171A5 (ja) Ｕｓｂホストコントローラ
JP2006236105A5 (enExample)
JP2018170733A5 (enExample)
JP2007226942A5 (enExample)
WO2008114443A1 (ja) マルチプロセッサシステム及びその制御方法