JP2011118893A5 - - Google Patents

Download PDF

Info

Publication number
JP2011118893A5
JP2011118893A5 JP2010256099A JP2010256099A JP2011118893A5 JP 2011118893 A5 JP2011118893 A5 JP 2011118893A5 JP 2010256099 A JP2010256099 A JP 2010256099A JP 2010256099 A JP2010256099 A JP 2010256099A JP 2011118893 A5 JP2011118893 A5 JP 2011118893A5
Authority
JP
Japan
Prior art keywords
asynchronous
clock
upsizing
channel
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010256099A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011118893A (ja
Filing date
Publication date
Priority claimed from KR1020090117760A external-priority patent/KR20110061189A/ko
Application filed filed Critical
Publication of JP2011118893A publication Critical patent/JP2011118893A/ja
Publication of JP2011118893A5 publication Critical patent/JP2011118893A5/ja
Pending legal-status Critical Current

Links

JP2010256099A 2009-12-01 2010-11-16 非同期統合アップサイジング回路 Pending JP2011118893A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090117760A KR20110061189A (ko) 2009-12-01 2009-12-01 데이터 프로세싱 시스템에서의 비동기 통합 업사이징 회로
KR10-2009-0117760 2009-12-01

Publications (2)

Publication Number Publication Date
JP2011118893A JP2011118893A (ja) 2011-06-16
JP2011118893A5 true JP2011118893A5 (enExample) 2014-01-09

Family

ID=44069700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010256099A Pending JP2011118893A (ja) 2009-12-01 2010-11-16 非同期統合アップサイジング回路

Country Status (4)

Country Link
US (1) US8443122B2 (enExample)
JP (1) JP2011118893A (enExample)
KR (1) KR20110061189A (enExample)
CN (1) CN102103561B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120046461A (ko) * 2010-11-02 2012-05-10 삼성전자주식회사 인터페이스 장치 및 이를 포함하는 시스템
US9159116B2 (en) 2013-02-13 2015-10-13 Google Inc. Adaptive screen interfaces based on viewing distance
CN104008076B (zh) * 2013-02-25 2018-04-10 中兴通讯股份有限公司 一种支持dvfs的总线数据信号传输的方法及装置
KR102206313B1 (ko) 2014-02-07 2021-01-22 삼성전자주식회사 시스템 인터커넥트 및 시스템 인터커넥트의 동작 방법
US9489009B2 (en) 2014-02-20 2016-11-08 Samsung Electronics Co., Ltd. System on chip, bus interface and method of operating the same
KR20160118049A (ko) * 2015-04-01 2016-10-11 삼성전기주식회사 전자 장치, 이의 비동기 방식 데이터 전송 방법 및 광학 이미지 안정화 모듈
DE102016109387A1 (de) * 2015-05-26 2016-12-01 Samsung Electronics Co., Ltd. Ein-Chip-System mit Taktverwaltungseinheit und Verfahren zum Betreiben des Ein-Chip-Systems
US9891986B2 (en) 2016-01-26 2018-02-13 Nxp Usa, Inc. System and method for performing bus transactions
KR102398181B1 (ko) * 2017-07-03 2022-05-17 삼성전자주식회사 쓰기 데이터를 위해 할당될 물리 어드레스를 미리 관리하는 스토리지 장치
CN108595350B (zh) * 2018-01-04 2022-04-05 深圳开阳电子股份有限公司 一种基于axi的数据传输方法和装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2632395B2 (ja) * 1988-12-01 1997-07-23 富士通株式会社 バス接続装置
KR0157924B1 (ko) * 1995-12-23 1998-12-15 문정환 데이타 전송 시스템 및 그 방법
JP2001014270A (ja) 1999-07-01 2001-01-19 Matsushita Electric Ind Co Ltd データ転送方法、データ転送装置及びその利用システム
JP2001134420A (ja) * 1999-11-02 2001-05-18 Hitachi Ltd データ処理装置
US6900812B1 (en) * 2000-08-02 2005-05-31 Ati International Srl Logic enhanced memory and method therefore
JP2002373146A (ja) 2001-06-15 2002-12-26 Fuji Xerox Co Ltd バスブリッジ装置
US7519728B1 (en) * 2002-07-18 2009-04-14 Juniper Networks, Inc. Merge systems and methods for transmit systems interfaces
DE602004026533D1 (de) * 2004-02-02 2010-05-27 Sony Deutschland Gmbh Verfahren zur Datenübertragung in einem Mehrnormensnetzwerk
US7085874B2 (en) * 2004-04-02 2006-08-01 Arm Limited Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits
US7454538B2 (en) * 2005-05-11 2008-11-18 Qualcomm Incorporated Latency insensitive FIFO signaling protocol
KR20070000941A (ko) 2005-06-28 2007-01-03 삼성전자주식회사 브릿지장치
US7457905B2 (en) * 2005-08-29 2008-11-25 Lsi Corporation Method for request transaction ordering in OCP bus to AXI bus bridge design
CN100483377C (zh) * 2006-05-17 2009-04-29 华为技术有限公司 一种异步桥及数据传输方法
CN101261575B (zh) * 2008-02-26 2010-04-21 北京天碁科技有限公司 一种实现不等宽数据传输的异步先进先出存储器及方法

Similar Documents

Publication Publication Date Title
JP2011118893A5 (enExample)
WO2023185035A1 (zh) 内存直接访问架构、系统、方法、电子设备和介质
JP6817273B2 (ja) 不揮発性大容量メモリ・システムによるキャッシュ移動を提供するための装置および方法
CN105224482B (zh) 一种fpga加速卡高速存储系统
AU2010319715B2 (en) Command queue for peripheral component
TWI451263B (zh) 通用序列匯流排傳輸轉譯器及微訊框同步方法
CN102591783B (zh) 可编程存储器控制器
JP6173340B2 (ja) バス上の複数のデータ線を介してデータを送るシステムおよび方法
KR20210038313A (ko) 레이턴시에 중점을 둔 판독 동작과 대역폭에 중점을 둔 판독 동작 사이의 동적 변경
WO2010051621A8 (en) Bridge device having a virtual page buffer
JP6370027B2 (ja) 高クロック速度での連続リードバーストサポート
WO2013176912A1 (en) Flash memory controller
JP2007087388A (ja) メモリコントローラ及びそれを含んだデータ処理システム
CN102103561B (zh) 数据处理系统中的异步扩展电路
WO2012099434A3 (en) Sas-based semiconductor storage device memory disk unit
US20180253391A1 (en) Multiple channel memory controller using virtual channel
JP2013542493A (ja) 複数のメモリチャネルを有するコンピューティングシステムにおけるメモリバッファの割り当て
CN113330428A (zh) 数据样本传输方案及相关系统、方法和设备
JP2017004430A5 (enExample)
US7913013B2 (en) Semiconductor integrated circuit
CN115586974B (zh) 内存控制器、系统、装置及电子设备
JP2008027247A5 (enExample)
CN103186351B (zh) 高性能ahci接口
JP2009064360A5 (enExample)
CN201218944Y (zh) 双口ram实现闪存控制器缓存的结构