CN101403958A - 存储器访问控制装置、命令发出装置和方法 - Google Patents

存储器访问控制装置、命令发出装置和方法 Download PDF

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Publication number
CN101403958A
CN101403958A CN200810148861.9A CN200810148861A CN101403958A CN 101403958 A CN101403958 A CN 101403958A CN 200810148861 A CN200810148861 A CN 200810148861A CN 101403958 A CN101403958 A CN 101403958A
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CN
China
Prior art keywords
access
command
order
memory device
memory
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Pending
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CN200810148861.9A
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English (en)
Chinese (zh)
Inventor
落合涉
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Publication of CN101403958A publication Critical patent/CN101403958A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
CN200810148861.9A 2007-10-03 2008-09-27 存储器访问控制装置、命令发出装置和方法 Pending CN101403958A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007260357A JP5188134B2 (ja) 2007-10-03 2007-10-03 メモリアクセス制御装置及びメモリアクセス制御方法
JP2007260357 2007-10-03

Related Child Applications (1)

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CN201210233110.3A Division CN102841879A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、存储器系统和存储器访问控制方法

Publications (1)

Publication Number Publication Date
CN101403958A true CN101403958A (zh) 2009-04-08

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CN200810148861.9A Pending CN101403958A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、命令发出装置和方法
CN201210233110.3A Pending CN102841879A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、存储器系统和存储器访问控制方法

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CN201210233110.3A Pending CN102841879A (zh) 2007-10-03 2008-09-27 存储器访问控制装置、存储器系统和存储器访问控制方法

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US (2) US8516214B2 (enExample)
JP (1) JP5188134B2 (enExample)
CN (2) CN101403958A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292281A (zh) * 2015-12-24 2018-07-17 英特尔公司 实现带宽服务质量的非一致性存储器访问延迟调整
WO2023226061A1 (zh) * 2022-05-26 2023-11-30 长鑫存储技术有限公司 指令的测试方法、装置、测试平台及可读存储介质
US11977465B2 (en) 2022-05-26 2024-05-07 Changxin Memory Technologies, Inc. Method for testing a command, an apparatus for testing a command and a readable storage medium

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256384B2 (en) * 2013-02-04 2016-02-09 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for reducing write latency in a data storage system by using a command-push model
JP6700739B2 (ja) * 2015-11-24 2020-05-27 キヤノン株式会社 コントローラおよび制御方法
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
KR102655360B1 (ko) * 2018-12-13 2024-04-05 에스케이하이닉스 주식회사 컨트롤러, 데이터 저장 장치 및 그것의 동작 방법
KR20220105890A (ko) * 2021-01-21 2022-07-28 삼성전자주식회사 커맨드가 삽입된 데이터를 공유된 채널 양방향으로 전송할 수 있는 스토리지 장치 및 그것의 동작 방법
WO2025032645A1 (ja) * 2023-08-04 2025-02-13 三菱電機株式会社 遅延装置、メモリ制御システム、遅延方法及びプログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821736B2 (ja) * 1977-08-10 1983-05-02 沖電気工業株式会社 メモリ制御方式
JP2972214B2 (ja) * 1988-10-24 1999-11-08 日本電気株式会社 情報処理装置
US6697926B2 (en) * 2001-06-06 2004-02-24 Micron Technology, Inc. Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
JP2003173290A (ja) * 2001-12-06 2003-06-20 Ricoh Co Ltd メモリ制御装置
US6819599B2 (en) * 2002-08-01 2004-11-16 Micron Technology, Inc. Programmable DQS preamble
WO2004025478A1 (ja) * 2002-09-11 2004-03-25 Fujitsu Limited メモリブロック間のレイテンシ差を活用するデータ処理装置および方法
US6963516B2 (en) * 2002-11-27 2005-11-08 International Business Machines Corporation Dynamic optimization of latency and bandwidth on DRAM interfaces
US7222224B2 (en) 2004-05-21 2007-05-22 Rambus Inc. System and method for improving performance in computer memory systems supporting multiple memory access latencies

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292281A (zh) * 2015-12-24 2018-07-17 英特尔公司 实现带宽服务质量的非一致性存储器访问延迟调整
US11138101B2 (en) 2015-12-24 2021-10-05 Intel Corporation Non-uniform memory access latency adaptations to achieve bandwidth quality of service
CN108292281B (zh) * 2015-12-24 2021-10-15 英特尔公司 用于非一致性存储器访问延迟调整的系统、装置、方法
WO2023226061A1 (zh) * 2022-05-26 2023-11-30 长鑫存储技术有限公司 指令的测试方法、装置、测试平台及可读存储介质
US11977465B2 (en) 2022-05-26 2024-05-07 Changxin Memory Technologies, Inc. Method for testing a command, an apparatus for testing a command and a readable storage medium

Also Published As

Publication number Publication date
US8516214B2 (en) 2013-08-20
US20130297896A1 (en) 2013-11-07
CN102841879A (zh) 2012-12-26
US8762676B2 (en) 2014-06-24
JP5188134B2 (ja) 2013-04-24
JP2009093227A (ja) 2009-04-30
US20090094432A1 (en) 2009-04-09

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Application publication date: 20090408