JP2016529618A5 - - Google Patents

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Publication number
JP2016529618A5
JP2016529618A5 JP2016533452A JP2016533452A JP2016529618A5 JP 2016529618 A5 JP2016529618 A5 JP 2016529618A5 JP 2016533452 A JP2016533452 A JP 2016533452A JP 2016533452 A JP2016533452 A JP 2016533452A JP 2016529618 A5 JP2016529618 A5 JP 2016529618A5
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Japan
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memory
preference
memory device
linear region
performance
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JP2016533452A
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Japanese (ja)
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JP6178512B2 (ja
JP2016529618A (ja
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Priority claimed from US13/962,746 external-priority patent/US9612648B2/en
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Publication of JP6178512B2 publication Critical patent/JP6178512B2/ja
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JP2016533452A 2013-08-08 2014-08-07 選択的な電力または性能の最適化を伴うメモリチャネルインターリービングのためのシステムおよび方法 Expired - Fee Related JP6178512B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/962,746 US9612648B2 (en) 2013-08-08 2013-08-08 System and method for memory channel interleaving with selective power or performance optimization
US13/962,746 2013-08-08
PCT/US2014/050208 WO2015021316A1 (en) 2013-08-08 2014-08-07 System and method for memory channel interleaving with selective power or performance optimization

Publications (3)

Publication Number Publication Date
JP2016529618A JP2016529618A (ja) 2016-09-23
JP2016529618A5 true JP2016529618A5 (enExample) 2017-07-20
JP6178512B2 JP6178512B2 (ja) 2017-08-09

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JP2016533452A Expired - Fee Related JP6178512B2 (ja) 2013-08-08 2014-08-07 選択的な電力または性能の最適化を伴うメモリチャネルインターリービングのためのシステムおよび方法

Country Status (8)

Country Link
US (1) US9612648B2 (enExample)
EP (1) EP3030949B1 (enExample)
JP (1) JP6178512B2 (enExample)
KR (1) KR101753020B1 (enExample)
CN (1) CN105452986B (enExample)
BR (1) BR112016002454B1 (enExample)
CA (1) CA2918091C (enExample)
WO (1) WO2015021316A1 (enExample)

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KR20220063335A (ko) 2020-11-10 2022-05-17 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US12314761B2 (en) * 2021-02-12 2025-05-27 University Of Massachusetts System and method for memory allocation and management in non-uniform memory access architecture computing environments
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