JP2014232525A5 - - Google Patents

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Publication number
JP2014232525A5
JP2014232525A5 JP2014092259A JP2014092259A JP2014232525A5 JP 2014232525 A5 JP2014232525 A5 JP 2014232525A5 JP 2014092259 A JP2014092259 A JP 2014092259A JP 2014092259 A JP2014092259 A JP 2014092259A JP 2014232525 A5 JP2014232525 A5 JP 2014232525A5
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JP
Japan
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operation mode
volatile memory
memory
processor
main memory
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JP2014092259A
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Japanese (ja)
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JP6335616B2 (ja
JP2014232525A (ja
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Priority claimed from JP2014092259A external-priority patent/JP6335616B2/ja
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Publication of JP2014232525A5 publication Critical patent/JP2014232525A5/ja
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Publication of JP6335616B2 publication Critical patent/JP6335616B2/ja
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JP2014092259A 2013-04-30 2014-04-28 半導体装置 Expired - Fee Related JP6335616B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014092259A JP6335616B2 (ja) 2013-04-30 2014-04-28 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013095552 2013-04-30
JP2013095552 2013-04-30
JP2014092259A JP6335616B2 (ja) 2013-04-30 2014-04-28 半導体装置

Related Child Applications (1)

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JP2018088150A Division JP6505910B2 (ja) 2013-04-30 2018-05-01 半導体装置

Publications (3)

Publication Number Publication Date
JP2014232525A JP2014232525A (ja) 2014-12-11
JP2014232525A5 true JP2014232525A5 (enExample) 2017-06-15
JP6335616B2 JP6335616B2 (ja) 2018-05-30

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JP2014092259A Expired - Fee Related JP6335616B2 (ja) 2013-04-30 2014-04-28 半導体装置
JP2018088150A Expired - Fee Related JP6505910B2 (ja) 2013-04-30 2018-05-01 半導体装置

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US (1) US10141053B2 (enExample)
JP (2) JP6335616B2 (enExample)

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JP6822853B2 (ja) 2016-01-21 2021-01-27 株式会社半導体エネルギー研究所 記憶装置及び記憶装置の駆動方法
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WO2019175704A1 (ja) 2018-03-16 2019-09-19 株式会社半導体エネルギー研究所 電気モジュール、表示パネル、表示装置、入出力装置、情報処理装置、電気モジュールの作製方法
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