JP2014042019A - 傾斜型ソース/ドレインを具備する半導体装置及び関連方法 - Google Patents
傾斜型ソース/ドレインを具備する半導体装置及び関連方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 12
- 239000007943 implant Substances 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000007935 neutral effect Effects 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】 半導体装置は、チャンネル領域と、該チャンネル領域上方のゲート構成体と、該ゲート構成体の両側のソース及びドレイン領域とを具備する半導体基板を包含している。該ソース及びドレイン領域の各々の上に夫々のコンタクトが設けられている。該ソース及びドレイン領域の内の少なくとも一方は、該夫々のコンタクトとの傾斜型上部接触表面を具備している。該傾斜型上部接触表面は、対応する平坦な接触表面の場合よりも少なくとも50%一層大きな面積を有している。
【選択図】 図1
Description
近くの電界を減少させ、従って、該トランジスタのホットキャリアに関する信頼性が改善される。延長部領域80は、該延長部領域を横断してのソース/ドレイン電圧の一部を効果的に降下させることによって電界を減少させる。
12:半導体基板
20:Pウエル
30:Nウエル
34:Pチャンネル領域
35:幅狭トレンチ分離(STI)領域
40:ゲート構成体
50,52:側壁スペーサ
60,62:ソース及びドレイン領域
61,63:傾斜型上部接触表面
70:コンタクト
80:軽度にドープしたドレイン/ソース延長部領域
Claims (20)
- 半導体装置において、
チャンネル領域を具備する半導体基板、
前記チャンネル領域上方のゲート構成体、
前記ゲート構成体の両側のソース及びドレイン領域、
前記ソース及びドレイン領域の各々の上の夫々のコンタクト、
を有しており、前記ソース及びドレイン領域の内の少なくとも一方が前記夫々のコンタクトとの傾斜型上部接触表面を具備している,半導体装置。 - 請求項1において、
前記傾斜型上部接触表面が前記ゲート構成体から離れるに従い下方へ傾斜している、
半導体装置。 - 請求項1において、
前記傾斜型上部接触表面が30〜45度の範囲内の角度で傾斜している、
半導体装置。 - 請求項1において、
前記ソース及びドレイン領域が夫々の隆起型ソース及びドレイン領域を有している、半導体装置。 - 請求項1において、
前記傾斜型上部接触表面が対応する平坦な接触表面の場合よりも少なくとも50%一層大きな面積を有している
半導体装置。 - 請求項1において、
前記ゲート構成体が、ゲートスタックと、前記ゲートスタックの両側の少なくとも1個の側壁スペーサと、を有している、
半導体装置。 - 請求項6において、
前記ゲートスタックが、チャンネル領域に隣接した誘電体層と、前記誘電体層上の導電層と、を有している、
半導体装置。 - 相補的金属酸化物半導体(CMOS)半導体装置において、
Pチャンネル領域とNチャンネル領域とを具備している半導体基板、
前記Pチャンネル及びNチャンネル領域上方の夫々のゲート構成体、
各ゲート構成体の両側の夫々のソース及びドレイン領域、
前記ソース及びドレイン領域の各々上の夫々のコンタクト、
を有しており、前記ソース及びドレイン領域の内の少なくとも一方が前記夫々のコンタクトとの傾斜型上部接触表面を具備しており、前記傾斜型上部接触表面は30〜45度の範囲内の角度において前記ゲート構成体から離れるに従い下方へ傾斜している、
CMOS半導体装置。 - 請求項8において、
前記夫々のソース及びドレイン領域が夫々の隆起型ソース及びドレイン領域を有している、
CMOS半導体装置。 - 請求項8において、
前記傾斜型上部接触表面が対応する平坦な接触表面の場合よりも少なくとも50%一層大きな面積を有している、
CMOS半導体装置。 - 請求項8において、
各ゲート構成体が、ゲートスタックと、前記ゲートスタックの両側の少なくとも1個の側壁スペーサと、を有している、
CMOS半導体装置。 - 請求項11において、
各ゲートスタックが、チャンネル領域に隣接した誘電体層と、前記誘電体層上の導電層と、を有している、
CMOS半導体装置。 - 半導体装置を製造する方法において、
チャンネル領域を具備する半導体基板を用意し、
前記チャンネル領域上方にゲート構成体を形成し、
前記ゲート構成体の両側にソース及びドレイン領域を形成し、
前記ソース及びドレイン領域の各々の上に夫々のコンタクトを形成する、
ことを包含しており、前記ソース及びドレイン領域の内の少なくとも一方が夫々のコンタクトとの傾斜型上部接触表面を具備している、
方法。 - 請求項13において、
前記傾斜型上部接触表面を形成することがエッチングステップを包含している、
方法。 - 請求項13において、
前記傾斜型上部接触表面が前記ゲート構成体から離れるに従い下方へ傾斜している、
方法。 - 請求項13において、
前記傾斜型上部接触表面が30〜45度の範囲内の角度で傾斜している、
方法。 - 請求項13において、
前記ソース及びドレイン領域が夫々の隆起型ソース及びドレイン領域を包含している、
方法。 - 請求項17において、
前記夫々の隆起型ソース及びドレイン領域を形成することが、前記半導体基板上にエピタキシャル層を形成することを包含している、
方法。 - 請求項13において、
前記傾斜型上部接触表面が対応する平坦な接触表面の場合よりも少なくとも50%一層大きな面積を有している、
方法。 - 請求項13において、
前記ゲート構成体が、ゲートスタックと、前記ゲートスタック両側の少なくとも1個の側壁スペーサと、を有している、
方法。
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US13/590,548 US9012999B2 (en) | 2012-08-21 | 2012-08-21 | Semiconductor device with an inclined source/drain and associated methods |
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US9679978B2 (en) | 2015-09-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US9871042B2 (en) | 2015-12-03 | 2018-01-16 | Samsung Electronics Co., Ltd. | Semiconductor device having fin-type patterns |
US9887289B2 (en) | 2015-12-14 | 2018-02-06 | International Business Machines Corporation | Method and structure of improving contact resistance for passive and long channel devices |
CN106952918A (zh) * | 2016-01-05 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 分离栅快闪存储器的制备方法 |
US9929271B2 (en) * | 2016-08-03 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10825897B2 (en) | 2019-01-30 | 2020-11-03 | Globalfoundries Inc. | Formation of enhanced faceted raised source/drain EPI material for transistor devices |
US10777642B2 (en) * | 2019-01-30 | 2020-09-15 | Globalfoundries Inc. | Formation of enhanced faceted raised source/drain epi material for transistor devices |
CN113889526B (zh) * | 2021-09-30 | 2024-04-26 | 合肥鑫晟光电科技有限公司 | 薄膜晶体管、显示基板及显示基板的制备方法 |
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CN108538787B (zh) | 2022-12-23 |
CN108538787A (zh) | 2018-09-14 |
JP6249666B2 (ja) | 2017-12-20 |
CN203721725U (zh) | 2014-07-16 |
EP2701196A2 (en) | 2014-02-26 |
EP2701196A3 (en) | 2017-04-26 |
CN103632937A (zh) | 2014-03-12 |
US9012999B2 (en) | 2015-04-21 |
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