JP2013229470A - 半導体装置及びそのレイアウト方法 - Google Patents

半導体装置及びそのレイアウト方法 Download PDF

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Publication number
JP2013229470A
JP2013229470A JP2012100976A JP2012100976A JP2013229470A JP 2013229470 A JP2013229470 A JP 2013229470A JP 2012100976 A JP2012100976 A JP 2012100976A JP 2012100976 A JP2012100976 A JP 2012100976A JP 2013229470 A JP2013229470 A JP 2013229470A
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JP
Japan
Prior art keywords
wiring
region
pattern
widened
intersecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
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JP2012100976A
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English (en)
Japanese (ja)
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JP2013229470A5 (https=
Inventor
Shuichi Nagase
修一 永瀬
Hisashi Nagamine
久之 長峰
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PS4 Luxco SARL
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PS4 Luxco SARL
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Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Priority to JP2012100976A priority Critical patent/JP2013229470A/ja
Priority to US13/800,782 priority patent/US9059165B2/en
Publication of JP2013229470A publication Critical patent/JP2013229470A/ja
Publication of JP2013229470A5 publication Critical patent/JP2013229470A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H10W20/432—Layouts of interconnections comprising crossing interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2012100976A 2012-04-26 2012-04-26 半導体装置及びそのレイアウト方法 Withdrawn JP2013229470A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012100976A JP2013229470A (ja) 2012-04-26 2012-04-26 半導体装置及びそのレイアウト方法
US13/800,782 US9059165B2 (en) 2012-04-26 2013-03-13 Semiconductor device having mesh-pattern wirings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012100976A JP2013229470A (ja) 2012-04-26 2012-04-26 半導体装置及びそのレイアウト方法

Publications (2)

Publication Number Publication Date
JP2013229470A true JP2013229470A (ja) 2013-11-07
JP2013229470A5 JP2013229470A5 (https=) 2015-05-28

Family

ID=49476576

Family Applications (1)

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JP2012100976A Withdrawn JP2013229470A (ja) 2012-04-26 2012-04-26 半導体装置及びそのレイアウト方法

Country Status (2)

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US (1) US9059165B2 (https=)
JP (1) JP2013229470A (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102349417B1 (ko) 2015-07-16 2022-01-10 삼성전자 주식회사 전압 강하를 개선할 수 있는 구조를 갖는 반도체 장치와 이를 포함하는 장치
JP7200066B2 (ja) * 2019-08-22 2023-01-06 ルネサスエレクトロニクス株式会社 半導体装置
KR20220015207A (ko) * 2020-07-30 2022-02-08 에스케이하이닉스 주식회사 반도체 장치
KR102879037B1 (ko) 2020-08-19 2025-10-29 삼성전자주식회사 복수개의 패턴들을 포함하는 반도체 소자

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410107A (en) * 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
JP2001127162A (ja) 1999-10-25 2001-05-11 Matsushita Electric Ind Co Ltd 半導体集積回路

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Publication number Publication date
US20130285258A1 (en) 2013-10-31
US9059165B2 (en) 2015-06-16

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