JP2013225352A - フラッシュメモリデバイス - Google Patents
フラッシュメモリデバイス Download PDFInfo
- Publication number
- JP2013225352A JP2013225352A JP2013164952A JP2013164952A JP2013225352A JP 2013225352 A JP2013225352 A JP 2013225352A JP 2013164952 A JP2013164952 A JP 2013164952A JP 2013164952 A JP2013164952 A JP 2013164952A JP 2013225352 A JP2013225352 A JP 2013225352A
- Authority
- JP
- Japan
- Prior art keywords
- memory device
- data
- memory
- controller
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
- G06F13/426—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
Abstract
【解決手段】メモリシステムは、デイジーチェーン方式で結合されたコントローラ、および多数の連続メモリデバイスからなる対応するストリングを含む。コントローラは、直列制御リンクを介してコマンドを伝達して、第1のメモリデバイスを、チェーン中の第2のメモリデバイスにデータブロックを書き込むように構成する。たとえば、コントローラは、デイジーチェーン制御リンクを介して通信して、多数のメモリデバイスのうち第1のメモリデバイスを、データを出力するソースとなるように構成し、デイジーチェーン制御リンクを介して通信して、第2のメモリデバイスを、データを受信する移動先となるように構成し、デイジーチェーン制御リンクを介して通信して、第1のメモリデバイスから第2のメモリデバイスへのデータの転送を開始することによって、データブロックのコピーを開始する。
【選択図】図1A
Description
31 ECC&バッファメモリブロック
40 コントローラ
50 コントローラ
100 メモリシステム
102 コントローラ
109 エラー検査モジュール
110 メモリデバイス
115 コアメモリ
118 バッファ
125 制御/データ処理(C.A.D.P.)回路
140 アクセス制御モジュール
150 制御リンク
151 通信経路
160 データリンク
162 デイジーチェーン通信リンク
200 メモリシステム
205 基板
300 メモリデバイス
301 メモリデバイス
302 メモリデバイス
303 メモリデバイス
304 メインクロック信号
321 経路
323 デイジーチェーン式データリンク経路
324 経路
325 経路
400 メモリデバイス
401 メモリデバイス
402 メモリデバイス
403 メモリデバイス
500 メモリデバイス
501 メモリデバイス
502 メモリデバイス
510 同期装置回路
600 メモリシステム
601 同形データパケット
602 同形データパケット
606 書込みデータパケット
1112 メモリシステム
1113 プロセッサ
1131 通信インタフェース
Claims (1)
- データを格納するためのメモリと、
バッファと、
上流メモリデバイスからデータを受信する入力と、
下流メモリデバイスにデータを送信する出力と、
前記入力と前記出力との間の回路機構であって、遠隔ソースから構成コマンドを受信し、前記遠隔ソースによる対応するモードの選択に基づいて、前記入力を監視し、前記バッファへの格納のために前記上流メモリデバイスからデータを受信するように構成された回路機構とを備える
メモリデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/897,105 | 2007-08-29 | ||
US11/897,105 US20090063786A1 (en) | 2007-08-29 | 2007-08-29 | Daisy-chain memory configuration and usage |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010522146A Division JP2010537326A (ja) | 2007-08-29 | 2008-08-27 | デイジーチェーンメモリの構成および使用 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2013225352A true JP2013225352A (ja) | 2013-10-31 |
Family
ID=40386615
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010522146A Pending JP2010537326A (ja) | 2007-08-29 | 2008-08-27 | デイジーチェーンメモリの構成および使用 |
JP2013164952A Pending JP2013225352A (ja) | 2007-08-29 | 2013-08-08 | フラッシュメモリデバイス |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010522146A Pending JP2010537326A (ja) | 2007-08-29 | 2008-08-27 | デイジーチェーンメモリの構成および使用 |
Country Status (8)
Country | Link |
---|---|
US (1) | US20090063786A1 (ja) |
EP (1) | EP2183748A4 (ja) |
JP (2) | JP2010537326A (ja) |
KR (1) | KR101507192B1 (ja) |
CN (1) | CN101836258A (ja) |
CA (1) | CA2695396A1 (ja) |
TW (1) | TW200931266A (ja) |
WO (1) | WO2009026696A1 (ja) |
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2008
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- 2008-08-27 EP EP08783415A patent/EP2183748A4/en not_active Withdrawn
- 2008-08-27 CN CN200880112684A patent/CN101836258A/zh active Pending
- 2008-08-27 KR KR1020107006531A patent/KR101507192B1/ko not_active IP Right Cessation
- 2008-08-27 JP JP2010522146A patent/JP2010537326A/ja active Pending
- 2008-08-27 CA CA2695396A patent/CA2695396A1/en not_active Abandoned
- 2008-08-27 WO PCT/CA2008/001512 patent/WO2009026696A1/en active Application Filing
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2013
- 2013-08-08 JP JP2013164952A patent/JP2013225352A/ja active Pending
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Also Published As
Publication number | Publication date |
---|---|
CN101836258A (zh) | 2010-09-15 |
CA2695396A1 (en) | 2009-03-05 |
JP2010537326A (ja) | 2010-12-02 |
US20090063786A1 (en) | 2009-03-05 |
EP2183748A4 (en) | 2011-04-06 |
KR101507192B1 (ko) | 2015-03-31 |
EP2183748A1 (en) | 2010-05-12 |
KR20100075860A (ko) | 2010-07-05 |
WO2009026696A1 (en) | 2009-03-05 |
TW200931266A (en) | 2009-07-16 |
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