JP2013207132A - 半導体パッケージおよびその製造方法 - Google Patents
半導体パッケージおよびその製造方法 Download PDFInfo
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- JP2013207132A JP2013207132A JP2012075518A JP2012075518A JP2013207132A JP 2013207132 A JP2013207132 A JP 2013207132A JP 2012075518 A JP2012075518 A JP 2012075518A JP 2012075518 A JP2012075518 A JP 2012075518A JP 2013207132 A JP2013207132 A JP 2013207132A
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Abstract
【解決手段】半導体パッケージ100は、表面に表面電極、裏面に裏面電極を有する半導体チップと、半導体チップとの間の少なくとも一部に空隙を有し、表面側貫通電極を有し、半導体チップの表面側に位置する表面側キャップ26部と、第1のキャップ部と接合されることで半導体チップを封止し、半導体チップとの間の少なくとも一部に空隙を有し、裏面側貫通電極を有し、半導体チップの裏面側に位置する裏面側キャップ部36と、表面電極と表面側貫通電極とを電気的に接続する表面側接続部と、裏面電極と裏面側貫通電極とを電気的に接続する裏面側接続部と、を備える。
【選択図】図1
Description
裏面側接続部54aを備える。そして、第2の裏面電極20と第2の裏面側貫通電極34とを電気的に接続する第2の裏面側接続部54bを備える。
実施例1は、高抵抗シリコンを用いて表面側キャップ部、裏面側キャップ部を形成したX帯周波数対応MMICチップのパッケージ構成例を示す。図9は、実施例1の半導体パッケージの模式断面図と評価結果である。図9(a)が半導体パッケージ100の模式断面図、図9(b)が入出力端子間の高周波信号の挿入損失に関する評価結果を示す図である。
実施例2は、2種の異なる厚みを持つ半導体チップに対するパッケージ構成例を示す。本実施例のプロセス工程は、キャップ部の形状と裏面側キャップ部のD−RIE深さに差が設けられている点を除き、実施例1と基本的に同様である。
厚さの薄い第2の半導体チップ12側の裏面側キャップ部36が厚くなるよう凹部を形成し、D−RIE深さに差を設けることで、異なる深さの第1および第2の裏面側貫通電極32、34を形成する。その後、表面側キャップ部26と裏面側キャップ部36とを接合する。
実施例3は、2種の異なる厚みを持つ半導体チップに対する別のパッケージ構成例を示す。厚みの異なるチップの薄い方の接続に、感光性樹脂による貫通孔を形成した例を示す。実施例3のプロセス工程は、感光性樹脂のパターニング、およびその貫通孔への導電性材料の充填の工程を除き、実施例1と基本的に同様である。
厚さの薄い第2の半導体チップ12の裏面電極20側に、感光性樹脂82aのパターニング、貫通孔の形成およびの導電材82bの充填を行う。その後、表面側キャップ部26と裏面側キャップ部36とを接合する。
実施例4は、実施例1の半導体パッケージ100が、他の半導体チップとともに、非感光性樹脂による再構築工程を施し、再構築した実施例を示す。この構造は、いわゆる疑似SOC構造である。実施例4のプロセス工程は、同再構築工程を除き、実施例1と基本的に同様である。
12 第2の半導体チップ
14a 第1の表面電極
14b 第1の表面電極
16 第1の裏面電極
18a 第2の表面電極
18b 第2の表面電極
20 第2の裏面電極
22a 第1の表面側貫通電極
22b 第1の表面側貫通電極
24a 第2の表面側貫通電極
24b 第2の表面側貫通電極
26 表面側キャップ部
28 中空部
32 第1の裏面側貫通電極
34 第2の裏面側貫通電極
50a 第1の表面側接続部
50b 第1の表面側接続部
52a 第2の表面側接続部
52b 第2の表面側接続部
54a 第1の裏面側接続部
54b 第2の裏面側接続部
60 第1のウェハ
70 第2のウェハ
Claims (10)
- 表面に表面電極、裏面に裏面電極を有する半導体チップと、
前記半導体チップとの間の少なくとも一部に空隙を有し、表面側貫通電極を有し、前記半導体チップの表面側に位置する表面側キャップ部と、
前記第1のキャップ部と接合されることで前記半導体チップを封止し、前記半導体チップとの間の少なくとも一部に空隙を有し、裏面側貫通電極を有し、前記半導体チップの裏面側に位置する裏面側キャップ部と、
前記表面電極と前記表面側貫通電極とを電気的に接続する表面側接続部と、
前記裏面電極と前記裏面側貫通電極とを電気的に接続する裏面側接続部と、
を備えることを特徴とする半導体パッケージ。 - 前記半導体チップが高周波用半導体チップであることを特徴とする請求項1記載の半導体パッケージ。
- 前記表面側キャップ部および前記裏面側キャップ部の材質の少なくとも一部がシリコンであることを特徴とする請求項1または請求項2記載の半導体パッケージ。
- 前記裏面側接続部と、前記裏面電極との間に、さらに樹脂と前記樹脂を貫通する導電材で形成される接続部材を有することを特徴とする請求項1ないし請求項3いずれか一項記載の半導体パッケージ。
- 前記表面側貫通電極および前記裏面側貫通電極が、銅(Cu)を含有することを特徴とする請求項1ないし請求項4いずれか一項記載の半導体パッケージ。
- 表面に第1の表面電極、裏面に第1の裏面電極を有する第1の半導体チップと、
表面に第2の表面電極、裏面に第2の裏面電極を有する第2の半導体チップと、
前記第1および第2の半導体チップとの間の少なくとも一部に空隙を有し、第1および第2の表面側貫通電極を有し、前記第1および第2の半導体チップの表面側に位置する表面側キャップ部と、
前記表面側キャップ部と接合されることで前記第1および第2の半導体チップを同一の中空部に封止し、前記第1および第2の半導体チップとの間の少なくとも一部に空隙を有し、第1および第2の裏面側貫通電極を有し、前記第1および第2の半導体チップの裏面側に位置する裏面側キャップ部と、
前記第1および第2の表面電極と前記第1および第2の表面側貫通電極とをそれぞれ電気的に接続する第1および第2の表面側接続部と、
前記第1および第2の裏面電極と前記第1および第2の裏面側貫通電極とを電気的に接続する第1および第2の裏面側接続部と、
を備えることを特徴とする半導体パッケージ。 - 前記第2の半導体チップの厚さが前記第1の半導体チップよりも薄く、前記第2の裏面側接続部と、前記第2の裏面電極との間に、さらに樹脂と前記樹脂を貫通する導電材で形成される接続部材を有することを特徴とする請求項6記載の半導体パッケージ。
- 第1のウェハに複数の第1の貫通電極を形成する工程と、
前記第1のウェハ上に、表面に表面電極、裏面に裏面電極を有する複数の半導体チップを、前記表面電極が導電性の第1の接続部を介して前記第1の貫通電極に接続され、前記第1のウェハとの間の少なくとも一部に空隙を有するよう実装する工程と、
第2のウェハに複数の第2の貫通電極を形成する工程と、
前記裏面電極が導電性の第2の接続部を介して前記第2の貫通電極に接続され、前記半導体チップと前記第2のウェハとの間の少なくとも一部に空隙を有し、複数の前記半導体チップがそれぞれ別個の中空部に封止されるよう前記第1のウェハと前記第2のウェハとを接合する工程と、
接合された前記第1および第2のウェハをダイシングすることにより封止された複数の前記半導体チップを個別化する工程と、
を備える特徴とする半導体パッケージの製造方法。 - 前記第1のウェハまたは前記第2のウェハに、前記半導体チップが実装される領域に対応する凹部を設ける工程をさらに備えることを特徴とする請求項8記載の半導体パッケージの製造方法。
- 前記第1または第2のウェハがシリコンウェハであることを特徴とする請求項8または請求項9記載の半導体パッケージの製造方法。
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US11309249B2 (en) | 2020-05-04 | 2022-04-19 | Nanya Technology Corporation | Semiconductor package with air gap and manufacturing method thereof |
TWI763421B (zh) * | 2020-05-04 | 2022-05-01 | 南亞科技股份有限公司 | 具有氣隙的半導體封裝結構及其製備方法 |
US11817306B2 (en) | 2020-05-04 | 2023-11-14 | Nanya Technology Corporation | Method for manufacturing semiconductor package with air gap |
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US20130256864A1 (en) | 2013-10-03 |
JP5813552B2 (ja) | 2015-11-17 |
US9041182B2 (en) | 2015-05-26 |
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