JP2013183104A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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Abstract
【解決手段】ドレイン電極40は、半導体素子30の上面に形成され、ソース電極50およびゲート電極60は、半導体素子30の下面に形成されている。脚部80,81,82,83は、絶縁性を有する。配線基板90には、脚部80,81,82,83が接触する状態で半導体素子30が搭載される。接合材S1,S2は、脚部80,81,82,83が配線基板90に接触することによりソース電極50およびゲート電極60と配線基板90との間に形成された空隙に配置され、ソース電極50およびゲート電極60と配線基板90とを接合する。
【選択図】図1
Description
請求項3に記載のように、請求項1または2に記載の半導体装置において、前記半導体素子を前記配線基板に搭載したとき前記配線基板と係合する位置決め用部材を更に備えると、半導体素子を配線基板に搭載したとき位置決め用部材が配線基板と係合して位置決めすることができる。
なお、図面において、水平面を、直交するX,Y方向で規定するとともに、上下方向をZ方向で規定している。
半導体デバイス20は、半導体素子30と、上部電極としてのドレイン電極40と、下部電極としてのソース電極50およびゲート電極60と、モールド樹脂70を備えている。
図3において半導体デバイス20は、半導体素子30の下面にソース電極50およびゲート電極60が形成されているとともに半導体素子30の上面にドレイン電極40が形成され、モールド樹脂70により封止されている。配線基板90の上において、ソース電極50とゲート電極60が下になる状態で配置される。
次に、半導体装置10の製造方法について説明する。
そして、ソース電極50と配線基板90との間の空隙G1に、接合材(はんだ等)S1を配置して接合材S1によりソース電極50と配線基板90とを接合する。同様に、ゲート電極60と配線基板90との間の空隙G2に、接合材(はんだ等)S2を配置して接合材S2によりゲート電極60と配線基板90とを接合する。
配線基板90に半導体デバイス20を載せたときにソースパッド51とゲートパッド61が同時に配線基板90に当接せずにガタガタする場合がある(ちゃんと座らない)。これに対し本実施形態では、電極部分の端面(パッド51,61)が合っていなくても(電極50,60の下面の形状によらず)半導体素子30を配線基板90に対して平行(または任意の状態)に置くことが可能となる。ソース電極50とゲート電極60は少し隙間(空隙G1,G2)が空いており、この隙間(空隙G1,G2)には接合材(はんだS1,S2)が配されて接合される。
このように、脚部80,81,82,83を利用して配線基板90への位置決めが可能となる。つまり、樹脂成型時に脚部80,81,82,83が形成され、脚部80,81,82,83により半導体素子30の縦方向(Z方向)の位置が決定されるため、ソース電極50の加工精度によらず、半導体素子30を配線基板90に対して平行(または任意の位置)に搭載することが可能となる。
(1)半導体装置10の構成として、半導体素子30と、上部電極としてのドレイン電極40と、下部電極としてのソース電極50およびゲート電極60と、脚部80,81,82,83と、配線基板90と、接合材S1,S2と、を備える。ドレイン電極40は、半導体素子30の上面に形成され、ソース電極50およびゲート電極60は、半導体素子30の下面に形成されている。脚部80,81,82,83は、絶縁性を有する。配線基板90には、脚部80,81,82,83が接触する状態で半導体素子30が搭載される。接合材S1,S2は、脚部80,81,82,83が配線基板90に接触することによりソース電極50およびゲート電極60と配線基板90との間に形成された空隙G1,G2に配置され、ソース電極50およびゲート電極60と配線基板90とを接合する。
(3)半導体素子30を配線基板90に搭載したとき配線基板90と係合する位置決め用部材としての位置決め突起84を更に備える。よって、半導体素子30を配線基板90に搭載したとき位置決め突起84が配線基板90と係合して容易に位置決めすることができる。
・図1に代わり図5に示すように位置決め用部材としての脚部(ピン)85を設けて脚部(ピン)85により位置決めを行ってもよい。つまり、2本の脚部(ピン)85が配線基板90への位置決めを担い、横方向、即ち、X,Y方向の位置を決める脚部(ピン)85と縦方向、即ち、Z方向の位置を決める脚部80,81,82,83を持つ構成としてもよい。
・半導体素子はMOSFETであったが、これに限ることはなく、他にも例えばIGBT、ダイオード等であってもよい。
Claims (3)
- 半導体素子と、
前記半導体素子の上面に形成された上部電極と、
前記半導体素子の下面に形成された下部電極と、
絶縁性を有する脚部と、
前記脚部が接触する状態で前記半導体素子が搭載された配線基板と、
前記脚部が前記配線基板に接触することにより前記下部電極と前記配線基板との間に形成された空隙に配置され、前記下部電極と前記配線基板とを接合する接合材と、
を備えることを特徴とする半導体装置。 - 前記脚部は、前記半導体素子を封止する樹脂に一体形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体素子を前記配線基板に搭載したとき前記配線基板と係合する位置決め用部材を更に備えたことを特徴とする請求項1または2に記載の半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016082169A (ja) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | 電子装置 |
JP2019091915A (ja) * | 2017-03-08 | 2019-06-13 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002246512A (ja) * | 2001-02-16 | 2002-08-30 | Nec Corp | Bgaパッケージの構造及び実装基板の構造 |
JP2006222121A (ja) * | 2005-02-08 | 2006-08-24 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006245434A (ja) * | 2005-03-04 | 2006-09-14 | Seiko Epson Corp | 配線基板上に面実装される電子部品、面実装される電子部品を有する回路、及び、印刷装置 |
-
2012
- 2012-03-02 JP JP2012047220A patent/JP2013183104A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002246512A (ja) * | 2001-02-16 | 2002-08-30 | Nec Corp | Bgaパッケージの構造及び実装基板の構造 |
JP2006222121A (ja) * | 2005-02-08 | 2006-08-24 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006245434A (ja) * | 2005-03-04 | 2006-09-14 | Seiko Epson Corp | 配線基板上に面実装される電子部品、面実装される電子部品を有する回路、及び、印刷装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016082169A (ja) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | 電子装置 |
JP2019091915A (ja) * | 2017-03-08 | 2019-06-13 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |
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