CN107591384B - 半导体模块 - Google Patents

半导体模块 Download PDF

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CN107591384B
CN107591384B CN201710536536.9A CN201710536536A CN107591384B CN 107591384 B CN107591384 B CN 107591384B CN 201710536536 A CN201710536536 A CN 201710536536A CN 107591384 B CN107591384 B CN 107591384B
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bus bar
semiconductor element
wiring pattern
semiconductor
semiconductor module
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CN107591384A (zh
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加藤直毅
森昌吾
佐藤晴光
渡边大城
汤口洋史
西村幸史
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Toyota Industries Corp
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Abstract

本发明涉及半导体模块。半导体模块具备布线基板和安装于布线基板的2个半导体元件。半导体模块具备壳体,该壳体具有包含4个侧壁的四边框状的框体。壳体具备在第1侧壁之间架设的梁。汇流条具备:一对端部、从各端部在绝缘基板的板厚方向上立设的立设部、与立设部连续的弯折部、与弯折部连续的延设部。延设部的一部分埋设于壳体。

Description

半导体模块
技术领域
本发明涉及半导体模块。
背景技术
在半导体元件接合了汇流条的半导体模块,例如在专利文献1中被公开。日本特开昭59-208736号公报所公开的半导体模块,具备与壳一体化的汇流条。根据该结构,在向半导体元件接合汇流条时,进行壳的定位。此时,也进行与壳一体化的汇流条的定位。在该状态下,在半导体元件接合汇流条。
在上述文献所公开的半导体模块中,接合汇流条时,半导体元件容纳于壳体。因此,无法目视汇流条的接合部。
发明内容
本发明的目的在于提供一种即使在安装了壳体后也能够目视汇流条的接合部的半导体模块。
为了解决上述问题,根据本发明的第一技术方案,具备:布线基板,其在绝缘基板配置有布线图案;半导体元件,其与布线图案连接;板状的汇流条,其具有与布线图案或半导体元件接合的至少1个端部;以及树脂制的壳体,其具有包围布线图案以及半导体元件的框体,并与汇流条一体化。汇流条具备:立设部,其从端部在绝缘基板的板厚方向上立设;弯折部,其与立设部连续,使汇流条向与板厚方向交叉的方向弯折;以及延设部,其与弯折部连续,并具有埋设于壳体的部分。壳体在与汇流条的端部和布线图案或半导体元件的接合部对应的位置具备目视用的开口部。
附图说明
图1是示出本发明的半导体模块的一个实施方式中省略了灌封树脂的状态的立体图。
图2是省略了灌封树脂的状态的半导体模块的俯视图。
图3是沿着图2的3-3线的截面图。
图4是沿着图3的4-4线的截面图。
图5是变形例的半导体模块的局部截面图。
图6是变形例的半导体模块的局部截面图。
图7是示出变形例的汇流条的局部立体图。
图8是示出变形例的汇流条的端部的局部截面图。
具体实施方式
以下,参照图1~图4对本发明的将半导体模块具体化的一个实施方式进行说明。在以下的说明中,如图1~图8所示那样分别进行定义了X、Y、Z各方向。另外,以下将Z方向记载为上下方向。
如图1以及图2所示,半导体模块10具备布线基板11和安装于布线基板11的2个半导体元件21、31。布线基板11具备绝缘基板12和位于绝缘基板12的上表面13的布线图案14、15。布线图案14、15设置在分别与半导体元件21、31对应的位置。半导体元件21、31由例如Si(硅)、SiC(炭化硅)形成。
如图3所示,半导体元件21、31是裸芯片。在各半导体元件21、31的下表面,分别形成有第1电极(接合区(land,触点))22、32。半导体元件21、31,在与第1电极22相反侧具有上表面,在半导体元件21、31的上表面,分别形成有第2电极(接合区)23、33。以下,将半导体元件21、31中的一方设为第1半导体元件21,将另一方设为第2半导体元件31。第1半导体元件21是IGBT(绝缘栅双极型晶体管)。第1半导体元件21中的第1电极22是集电极,第2电极23是发射电极。第1半导体元件21具备未图示的栅电极。第2半导体元件31是二极管。第2半导体元件31中的第1电极32是阴电极,第2电极33是阳电极。
布线图案14与第1半导体元件21的第1电极22接合。布线图案15与第2半导体元件31的第1电极32接合。由此,布线图案14、15分别与半导体元件21、31电连接。
如图1以及图2所示,半导体模块10具备树脂制的壳体41。壳体41具备包括4个侧壁43、44的四边框状的框体42。将4个侧壁43、44中在X方向上相对向的2个侧壁43设为第1侧壁43,在Y方向上相对向的2个侧壁44设为第2侧壁44。壳体41具备架设在2个第1侧壁43之间的梁45。壳体41在梁45的两侧具备开口部46、47。壳体41配置在绝缘基板12的上表面。从Z方向观察,梁45位于第1半导体元件21与第2半导体元件31之间的位置。Z方向与绝缘基板12的板厚方向相同。
如图3所示,半导体模块10具备板状的汇流条51。汇流条51通过将金属板弯折而形成。汇流条51具备延设部52、弯折部55、56、立设部57、58。延设部52具备矩形平板状的连结部53和从连结部53突出的突出部54。连结部53具有在连结部53的板厚方向上配置的一对表面和与两表面交叉的一对侧面。突出部54从连结部53的两侧面中的一方突出,向连结部53的板厚方向的上方延伸。汇流条51具有以连结部53的长边方向的中央为中心的对称构造。
弯折部55、56在连结部53的两端分别设置。各弯折部55、56与连结部53连续,汇流条51在弯折部55、56呈直角地弯折。立设部57与弯折部55连续,立设部58与弯折部56连续。各立设部57、58在连结部53的板厚方向并向突出部54的相反侧的下方延伸。
如图4所示,汇流条51还具有与立设部57、58连续的端部59、60。两端部59、60被倒角。由此,端部59、60的X方向的尺寸即宽度,随着靠近各顶端面61、62而变小。图4示出立设部57以及端部59的截面,立设部58以及端部60的截面形状也与立设部57以及端部59相同。因此,使用图4,对立设部57、58以及端部59、60进行说明。
端部59的顶端面61与第1半导体元件21的第2电极23对接。端部60的顶端面62与第2半导体元件31的第2电极33对接。端部59,通过焊料71与第1半导体元件21的第2电极23接合。端部60,通过焊料72与第2半导体元件31的第2电极33接合。即,汇流条51具备与半导体元件21、31接合的多个端部59、60。焊料71、72是从顶端面61、62朝向第2电极23、33扩展的内圆角形状(フィレット形状)。焊料71、72成为将端部59、60与半导体元件21、31接合的接合部。端部59、60的顶端面61、62与汇流条51的两表面交叉,并且与绝缘基板12的板厚方向正交。
如图3所示,汇流条51的各端部59、60与各半导体元件21、31接合,由此,立设部57、58在Z方向上立设。汇流条51,在弯折部55、56,相对于立设部57、58,向与绝缘基板12的板厚方向交叉的方向弯折。在此,汇流条51在弯折部55、56,向与绝缘基板12的板厚方向正交的Y方向弯折。突出部54以离开绝缘基板12的方式延伸,向壳体41的外侧突出。
如图1所示,延设部52的一部分埋设于壳体41。即,连结部53中设置有突出部54的部分和突出部54的基端被埋设于梁45。连结部53在Y方向上贯通梁45。由此,成为延设部52的一部分的连结部53,从梁45的端面45a突出,并向各开口部46、47的内侧突出。梁45的端面45a是划分开口部46、47的面,连结部53跨及两个开口部46、47。突出部54从梁45的上表面向壳体41的外侧突出。
延设部52的一部分被埋设,由此,汇流条51与壳体41一体化。延设部52是汇流条51中除了端部59、60、立设部57、58以及弯折部55、56外的其余所有部分。
从Z方向观察,立设部57、58以及弯折部55、56配置在连结焊料71、72的线上。在将立设部57、58以及弯折部55、56这双方埋设于梁45的结构的情况下,从Z方向观察,梁45被配置成与焊料71、72重叠。关于这点,在本实施方式中,由于是仅将延设部52埋设于梁45的结构,因此,从Z方向观察,梁45被配置成不与焊料71、72重叠。在该情况下,从Z方向观察,开口部46配置在焊料71的上方,开口部47配置在焊料72的上方。即,开口部46、47设置在与焊料71、72分别对应的位置。
如图3以及图4所示,壳体41的内部空间被灌封树脂81密封。为了方便说明,在图1以及图2中,省略了灌封树脂81。
接下来,对本实施方式的半导体模块10的作用进行说明。
在制造半导体模块10的过程中,首先,向各半导体元件21、31的第2电极23、33涂敷焊膏。接下来,进行汇流条51的定位,以使得汇流条51的端部59、60配置在焊膏上。此时,通过进行壳体41的定位,也进行与壳体41一体化的汇流条51的定位。并且,在利用焊料71、72将汇流条51的端部59、60与半导体元件21、31接合后,向壳体41内填充固化前的灌封树脂81。此时,在进行树脂密封前,通过目视焊料71、72,来确认半导体元件21、31与汇流条51的接合状态。在此,开口部46、47设置在分别与焊料71、72对应的位置。因此,能够从壳体41的开口部46、47目视半导体元件21、31与汇流条51的接合状态。也即是,壳体41具备用于目视半导体元件21、31和汇流条51的接合状态的目视用开口部46、47。
因此,根据上述实施方式,能够得到以下这样的效果。
(1)由于汇流条51和壳体41被一体化,因此,通过将汇流条51与半导体元件21、31接合,使得壳体41安装于布线基板11。根据本实施方式,壳体41具有目视用开口部46、47,因此,即使在将壳体41安装于布线基板11后,也能够目视焊料71、72,能够确认半导体元件21、31与汇流条51的接合状态。
(2)例如,在连结部53贯通梁45的上下各面的情况下,需要将连结部53的长度确保为留有连结部53在上下方向上贯通梁45的尺寸的余量。关于这点,如本实施方式那样,构成为连结部53贯通梁45而从端面45a突出,则能够抑制半导体模块10在上下方向上的大型化。
(3)汇流条51具备与多个半导体元件21、31接合的端部59、60。与分别设置与多个半导体元件21、31接合的汇流条的情况相比,能够简单地构成半导体模块10。另外,通过将汇流条51共用化,能够减少部件个数。
(4)例如,考虑了使汇流条52的端部59、60相对于立设部57、58向横方向弯折,而使端部59、60的表面与第2电极23、33接合。关于这点,在本实施方式中,使汇流条51的顶端面61、62与半导体元件21、31的第2电极23、33对接,而使汇流条51与半导体元件21、31接合。由此,能够减小与半导体元件21、31接合的汇流条51的面积。此外,半导体元件21、31的第2电极(连接盘)23、33的面积,根据与半导体元件21、31接合的汇流条51的面积来决定。因此,如果使与第2电极23、33接合的汇流条51的面积小,则能够抑制第2电极23、33的大型化。
(5)通过将汇流条51的端部59、60倒角,使得随着靠近顶端面61、62,端部59、60的宽度变小。根据该结构,与不对端部59、60倒角的情况相比,能够减小顶端面61、62的面积。在使顶端面61、62与第2电极23、33对接时,以使顶端面61、62的整体与第2电极23、33相对向地配置的方式进行定位。在该情况下,通过使顶端面61、62减小,使得顶端面61、62的整体会容易与第2电极23、33相对向地配置。由此,能够吸收进行壳体41的定位时的公差。
(6)连结部53中设置有突出部54的部分与突出部54的基端被埋设于梁45。当向突出部54施加力时,向突出部54与连结部53的边界部分施加力。关于这点,根据本实施方式,突出部54与连结部53的边界部分被埋设于梁45。因此,能够抑制突出部54以突出部54与连结部53的边界部分为基点而弯曲。另外,由于突出部54难以弯曲,因此,还能够抑制向半导体元件21、31以及焊料71、72施加应力。另外,在力被传递至连结部53时,应力在弯折部55、56被缓和,由此也能够抑制向半导体元件21、31以及焊料71、72施加应力。
(7)汇流条51的端部59、60被倒角,因此,焊料71、72容易成为内圆角形状。
(8)汇流条51的突出部54向壳体41的外侧突出。根据该结构,在构成变换装置等功率模块时,不使用接合线,而使用布线图案和/或汇流条进行连接,由此能够减少寄生元件。
本实施方式,也可以如下变更。
第1半导体元件21中的第1电极22是集电极,第2电极23是发射电极,但是,也可以使第1半导体元件21面朝下,而相对于布线基板11正反颠倒。
汇流条51弯折成直角,但是,也可以弯折成钝角或锐角。
汇流条51的端部59、60也可以与布线图案14、15接合。另外,也可以是,多个端部59、60中的一部分的端部59、60与半导体元件21、31接合,其余的端部59、60与布线图案14、15接合。
如图5所示,与半导体元件21、31或布线图案14、15接合的端部59、60,也可以是一个。即,汇流条51的至少一个端部59、60与半导体元件21、31或布线图案14、15接合即可。
如图5所示,延设部91也可以具备连结部92、弯折部93、突出部94。弯折部93与连结部92连续,汇流条51在弯折部93弯折后,向壳体41的外侧突出。突出部94是突出到壳体41的外侧的汇流条51的部分。在该情况下,通过使弯折部93埋设于壳体41,能够抑制向半导体元件21、31施加应力。另外,如图6所示,也可以将连结部92埋设于壳体41。
如图7所示,在汇流条51中,与半导体元件21、31或布线图案14、15接合的端部95的数量也可以设为三个以上。
突出部54也可以省略。即,汇流条51仅具备将半导体元件21、31彼此连接、将布线图案14、15彼此连接和/或将半导体元件21、31与布线图案14、15连接的部分即可。
作为被钎焊的部位的端部59、60,也可以不进行倒角。即,端部59、60的宽度,无须随着靠近顶端面61、62而变小。
汇流条51的端部59、60也可以弯折成与立设部57、58呈直角地交叉。在该情况下,汇流条51的端部59、60的表面与第2电极23、33接合。
汇流条51的延设部52也可以埋设于壳体41的侧壁43、44。在该情况下,也可以省略壳体41的梁45。
延设部也可以在上下方向上贯通梁45。
半导体元件也可以是MOSFET等。
梁的数量也可以根据汇流条的数量等适当变更。
延设部52的整体也可以埋设于壳体41。
半导体元件21、31和/或布线图案14、15的数量也可以适当变更。
框体42的形状也可以是四边形以外的多边形形状、圆形等。
也可以省略半导体模块10的灌封树脂81。
开口部46、47设置在能够目视焊料71、72的位置即可。例如,从Z方向观察,开口部46、47设置在从与焊料71、72重叠的位置错开一些的位置即可。即,与焊料71、72(接合部)对应的位置是指能够从开口部46、47目视焊料71、72的位置。
接合部,也可以是焊料以外的导电性材料,例如银糊剂。
如图8所示,第2电极23、33的宽度,例如也可以比汇流条51的端部59、60中宽度最宽的部分的宽度小。该情况下,如果将汇流条51的端部59、60进行倒角,则能够使顶端面61、62的宽度比端部59、60中宽度最宽的部分的宽度小,因此,能够使汇流条51与第2电极23、33接合。

Claims (8)

1.一种半导体模块,具备:
布线基板,其在绝缘基板配置有布线图案;
半导体元件,其与所述布线图案连接;
板状的汇流条,其具有与所述布线图案或所述半导体元件接合的至少1个端部;以及
树脂制的壳体,其具有包围所述布线图案以及所述半导体元件的框体,并与所述汇流条一体化,
所述汇流条具备:
立设部,其从所述端部在所述绝缘基板的板厚方向上立设;
弯折部,其与所述立设部连续,使所述汇流条向与所述板厚方向交叉的方向弯折;以及
延设部,其与所述弯折部连续,并具有埋设于所述壳体的部分,
所述壳体,在与所述汇流条的端部和所述布线图案或所述半导体元件的接合部对应的位置具备目视用的开口部,
所述半导体元件具有与第1布线图案连接的第1半导体元件、和与第2布线图案连接的第2半导体元件,
所述框体具有彼此相对向的两个侧壁、和架设在所述两个侧壁彼此之间的梁,
所述梁,从所述绝缘基板的板厚方向观察,位于所述第1半导体元件与所述第2半导体元件之间或者所述第1布线图案与所述第2布线图案之间,从而将所述开口部划分成位于该梁两侧的两个开口部,
所述立设部具有从接合于所述第1布线图案或所述第1半导体元件的端部在所述绝缘基板的板厚方向上立设的第1立设部、和从接合于所述第2布线图案或所述第2半导体元件的端部在所述绝缘基板的板厚方向上立设的第2立设部,
所述延设部具有与所述弯折部连续的平板状的连结部、和从所述连结部的侧面向所述连结部的板厚方向中的从所述绝缘基板离开的方向延伸且向所述壳体外突出的突出部,所述延设部的至少一部分埋设于所述梁,
所述连结部跨及所述两个开口部,所述第1立设部或所述第2立设部经由所述弯折部分别连续于所述连结部的突出到各开口部内的两端。
2.根据权利要求1所述的半导体模块,
所述汇流条从划分所述开口部的所述壳体的端面向所述开口部的内侧突出。
3.根据权利要求1所述的半导体模块,
所述汇流条具有与所述布线图案或所述半导体元件接合的多个端部。
4.根据权利要求2所述的半导体模块,
所述汇流条具有与所述布线图案或所述半导体元件接合的多个端部。
5.根据权利要求1~4中任一项所述的半导体模块,
所述汇流条的端部,具有与所述布线图案或所述半导体元件对接的顶端面。
6.根据权利要求5所述的半导体模块,
所述汇流条的端部的宽度,随着靠近所述顶端面而变小。
7.根据权利要求1或2所述的半导体模块,
所述连结部中的设置有所述突出部的部分、和所述突出部的基端,埋设于所述梁。
8.根据权利要求1或2所述的半导体模块,
所述汇流条为以所述连结部的延伸方向为中心的对称构造。
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