JP2013110429A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a plurality of active elements or a plurality of passive elements are formed on a single semiconductor substrate, and which can achieve insulation isolation and integration of double-sided electrode elements and which can be manufactured at low cost; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 100 comprises: a semiconductor substrate 20 divided into a plurality of field regions F1-F8 each surrounded by an insulation isolation trench T penetrating the semiconductor substrate 20; and a plurality of active elements 31-33, 41-43 or a plurality of passive elements 51, 52 are arranged in the respective field regions F1-F8 in a dispersed manner. More than one element are double-sided electrode elements 41-43, 51, 52 in which a pair of electrodes dr1, dr2 for energizing the elements are arranged separately on both surfaces S1, S2 of the semiconductor substrate 20.

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a plurality of active elements or passive elements are formed on a single semiconductor substrate.

  A semiconductor device in which a MOS transistor and a bipolar transistor are formed on one semiconductor substrate and a method for manufacturing the same are disclosed in, for example, Japanese Patent Laid-Open No. 2001-60634 (Patent Document 1). FIG. 15 is a diagram schematically showing a cross section of a semiconductor device 90 in the conventional semiconductor device disclosed in Patent Document 1. In FIG.

  A semiconductor device 90 shown in FIG. 15 is a composite IC in which an active element and a passive element are formed on one semiconductor substrate 1. The semiconductor device 90 is a member constituting an automobile controller, and is for driving a load such as a fuel injector (electromagnetic valve). In the semiconductor device 90, an up drain (UpDrain) MOSFET 8, an NPN transistor 9, a CMOS 10, and the like are integrated.

  In the semiconductor device 90 of FIG. 15, an SOI (Silicon On Insulator) substrate 1 is used as a semiconductor substrate. The SOI substrate 1 is manufactured by bonding substrates, and has a configuration in which a thin silicon layer 4 is disposed on a p-type silicon substrate 2 via a silicon oxide film 3. A trench 7 is formed in the silicon layer 4, a silicon oxide film is formed on the inner wall surface thereof, and the trench 7 is filled with polysilicon. Numerous islands are defined by the trenches 7, and nMOS and pMOS constituting the up drain MOSFET 8, the NPN transistor 9, and the CMOS 10 are formed on each island. The up drain (UpDrain) MOSFET 8, the NPN transistor 9, and the CMOS 10 in the semiconductor device 90 each have a set of electrodes for driving these elements arranged together on the surface of the semiconductor substrate 1 on the silicon layer 4 side. A single-sided electrode element.

  As in the semiconductor device 90 shown in FIG. 15, the SOI substrate 1 having the embedded silicon oxide film 3 using substrate bonding is used for various applications such as high speed and high integration of semiconductor elements formed there. It has been.

  On the other hand, the manufacturing cost of the semiconductor device 90 using the SOI substrate 1 by bonding the substrates increases due to an increase in the number of processes from die mounting to mounting on the package. Japanese Laid-Open Patent Publication No. 2001-144173 (Patent Document 2) discloses a method for suppressing an increase in manufacturing cost of a semiconductor device using this bonded substrate. According to the method disclosed in Patent Document 2, it is possible to manufacture a semiconductor device that employs an element isolation structure without using an SOI substrate by bonding substrates, simplifying the manufacturing process, and suppressing an increase in manufacturing cost. can do.

JP 2001-60634 A JP 2001-144173 A

  An SOI substrate having a buried oxide film is suitable for forming single-sided electrode elements as in the semiconductor device 90 shown in FIG. 15, and is insulated and separated by an insulation isolation trench that reaches the buried oxide film. Integration is possible. On the other hand, in an SOI substrate having a buried oxide film, the current in the substrate cross-sectional direction is blocked by the buried oxide film. For this reason, an SOI substrate having a buried oxide film is used for high-current power applications such as a vertical MOS transistor element and an IGBT element, and a pair of electrodes for driving these elements is provided on both sides of the semiconductor substrate. It is not suitable for forming double-sided electrode elements that are dispersed on the surface. Therefore, many of these vertical MOS transistor elements and IGBT elements are formed in one chip, and it is difficult to integrate with other elements, resulting in an increase in manufacturing cost.

  Accordingly, the present invention is a method of manufacturing a semiconductor device in which a plurality of active elements or passive elements are formed on a single semiconductor substrate. The double-sided electrode elements can also be isolated and integrated, and manufactured at low cost. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  First, a semiconductor device to be manufactured according to the present invention will be described.

  A semiconductor device to be manufactured according to the present invention is a semiconductor device in which a plurality of active elements or passive elements using a semiconductor substrate are formed on one semiconductor substrate, and the semiconductor substrate penetrates the semiconductor substrate. A plurality of active elements or passive elements distributed in different field regions, each being surrounded by an insulating isolation trench and divided into a plurality of field regions. Alternatively, among the passive elements, two or more elements are double-sided electrode elements in which a pair of electrodes for energizing the elements are dispersedly arranged on both surfaces of the semiconductor substrate. Yes.

  In the semiconductor device, when realizing an integrated structure composed of a plurality of active elements or passive elements, the semiconductor substrate used in the semiconductor device is not an SOI substrate having a buried oxide film, but a general and inexpensive bulk single crystal. It may be a silicon substrate. The semiconductor substrate is divided into a plurality of field regions surrounded by an insulating isolation trench penetrating the semiconductor substrate, and a plurality of active elements or passive elements are dispersed in these different field regions, respectively. Has been placed. As a result, in the semiconductor device, a plurality of active elements or passive elements are insulated and integrated with each other by an insulating isolation trench penetrating the semiconductor substrate. Further, since the semiconductor substrate may be a bulk single crystal silicon substrate without a buried oxide film, even if the semiconductor substrate is the double-sided electrode element in which two or more active elements or passive elements forming the semiconductor device are formed. Integration is possible. Further, the semiconductor device can be manufactured at low cost by a manufacturing method described later.

  As described above, the semiconductor device is a semiconductor device in which a plurality of active elements or passive elements are formed on one semiconductor substrate, and the double-sided electrode elements formed on two or more are also insulated and integrated. Therefore, an inexpensive semiconductor device can be obtained.

  The semiconductor device can be, for example, a semiconductor device in which a half-bridge circuit is configured, and the semiconductor device has two identical structures composed of vertical MOS transistor elements or IGBT elements as the double-sided electrode elements. The half-bridge circuit is composed of two vertical transistor elements connected in series via another double-sided electrode element, and the two connected in series This can be realized by adopting a configuration in which the output of the half bridge circuit is taken out from the connection point of the vertical transistor elements.

  Therefore, for example, when the semiconductor device is a semiconductor device in which a power module of a three-phase inverter is configured, three sets of the half bridge circuits are configured in the semiconductor device, and the three sets of half What is necessary is just to set it as the structure by which the output of each phase of the said 3-phase inverter is taken out from the connection point of each two said vertical-type transistor elements connected in series in the bridge circuit.

  Alternatively, when the semiconductor device is a semiconductor device in which an H-bridge circuit is configured, two sets of the half-bridge circuits are configured in the semiconductor device, and each of the two sets of half-bridge circuits The output of the H bridge circuit may be taken out from the connection point of the two vertical transistor elements connected in series.

  Further, the semiconductor device can be, for example, a semiconductor device for forming a half bridge circuit by a set of two, and each of the two semiconductor devices has a vertical MOS transistor as the double-sided electrode element. A vertical transistor element having the same structure made up of an element or an IGBT element, and the two semiconductor devices are stacked with one lead interposed therebetween, and the vertical transistor element in the two semiconductor devices This can be realized by connecting the components in series via the leads to form the half-bridge circuit and extracting the output of the half-bridge circuit from the leads.

  Therefore, for example, when the semiconductor device is a semiconductor device for forming a power module of a three-phase inverter as a set of two, each of the semiconductor devices includes three vertical electrodes as the double-sided electrode elements. A configuration in which three sets of half-bridge circuits are configured by two semiconductor devices, and outputs of each phase of the three-phase inverter are extracted from the three leads. do it.

  Alternatively, when the semiconductor device is a semiconductor device for forming an H-bridge circuit by a set of two, each of the semiconductor devices includes the two vertical transistor elements as the double-sided electrode elements. In other words, two sets of the half-bridge circuit may be configured by two semiconductor devices, and the output of the H-bridge circuit may be extracted from the two leads.

  In the semiconductor device, a diode element composed of another double-sided electrode element may be connected in parallel with the vertical transistor element. According to this, the diode element can be used as a free wheel diode (FWD).

  In the semiconductor device, for example, the double-sided electrode element is a power element for electric power use, and at least one of the active element and the passive element in the semiconductor device energizes the element. Is a single-sided electrode element that is arranged together on one surface of the semiconductor substrate, and the single-sided electrode element can be used for controlling the double-sided electrode element. According to this, the semiconductor device can be a composite IC in which a power element for power use and a single-sided electrode element for controlling the power element are formed on one semiconductor substrate.

  The semiconductor device may have a configuration in which, for example, a pair of electrodes of the double-sided electrode element are connected to each other on both sides of the semiconductor substrate, or one side of the semiconductor substrate of the double-sided electrode element may be provided. The electrodes may be connected by wiring provided on the circuit board. When the double-sided electrode element is a power element for power use, the electrode on one side of the semiconductor substrate of the double-sided electrode element is connected to a heat sink provided on the circuit board. You can also.

  The semiconductor device is suitable as a semiconductor device for power use because two or more double-sided electrode elements such as vertical MOS transistor elements and IGBT elements are formed by insulation isolation trenches penetrating the semiconductor substrate. . As will be described later, since the semiconductor device can use a bulk single crystal silicon substrate, when a double-sided electrode element such as a vertical MOS transistor element or IGBT element is formed, a large current and a surge such as ESD are prevented. It is easy to increase the resistance. Further, since there is no buried oxide film, heat dissipation can be improved as compared with a semiconductor device using an SOI substrate.

  As a power application of the semiconductor device, for example, when the above-described three-phase inverter power module is configured as a semiconductor device, the double-sided electrode element in the semiconductor device includes a pair of electrodes for driving the element as a semiconductor. Since these electrodes are distributed and arranged on both surfaces of the substrate, a power module of a three-phase inverter having low loss and high heat dissipation can be obtained by directly connecting these electrodes to a lead frame or a heat sink.

  Therefore, the semiconductor device is suitable as an in-vehicle semiconductor device that requires high breakdown voltage and large current drive.

  The semiconductor substrate in the semiconductor device may be, for example, an epitaxial substrate in which a silicon epitaxial layer is formed on a bulk single crystal silicon substrate.

  The semiconductor substrate in the semiconductor device requires a predetermined substrate thickness in order to ensure a predetermined strength necessary for handling. For example, when forming a double-sided electrode element for power such as a vertical MOS transistor element or an IGBT element, a carrier drift layer having a low impurity concentration is required to achieve a high breakdown voltage. On the other hand, a drift layer having a high impurity concentration is necessary to obtain a low ON resistance element.

  According to the above epitaxial substrate, a double-sided electrode element having a high breakdown voltage or a low ON resistance is obtained by using a bulk single crystal silicon substrate as a support substrate for ensuring strength, and a silicon epitaxial layer in which thickness and impurity concentration are appropriately set as a carrier drift layer. Can be formed.

  The insulating isolation trench in the semiconductor device includes, for example, an insulating isolation trench in which an insulator is embedded in the trench, an insulating isolation trench in which a conductor is embedded in the trench via a sidewall oxide film, and a cavity in the trench. It may be any of the insulating isolation trenches formed.

  In the semiconductor device, an impurity diffusion layer having a different conductivity type or a different concentration from that of the semiconductor substrate may be formed on at least one surface side of the semiconductor substrate. Accordingly, it is possible to form a double-sided electrode element having various characteristics by appropriately setting the conductivity type, concentration, and thickness of the impurity diffusion layer.

  The impurity diffusion layer may be formed in a part of the plurality of field regions. Accordingly, various active elements or passive elements can be formed on one semiconductor substrate by appropriately forming an impurity diffusion layer having a predetermined conductivity type, concentration and thickness in a predetermined field region.

  Next, a method for manufacturing a semiconductor device according to the present invention, in which the semiconductor device is a manufacturing object, will be described.

  According to the first aspect of the present invention, one semiconductor substrate is surrounded by an insulating isolation trench penetrating the semiconductor substrate and divided into a plurality of field regions, and an active element or a passive element using the semiconductor substrate. Are formed on the semiconductor substrate and distributed in different field regions, and two or more of the plurality of active elements or passive elements drive the element. A method of manufacturing a semiconductor device which is a double-sided electrode element, in which a set of electrodes is distributed and arranged on both surfaces of the semiconductor substrate, and preparing a semiconductor substrate for element formation having a predetermined thickness Forming a non-penetrating insulating isolation trench at a predetermined depth from the first surface side surface of the element forming semiconductor substrate so as to surround each of the plurality of field regions; Polishing from the second surface side of the element forming semiconductor substrate until the tip of the non-penetrating insulating isolation trench is exposed, thereby making the element forming semiconductor substrate the semiconductor substrate. And a first surface side element for forming the plurality of active elements or passive elements on the first surface side of the element forming semiconductor substrate. And a second surface side element forming step for forming the plurality of active elements or passive elements on the second surface side of the semiconductor substrate after the substrate polishing step. .

  The manufacturing method of the semiconductor device does not require a special process when forming a plurality of active elements or passive elements on a single semiconductor substrate, and includes only a processing process for a general bulk single crystal silicon substrate. ing. The above-described semiconductor device manufacturing method uses an inexpensive bulk single crystal silicon substrate without using an SOI substrate having a buried oxide film that requires a substrate bonding step when insulating and separating a plurality of active elements or passive elements. Thus, the manufacturing process is simplified because it is only necessary to form an isolation trench that penetrates the substrate.

  The plurality of active elements or passive elements include two or more double-sided electrode elements. In the method of manufacturing a semiconductor device, the first method is performed on the first surface side of the element forming semiconductor substrate. A plurality of active elements or passive elements are formed by dividing into a first surface side element forming step and a second surface side element forming step performed on the second surface side of the semiconductor substrate after the substrate polishing step. . As a result, even a semiconductor device including a double-sided electrode element can be manufactured.

  As described above, the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a plurality of active elements or passive elements including two or more double-sided electrode elements are formed on a single semiconductor substrate. The electrode element can also be insulated and integrated, and can be a method for manufacturing a semiconductor device that can be manufactured at low cost.

  In the method for manufacturing a semiconductor device, it is preferable that the first surface side element forming step is performed between the non-penetrating insulating isolation trench forming step and the substrate polishing step.

  The first surface side element forming step in the semiconductor device manufacturing method may be performed before the non-penetrating insulating isolation trench forming step or after the substrate polishing step. However, by performing the first surface side element forming step after the non-penetrating insulating isolation trench forming step, it is possible to prevent an adverse effect on the element formation associated with the non-penetrating insulating isolation trench forming step. By performing the element formation step before the substrate polishing step, the first surface side element formation step can be performed in an easy-to-handle state before the substrate thickness is reduced.

  In the semiconductor device manufacturing method, when the element forming semiconductor substrate is an epitaxial substrate in which a silicon epitaxial layer is formed on a bulk single crystal silicon substrate, the first surface side surface of the element forming semiconductor substrate Is the silicon epitaxial layer.

  The non-penetrating insulating isolation trench in the semiconductor device manufacturing method includes, for example, a non-penetrating insulating isolating trench in which an insulator is embedded in the trench, and an unembedded conductor in the trench through a sidewall oxide film. It may be either a through-insulation isolation trench or a non-through-insulation isolation trench having a hollow inside the trench.

  In the method of manufacturing a semiconductor device, when an impurity diffusion layer having a different conductivity type or a different concentration from the semiconductor substrate is formed on at least one surface side of the semiconductor substrate, the impurity diffusion layer includes the plurality of impurity diffusion layers. In the case of being formed in a part of the field region, an ion implantation step for forming the impurity diffusion layer is performed after the substrate polishing step.

  The effects of the semiconductor device manufactured by the above manufacturing method are as described above, and the description thereof is omitted.

1 is a diagram showing a schematic cross section of a semiconductor device 100 as an example of a semiconductor device to be manufactured according to the present invention. FIG. 6 is a diagram showing a schematic cross section of a semiconductor device 101 as another example of the semiconductor device. FIGS. 5A to 5E are cross-sectional views for each process showing a method for manufacturing the semiconductor device 102. FIGS. FIG. 3 is a schematic cross-sectional view of the semiconductor device 103 and is a diagram illustrating an example of connection wiring of each double-sided electrode element formed in the semiconductor device 103. (A), (b) is typical sectional drawing which showed the mounting state of the semiconductor device 104 to the circuit board P, respectively. 2A and 2B are diagrams illustrating a semiconductor device 110 configured with a half-bridge circuit, in which FIG. 1A is an equivalent circuit diagram of the semiconductor device 110 and FIG. 2B is a schematic cross-sectional view of the semiconductor device 110; 2A and 2B are diagrams illustrating another semiconductor device 111 having a half-bridge circuit, where FIG. 2A is an equivalent circuit diagram of the semiconductor device 111 and FIG. 2B is a schematic cross-sectional view of the semiconductor device 111; 2A and 2B are diagrams illustrating a semiconductor device 112 in which an H-bridge circuit is configured, in which FIG. 1A is an equivalent circuit diagram of the semiconductor device 112 and FIG. 2B is a schematic cross-sectional view of the semiconductor device 112; 4A and 4B are diagrams showing another semiconductor device 113 in which an H-bridge circuit is configured, in which FIG. 5A is an equivalent circuit diagram of the semiconductor device 113, and FIG. 5B is a schematic cross-sectional view of the semiconductor device 113. 4A and 4B are diagrams showing another semiconductor device 114 in which an H-bridge circuit is configured, in which FIG. 5A is an equivalent circuit diagram of the semiconductor device 114, and FIG. 5B is a schematic cross-sectional view of the semiconductor device 114. 4A and 4B are diagrams showing another semiconductor device 115 in which an H-bridge circuit is configured, in which FIG. 5A is an equivalent circuit diagram of the semiconductor device 115, and FIG. 5B is a schematic cross-sectional view of the semiconductor device 115. It is a circuit diagram of the power module (IPM) of a three-phase inverter. 1 is a schematic cross-sectional view of a semiconductor device 105 as an example of a semiconductor device in which a power module (IPM) of a three-phase inverter is configured. FIG. 5 is a schematic cross-sectional view of a semiconductor device 106 as another example of a semiconductor device in which a power module (IPM) of a three-phase inverter is configured. It is the figure which showed the cross section of the conventional semiconductor device 90 typically.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 as an example of a semiconductor device to be manufactured according to the present invention.

  A semiconductor device 100 in FIG. 1 is a semiconductor device in which a plurality of active elements 31 to 33 and 41 to 43 and passive elements 51 and 52 are formed on one semiconductor substrate 20. In the semiconductor device 100, as representative examples of active elements, bipolar transistor elements 31, complementary metal oxide semiconductor (CMOS) transistor elements 32, horizontal MOS transistor elements 33, vertical MOS transistor elements 41, IGBTs (Insulated Gate Bipolar Transistors). ) Element 42 and diode element 43 are illustrated. Further, in the semiconductor device 100, as representative examples of passive elements, an N conductivity type (n−) low impurity concentration element 51 used as a resistance element and an N conductivity type (n +) high impurity concentration element 52 used as a wiring element. Is illustrated.

  The semiconductor substrate 20 used in the semiconductor device 100 is made of an N conductivity type (n−) bulk single crystal silicon substrate. The active elements 31 to 33 and 41 to 43 and the passive elements 51 and 52 shown in FIG. 1 are not thin film elements, but a semiconductor substrate 20 made of an N conductivity type (n−) bulk single crystal silicon substrate is used. It is an element.

  In the semiconductor device 100 of FIG. 1, the semiconductor substrate 20 is surrounded by an insulating isolation trench T penetrating the semiconductor substrate 20 and divided into a plurality of field regions F1 to F8. The insulating isolation trench T includes, for example, an insulating isolation trench in which an insulator such as silicon oxide is embedded in the trench, and an insulating isolation trench in which a conductor such as polycrystalline silicon is embedded in the trench via a sidewall oxide film. , And an insulating isolation trench in which a cavity is formed in the trench and both surfaces are covered with silicon oxide or the like.

  The plurality of active elements 31 to 33 and 41 to 43 and the passive elements 51 and 52 in the semiconductor device 100 are distributed in different field regions F1 to F8. Among the plurality of active elements 31 to 33 and 41 to 43 and the passive elements 51 and 52, the active elements 41 to 43 exemplified by the vertical MOS transistor element 41, the IGBT element 42, and the diode element 43 and the resistances. The passive elements 51 and 52, which are exemplified by the low impurity concentration element 51 as the element and the high impurity concentration element 52 as the wiring element, are hatched in FIG. 1 for energizing the elements 41 to 43, 51 and 52. This is a double-sided electrode element in which a pair of electrodes dr1 and dr2 are distributed and arranged on both surfaces of the semiconductor substrate 20 on the first surface S1 side and the second surface S2 side. As described above, the semiconductor device 100 includes two or more double-sided electrode elements 41 to 43, 51, and 52. Accordingly, at least the double-sided electrode elements 41 to 43, 51, and 52 are formed on the second surface S2 side of the semiconductor substrate 20. In addition, the active elements 31 to 33 exemplified by the bipolar transistor element 31, the CMOS transistor element 32, and the lateral MOS transistor element 33 are a set of hatched electrodes in FIG. 1 for energizing the elements 31 to 33. ds1 is a single-sided electrode element that is collectively arranged on one surface of the semiconductor substrate 20 on the first surface S1 side.

  In the semiconductor device 100, an impurity diffusion layer 21 of P conductivity type (p) different from the N conductivity type (n−) semiconductor substrate 20 or the same N conductivity type is formed on at least one second surface S2 side of the semiconductor substrate 20. Impurity diffusion layers 22 having different concentrations (n +) are formed. These impurity diffusion layers 21 and 22 are respectively formed in some field regions F5 and field regions F1 to F4 and F8 among the plurality of field regions F1 to F8. In the semiconductor device 100, the impurity diffusion layers 21 and 22 having a predetermined conductivity type, concentration and thickness are appropriately formed in predetermined field regions F1 to F4, F5 and F8, so that various characteristics can be obtained on one semiconductor substrate 20. The double-sided electrode elements 41 to 43, 51, and 52 having various active elements 31 to 33 and 41 to 43 and the passive elements 51 and 52 can be formed.

  Since the double-sided electrode elements such as the vertical MOS transistor element 41 and the IGBT element 42 are formed in the semiconductor device 100 of FIG. Since the bulk single crystal silicon substrate 20 is used for the semiconductor device 100, when a double-sided electrode element such as the vertical MOS transistor element 41 or the IGBT element 42 is formed, the withstand capability against surges such as large current and ESD is increased. Is easy. Further, since there is no buried oxide film, heat dissipation can be improved as compared with a semiconductor device using an SOI substrate.

  Further, according to the insulating isolation structure, as in the semiconductor device 100 shown in FIG. 1, the double-sided electrode element such as the vertical MOS transistor element 41 and the IGBT element 42, the bipolar transistor element 31, and the horizontal MOS transistor element 33. It can be set as the composite IC which combined the single-sided electrode element like.

  In the semiconductor device 100 of FIG. 1, in realizing an integrated structure composed of a plurality of active elements 31 to 33, 41 to 43 and passive elements 51 and 52, the semiconductor substrate 20 used in the semiconductor device 100 is shown in FIG. Instead of the SOI substrate 1 having the buried oxide film 3 such as the semiconductor device 90, it may be a general and inexpensive bulk single crystal silicon substrate. Further, the semiconductor substrate 20 shown in FIG. 1 is surrounded by an insulating isolation trench T penetrating the semiconductor substrate 20 and divided into a plurality of field regions F1 to F8, and dispersed into these different field regions F1 to F8. A plurality of active elements 31 to 33 and 41 to 43 and passive elements 51 and 52 are arranged, respectively. Thus, in the semiconductor device 100, the plurality of active elements 31 to 33, 41 to 43 and the passive elements 51 and 52 are insulated and integrated with each other by the insulating isolation trench T that penetrates the semiconductor substrate 20. It becomes. In addition, since the semiconductor substrate 20 may be a bulk single crystal silicon substrate without a buried oxide film, the active elements 41 to 43 and the passive elements 51 and 52 constituting the semiconductor device 100 are double-sided electrode elements as described above. Even if it is, integration is possible. Furthermore, the semiconductor device 100 can be manufactured at low cost by a manufacturing method described later.

  FIG. 2 is a diagram illustrating a schematic cross-section of the semiconductor device 101 as another example of the semiconductor device. In the semiconductor device 101 of FIG. 2, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  The semiconductor device 100 of FIG. 1 is formed on a semiconductor substrate 20 made of an N conductivity type (n−) bulk single crystal silicon substrate. On the other hand, the semiconductor device 101 of FIG. 2 is a semiconductor substrate made of an epitaxial substrate in which an N conductivity type (n−) silicon epitaxial layer 62 is formed on an N conductivity type (n +) bulk single crystal silicon substrate 61. 60.

  The semiconductor substrates 20 and 60 in the semiconductor devices 100 and 101 of FIG. 1 and FIG. 2 require a predetermined substrate thickness in order to ensure a predetermined strength necessary for handling. For example, when forming a double-sided electrode element for power such as the vertical MOS transistor element 41 and the IGBT element 42, a drift layer of (n−) carriers having a low impurity concentration is necessary to achieve a high breakdown voltage. is there. On the other hand, in order to obtain a low ON resistance element, an (n +) drift layer having a high impurity concentration is required. According to the epitaxial substrate 60 in the semiconductor device 101 of FIG. 2, an N conductivity type (n +) bulk single crystal silicon substrate 61 is used as a support substrate for ensuring strength, and an N conductivity type (n It is possible to form a double-sided electrode element having a high breakdown voltage or low ON resistance by using the silicon epitaxial layer 62 of −) as a carrier drift layer.

  2, a plurality of active elements 31 to 33 and 41 to 43 and passive elements 51 and 52 similar to those of the semiconductor device 100 of FIG. 1 are arranged in different field regions. ing. The semiconductor device 101 of FIG. 2 also has two or more double-sided electrode elements 41 to 43, 51, 52, and at least the double-sided electrode elements 41 to 43 are provided on the second surface S2 side of the semiconductor substrate 60. , 51, 52 or more electrodes are formed.

  As described above, each of the semiconductor devices 100 and 101 shown in FIGS. 1 and 2 is a semiconductor device in which a plurality of active elements or passive elements are formed on one semiconductor substrate, and there are two or more semiconductor devices. The double-sided electrode element can also be insulated and integrated, resulting in an inexpensive semiconductor device.

  Next, a method for manufacturing the semiconductor devices 100 and 101 shown in FIGS. 1 and 2 will be described.

  3A to 3E are cross-sectional views for each process showing a method for manufacturing the semiconductor device 102 in which the semiconductor device 100 of FIG. 1 is simplified. In the semiconductor device 102 shown in FIG. 3E, a vertical MOS transistor element 41 and an IGBT element 42 which are double-sided electrode elements are formed. In the semiconductor device 102 of FIG. 3E, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  In manufacturing the semiconductor device 102, first, in the substrate preparation step shown in FIG. 3A, an element forming semiconductor substrate 20a having a predetermined thickness (for example, 400 μm) is prepared.

  Next, in the non-penetrating insulating isolation trench forming step shown in FIG. 3B, a predetermined depth is formed from the surface on the first surface S1 side of the element forming semiconductor substrate so as to surround each region to be the field regions F4 and F5. A non-penetrating insulating isolation trench Ta is formed in (for example, 150 μm). The non-penetrating insulating isolation trench Ta includes a non-penetrating insulating isolating trench in which an insulator is embedded in the trench, a non-penetrating insulating isolating trench in which a conductor is embedded via a sidewall oxide film, and a hollow in the trench It may be any of the non-through insulating isolation trenches. In the case of forming the non-penetrating insulating isolation trench Ta in which the trench is hollow, the first surface S1 of the non-penetrating insulating isolating trench Ta is formed in the first surface side element forming step shown in FIG. Cover the opening on the side surface with an insulator.

  Next, in the first surface side element formation step shown in FIG. 3C, the vertical MOS transistor elements 41 and the IGBT elements 42 which are double-sided electrode elements are formed on the first surface S1 side of the element formation semiconductor substrate 20a. Each process required in order to form each part by the side of 1st surface S1 is implemented.

  Next, in the substrate polishing step shown in FIG. 3D, the tip of the non-penetrating insulating isolation trench Ta is exposed from the second surface S2 side of the element forming semiconductor substrate 20a (for example, the substrate thickness is 120 μm). Polish up to. Note that it is desirable to wet-etch the polished surface after mechanical polishing in order to remove the damaged layer. As a result, the element forming semiconductor substrate 20 a becomes the semiconductor substrate 20 having a predetermined thickness, and the non-penetrating insulating isolation trench Ta becomes the insulating isolation trench T penetrating the semiconductor substrate 20.

  Finally, in the second surface side element forming step shown in FIG. 3E after the substrate polishing step, an ion implantation step for forming the impurity diffusion layers 21 and 22 on the second surface S2 side of the semiconductor substrate 20 is performed. At the same time, the respective steps necessary for forming the respective parts on the second surface S2 side of the vertical MOS transistor element 41 and the IGBT element 42 which are double-sided electrode elements are carried out.

  Thus, the semiconductor device 102 is completed.

  In the method for manufacturing the semiconductor device 102 shown in FIGS. 3A to 3E, the first surface side element forming step shown in FIG. 3C is replaced with the non-penetrating insulating isolation trench shown in FIG. It is carried out between the forming process and the substrate polishing process of FIG. The first surface side element forming step in the method for manufacturing the semiconductor device 102 can be performed, for example, before the non-penetrating insulating isolation trench forming step in FIG. 3B or after the substrate polishing step in FIG. It is. However, by performing the first surface side element forming step after the non-penetrating insulating isolation trench forming step of FIG. 3B, the element formation associated with the non-penetrating insulating isolating trench forming step of FIG. An adverse effect can be prevented, and the first surface side element can be easily handled before the substrate thickness is reduced by performing the first surface side element forming step before the substrate polishing step of FIG. It becomes possible to perform a formation process.

  The manufacturing method of the semiconductor device 102 shown in FIGS. 3A to 3E does not require a special process when forming the vertical MOS transistor element 41 and the IGBT element 42 on one semiconductor substrate 20, and is generally used. It is composed only of a processing process to a bulk single crystal silicon substrate. Further, in the method of manufacturing the semiconductor device 102 shown in FIGS. 3A to 3E, when the vertical MOS transistor element 41 and the IGBT element 42 are insulated and separated, the substrate bonding step described in the semiconductor device 90 of FIG. The manufacturing process is simplified because it is only necessary to form an insulating isolation trench penetrating the substrate using an inexpensive bulk single crystal silicon substrate without using an SOI substrate having a buried oxide film that requires a large thickness.

  Further, the vertical MOS transistor element 41 and the IGBT element 42 are double-sided electrode elements. However, in the method of manufacturing the semiconductor device 102 shown in FIGS. 3A to 3E, the first surface S1 of the element forming semiconductor substrate 20a is used. The first surface side element forming step of FIG. 3C performed on the side, and the second surface side element forming step of FIG. 3E performed on the second surface S2 side of the semiconductor substrate 20 after the substrate polishing step, The vertical MOS transistor element 41 and the IGBT element 42 are formed separately. As a result, even the semiconductor device 102 including the double-sided electrode element can be manufactured.

  As described above, in the method of manufacturing the semiconductor device 102 shown in FIGS. 3A to 3E, a plurality of active elements or passive elements including two or more double-sided electrode elements are formed on one semiconductor substrate. The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device that can be insulated and integrated with respect to a double-sided electrode element, and can be manufactured at low cost.

  In the method for manufacturing the semiconductor device 102 shown in FIGS. 3A to 3E, a bulk single crystal silicon substrate is used as the element forming semiconductor substrate 20a, and the semiconductor device 102 is the semiconductor device shown in FIG. Similar to 100, it is a semiconductor device formed on a bulk single crystal silicon substrate. On the other hand, a semiconductor device formed on the same epitaxial substrate as the semiconductor device 101 shown in FIG. 2 can be manufactured in the same manner by the manufacturing method shown in FIGS. In this case, in the substrate preparation step shown in FIG. 3A, an epitaxial substrate in which a silicon epitaxial layer is formed on a bulk single crystal silicon substrate is prepared as an element forming semiconductor substrate, and FIGS. In each step shown in (1), each step may be performed such that the surface on the first surface S1 side of the semiconductor substrate for forming an element becomes a silicon epitaxial layer.

  Next, application forms such as connection wiring and mounting on a circuit board will be described for semiconductor devices similar to the semiconductor devices 100 to 102 shown in FIGS.

  FIG. 4 is a schematic cross-sectional view of the semiconductor device 103 and is a diagram illustrating an example of connection wiring of each double-sided electrode element formed in the semiconductor device 103. In the semiconductor device 103 of FIG. 4, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  As described above, the double-sided electrode elements 41 to 44, 51, and 52 in the semiconductor device 103 of FIG. 4 are a pair of electrodes dr1 that are hatched in FIG. 4 for driving the elements 41 to 43, 51, and 52, respectively. , Dr2 are elements that are distributed and arranged on both surfaces of the semiconductor substrate 20 on the first surface S1 side and the second surface S2 side. Therefore, in the semiconductor device 103 having two or more double-sided electrode elements 41 to 44, 51, 52, the interlayer insulating films Z1, Z2 are respectively provided on both the first surface S1 side and the second surface S2 side of the semiconductor substrate. Wirings L1 and L2 are formed via the. Further, the high impurity concentration element 52 as a wiring element is used as a wiring connecting the first surface S1 side and the second surface S2 side of the semiconductor substrate 20.

  FIGS. 5A and 5B are schematic cross-sectional views showing the mounting state of the semiconductor device 104 on the circuit board P, respectively. In the semiconductor device 104 of FIG. 5, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  In FIG. 5A, the electrodes dr <b> 2 on the second surface S <b> 2 side of the double-sided electrode element 41 formed on the semiconductor device 104 are connected by the wiring PL provided on the circuit board P. As described above, the electrode on the second surface side of the double-sided electrode element formed in the semiconductor device of the present invention is connected using the wiring on the circuit board side when the semiconductor device is mounted on the circuit board. Also good.

  In FIG. 5B, the electrode dr <b> 2 on the second surface S <b> 2 side of the double-sided electrode element 41 formed on the semiconductor device 104 is connected to the heat sink Ph provided on the circuit board P. Thus, the electrode on the second surface side of the double-sided electrode element formed in the semiconductor device of the present invention can be used for heat dissipation by connecting to the heat sink on the circuit board side.

  Next, a more specific application mode of the semiconductor device similar to the semiconductor devices 100 to 104 illustrated in FIGS. 1 to 5 will be described.

  6A and 6B are diagrams illustrating the semiconductor device 110 in which a half-bridge circuit is configured. FIG. 6A is an equivalent circuit diagram of the semiconductor device 110, and FIG. 6B is a schematic diagram of the semiconductor device 110. FIG. In the following semiconductor devices 110 to 115 shown in FIGS. 6 to 11, the same parts as those of the semiconductor devices 100 to 104 shown in FIGS.

  In the semiconductor device 110 shown in FIG. 6, two vertical MOS transistor elements 41 a and 41 b having the same structure are formed on the semiconductor substrate 20 as double-sided electrode elements. As shown in FIG. 6B, the two vertical MOS transistor elements 41a and 41b are connected in series via a double-sided electrode element 52a that functions as a wiring element in which a buried metal Mk penetrating the semiconductor substrate 20 is formed. It is connected. The two vertical MOS transistor elements 41a and 41b connected in series constitute the half bridge circuit shown in FIG. 6A, and the output of the half bridge circuit is two vertical types connected in series. It is taken out from the connection point of the MOS transistor elements 41a and 41b. In addition, although the output insertion terminal L of the semiconductor device 110 formed of the half bridge circuit is arranged on the first surface S1 side which is the source side of the vertical MOS transistor element 41a in FIG. 6B, It is also possible to arrange it on the second surface S2 side which is the drain side of the vertical MOS transistor element 41b.

  FIG. 7 is a diagram illustrating another semiconductor device 111 in which a half-bridge circuit is configured. FIG. 7A is an equivalent circuit diagram of the semiconductor device 111, and FIG. 7B is a diagram illustrating the semiconductor device 111. It is typical sectional drawing.

  In the semiconductor device 111 shown in FIG. 7, two IGBT elements 42 a and 42 b having the same structure are formed on the semiconductor substrate 20 as double-sided electrode elements. In the semiconductor device 111, diode elements 43a and 43b, which are other double-sided electrode elements, are connected in parallel to the IGBT elements 42a and 42b. The diode elements 43a and 43b connected in parallel to the IGBT elements 42a and 42b can be used as so-called free wheel diodes (FWD) in, for example, a power module of a three-phase inverter described later. In the semiconductor device 110 shown in FIG. 6, the diode elements 43a and 43b can be similarly connected.

  As shown in FIG. 7B, the two IGBT elements 42a and 42b in the semiconductor device 111 of FIG. 7 are connected in series via a double-sided electrode element 52a that functions as a wiring element, as in the semiconductor device 110 of FIG. It is connected. The two IGBT elements 42a and 42b connected in series constitute the half bridge circuit shown in FIG. 7A, and the outputs of the half bridge circuit are connected to the two IGBT elements 42a and 42b connected in series. Taken from the connection point. Also in the semiconductor device 111 of FIG. 7, the output insertion terminal L of the half bridge circuit is on the first surface S1 side which is the emitter side of the IGBT element 42a and on the second surface S2 side which is the collector side of the IGBT element 42b. Either can be arranged.

  FIG. 8 is a diagram illustrating the semiconductor device 112 in which an H-bridge circuit is configured. FIG. 8A is an equivalent circuit diagram of the semiconductor device 112, and FIG. 8B is a schematic diagram of the semiconductor device 112. FIG.

  A semiconductor device 112 illustrated in FIG. 8 corresponds to a semiconductor device in which two sets of half-bridge circuits of the semiconductor device 110 illustrated in FIG. 6 are configured. In the semiconductor device 112, four vertical MOS transistor elements 41a to 41d having the same structure are formed on the semiconductor substrate 20 as double-sided electrode elements, and each set of two vertical MOS transistor elements 41a and 41b and As shown in FIG. 8B, 41c and 41d are connected in series via double-sided electrode elements 52a and 52b that function as wiring elements, respectively. The two vertical MOS transistor elements 41a, 41b and 41c, 41d of each set connected in series are further connected in parallel to form the H bridge circuit shown in FIG. The output of the circuit is taken out from each connection point of two sets of vertical MOS transistor elements 41a, 41b and 41c, 41d connected in series. Also in the semiconductor device 112, the output insertion terminals L1 and L2 of the H bridge circuit are arranged on the first surface S1 side which is the source side of the vertical MOS transistor elements 41a and 41c in FIG. 8B, respectively. However, it may be arranged on the second surface S2 side which is the drain side of the vertical MOS transistor elements 41b and 41d.

  FIG. 9 is a diagram illustrating another semiconductor device 113 in which an H-bridge circuit is configured. FIG. 9A is an equivalent circuit diagram of the semiconductor device 113, and FIG. 9B is a diagram of the semiconductor device 113. It is typical sectional drawing.

  A semiconductor device 113 illustrated in FIG. 9 corresponds to a semiconductor device in which two sets of half-bridge circuits of the semiconductor device 111 illustrated in FIG. 7 are configured. In the semiconductor device 113, four IGBT elements 42 a to 42 d having the same structure are formed on the semiconductor substrate 20 as double-sided electrode elements. Further, diode elements 43a to 43d, which are other double-sided electrode elements, are connected in parallel to the IGBT elements 42a to 42d. Also in the semiconductor device 113, the output insertion terminals L1 and L2 of the H bridge circuit are arranged on the first surface S1 side which is the emitter side of the IGBT elements 42a and 42c in FIG. 9B, respectively. It is also possible to arrange the IGBT elements 42b and 42d on the second surface S2 side which is the collector side.

  Similarly, a semiconductor device in which a power module of a three-phase inverter is configured can be provided. In this case, a semiconductor device in which three sets of half-bridge circuits of the semiconductor devices 110 and 111 shown in FIGS. The output of each phase of the three-phase inverter is taken out from the connection point of two vertical MOS transistor elements and IGBT elements connected in series in the three sets of half-bridge circuits. A semiconductor device in which the power module of the three-phase inverter is configured will be described in detail later.

  The H bridge circuit shown in FIG. 8A or FIG. 9A uses a semiconductor device similar to the semiconductor devices 100 to 104 shown in FIG. 1 to FIG. Is also possible.

  FIG. 10 is a diagram illustrating another semiconductor device 114 in which an H-bridge circuit is configured. FIG. 10A is an equivalent circuit diagram of the semiconductor device 114, and FIG. 10B is a diagram of the semiconductor device 114. It is typical sectional drawing.

  As shown in FIG. 10A, the equivalent circuit diagram of the semiconductor device 114 is basically the same as the equivalent circuit diagram of the semiconductor device 112 shown in FIG. On the other hand, in the semiconductor device 112 shown in FIG. 8, the H bridge circuit is formed on one semiconductor substrate 20, whereas the semiconductor device 114 shown in FIG. Therefore, the semiconductor devices 114H and 114L are formed on the semiconductor substrates 22 and 23, respectively.

  In the semiconductor devices 114H and 114L, two vertical MOS transistor elements 41Ha and 41Hb and 41La and 41Lb having the same structure as double-sided electrode elements are formed on the semiconductor substrates 22 and 23, respectively. As shown in FIG. 10B, the two semiconductor devices 114H and 114L are stacked with two leads M1 and M2 interposed therebetween. The vertical MOS transistor elements 41Ha and 41La and the vertical MOS transistor elements 41Hb and 41Lb of the semiconductor devices 114H and 114L are connected in series via the leads M1 and M2, respectively, to form an H bridge circuit. Yes. The output of the H bridge circuit is taken out from these leads M1 and M2.

  FIG. 11 is a diagram illustrating another semiconductor device 115 in which an H-bridge circuit is configured. FIG. 11A is an equivalent circuit diagram of the semiconductor device 115, and FIG. 11B is a diagram of the semiconductor device 115. It is typical sectional drawing.

  As shown in FIG. 11A, the equivalent circuit diagram of the semiconductor device 115 is basically the same as the equivalent circuit diagram of the semiconductor device 113 shown in FIG. On the other hand, in the semiconductor device 113 shown in FIG. 9, the H bridge circuit is formed on one semiconductor substrate 20, whereas the semiconductor device 115 shown in FIG. Therefore, the semiconductor devices 115H and 115L are formed on the semiconductor substrates 22 and 23, respectively.

  In the semiconductor devices 115H and 115L, two IGBT elements 42Ha and 42Hb and 42La and 42Lb having the same structure as double-sided electrode elements are formed on the semiconductor substrates 22 and 23, respectively. Further, diode elements 43Ha, 43Hb, 43La, and 43Lb, which are other double-sided electrode elements, are connected in parallel to the IGBT elements 42Ha, 42Hb, 42La, and 42Lb. As shown in FIG. 11B, the two semiconductor devices 115H and 115L are stacked with two leads M1 and M2 interposed therebetween. The IGBT elements 42Ha and 42La and the IGBT elements 42Hb and 42Lb of the semiconductor devices 115H and 115L are connected in series via the leads M1 and M2, respectively, to form an H bridge circuit. The output of the H bridge circuit is taken out from these leads M1 and M2.

  Similarly to the semiconductor devices 114 and 115 shown in FIG. 10 and FIG. 11, a set of two semiconductor devices for forming a semiconductor device in which a half-bridge circuit is formed and a power module of a three-phase inverter are formed. Needless to say, the semiconductor device can be constituted by the semiconductor device.

  6 to 11, only the main part of the semiconductor devices 110 to 115 is shown. However, like the semiconductor devices 100 to 104 shown in FIGS. Another double-sided electrode element or single-sided electrode element may be formed. When the double-sided electrode element is a power element for power use as in the semiconductor devices 110 to 115 shown in FIGS. 6 to 11, for example, if the single-sided electrode element is formed at another position of the semiconductor substrate, the single-sided electrode element Can be used to control the double-sided electrode element. According to this, the semiconductor device can be a composite IC in which a power element for power use and a single-sided electrode element for controlling the power element are formed on one semiconductor substrate.

  Next, with respect to the semiconductor devices similar to the semiconductor devices 100 to 104 shown in FIG. 1 to FIG.

  FIG. 12 is a circuit diagram of a power module (IPM) of a three-phase inverter.

  As shown in FIG. 12, the power module (IPM) of the three-phase inverter surrounded by a dotted line corresponds to three sets of power transistors (HTu) connected in series corresponding to the phases u, v, and w of the three-phase alternating current. , LTu), (HTv, LTv), (HTw, LTw). The outputs of the three-phase alternating current phases u, v, w are respectively the sources of the three power transistors HTu, HTv, HTw on the high potential side and the three power transistors LTu, LTv, LTw on the low potential side. It is taken out from the connection point of the drain. Each of the power transistors HTu, HTv, HTw, LTu, LTv, and LTw is driven by an input signal to the gate from the driver circuit.

  FIG. 13 is an example of a semiconductor device in which the power module (IPM) of the three-phase inverter of FIG. 12 is configured, and is a schematic cross-sectional view of the semiconductor device 105. In the semiconductor device 105 of FIG. 13, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  A semiconductor device 105 in FIG. 13 is a semiconductor device in which each of the power transistors HTu, HTv, HTw, LTu, LTv, and LTw in FIG. 12 is formed as a double-sided electrode element on one semiconductor substrate 20. In the semiconductor device 105, the three power transistors HTu, HTv, HTw on the high potential side and the three power transistors LTu, LTv, LTw on the low potential side are respectively connected to the wiring L1, the high potential on the first surface S1 side. The impurity concentration element 52 and the wiring L2 on the second surface S2 side are connected in series. Further, the driver circuit shown in FIG. 12 can be formed at another position on the same semiconductor substrate 20 by using a single-sided electrode element or the like.

  FIG. 14 is a schematic cross-sectional view of a semiconductor device 106 as another example of a semiconductor device in which the power module (IPM) of the three-phase inverter of FIG. 12 is configured. In the semiconductor device 106 of FIG. 14, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  A semiconductor device 106 in FIG. 14 includes two semiconductor devices 106H and 106L, and is a semiconductor device that is molded with a resin M. In the semiconductor device 106H, three power transistors HTu, HTv, and HTw on the high potential side shown in FIG. 12 are formed on the semiconductor substrate 22 as double-sided electrode elements. In the semiconductor device 106L, three power transistors LTu, LTv, LTw on the low potential side shown in FIG. 12 are formed on the semiconductor substrate 23 as double-sided electrode elements. The source electrode dr1H of each power transistor HTu, HTv, HTw of the semiconductor device 106H and the drain electrode dr2L of each power transistor LTu, LTv, LTw of the semiconductor device 106L are respectively the three-phase AC phases u, v, w. Are directly connected to lead pins Mu, Mv, and Mw. The drain electrodes dr2H of the power transistors HTu, HTv, HTw of the semiconductor device 106H are commonly connected to a lead pin Md and a heat sink Mdh connected to the power source. The source electrode dr1L of each power transistor LTu, LTv, LTw of the semiconductor device 106L is commonly connected to a lead pin Mg and a heat sink Mgh connected to the ground. As described above, in each of the semiconductor devices 106H and 106L, the electrodes dr1H, dr2H, dr1L, and dr2L are directly connected to the lead pins Mu, Mv, Mw, Md, and Mg, and are also connected to the heat sinks Mdh and Mgh. Therefore, the semiconductor device 106 shown in FIG. 12 can be a power module (IPM) of a three-phase inverter having low loss and high heat dissipation.

  Like the semiconductor device 106 shown in FIG. 12, the double-sided electrode elements in the semiconductor devices 100 to 106 and 110 to 115 described above have a pair of electrodes for driving the elements dispersed on the surfaces on both sides of the semiconductor substrate. Therefore, by directly connecting these electrodes to a lead frame or a heat sink, a semiconductor device having low loss and high heat dissipation can be obtained. Therefore, it is particularly suitable as an in-vehicle semiconductor device that requires high breakdown voltage and large current drive.

  As described above, the semiconductor device manufacturing method according to the present invention is a method for manufacturing a semiconductor device in which a plurality of active elements or passive elements are formed on a single semiconductor substrate. It is a method for manufacturing a semiconductor device that can be insulated and integrated and can be manufactured at low cost.

90, 100-106, 110-113, 106H, 106L, 114H, 114L, 115H, 115L Semiconductor device 20-23, 60 Semiconductor substrate 20a Semiconductor substrate for element formation S1 First surface S2 Second surface T Insulation isolation trench Ta Not yet Through insulation isolation trench F1 to F8 Field region 31 to 33 Active element (single-sided electrode element)
41-43, 41a-41d, 41Ha, 41Hb, 41La, 41Lb, 42a-42d, 42Ha, 42Hb, 42La, 42Lb, 43a-43d, 43Ha, 43Hb, 43La, 43Lb, HTu, HTv, HTw, LTu, LTv, LTw Active element (double-sided electrode element)
51, 52, 52a, 52b Passive element (double-sided electrode element)
ds1 electrode (single-sided electrode element)
dr1, dr1H, dr1L electrode (first surface side of double-sided electrode element)
dr2, dr2H, dr2L electrode (second surface side of double-sided electrode element)

Claims (6)

One semiconductor substrate is surrounded by insulating isolation trenches penetrating the semiconductor substrate and divided into a plurality of field regions,
A plurality of active elements or passive elements using the semiconductor substrate are formed on the semiconductor substrate and are distributed and arranged in different field regions,
Of the plurality of active elements or passive elements, two or more elements are:
A method of manufacturing a semiconductor device which is a double-sided electrode element, in which a set of electrodes for driving the element is dispersedly disposed on both surfaces of the semiconductor substrate,
A substrate preparation step of preparing an element forming semiconductor substrate of a predetermined thickness;
A non-penetrating insulating isolation trench forming step of forming a non-penetrating insulating isolation trench at a predetermined depth from the first surface side surface of the element forming semiconductor substrate so as to surround each of the plurality of field regions;
Polishing from the second surface side of the element forming semiconductor substrate until the tip of the non-penetrating insulating isolation trench is exposed to make the element forming semiconductor substrate the semiconductor substrate and isolating the non-penetrating insulating isolating trench into the insulating isolation A substrate polishing step to be a trench;
A first surface side element forming step for forming the plurality of active elements or passive elements on the first surface side of the element forming semiconductor substrate;
And a second surface side element forming step for forming the plurality of active elements or passive elements on the second surface side of the semiconductor substrate after the substrate polishing step. Method. The first surface side element forming step,
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed between the non-penetrating insulating isolation trench forming step and the substrate polishing step. The semiconductor substrate for element formation is
An epitaxial substrate in which a silicon epitaxial layer is formed on a bulk single crystal silicon substrate,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first surface side surface of the element forming semiconductor substrate is the silicon epitaxial layer. The non-through insulating isolation trench,
A non-through insulating isolation trench in which an insulator is embedded in the trench, a non-through insulating isolation trench in which a conductor is embedded in the trench through a sidewall oxide film, and a non-through insulating isolation trench in which the trench is hollow. The method for manufacturing a semiconductor device according to claim 1, wherein the method is any one of the above. An impurity diffusion layer having a different conductivity type or a different concentration from that of the semiconductor substrate is formed on at least one surface side of the semiconductor substrate,
5. The method of manufacturing a semiconductor device according to claim 1, wherein an ion implantation step for forming the impurity diffusion layer is performed after the substrate polishing step. 6. The impurity diffusion layer is
6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed in a part of the plurality of field regions.

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