JP4873002B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device in which an IGBT (insulated gate field effect transistor) and a free wheel diode (simply referred to as a diode) are formed in the same chip.

Conventionally, in a semiconductor device including an IGBT and a diode on the same chip, an n ⁺ type layer serving as a cathode layer is formed in the diode formation region, and a p ⁺ type layer serving as a collector layer is formed in the IGBT formation region (for example, Patent Document 1). The semiconductor device having such a structure is manufactured using the following manufacturing method because cracking or the like occurs when handling in a thin film state. 13 and 14 are cross-sectional views showing a manufacturing process of a semiconductor device in which a conventional IGBT and a diode are integrated.

  As shown in FIG. 13A, first, after preparing an n-type semiconductor substrate J1 such as an FZ substrate having a warp of 200 μm or more and forming an oxide film J2 on the main surface of the n-type semiconductor substrate J1, The oxide film J2 is patterned to form an opening pattern at a desired position. P-type impurity ions are implanted into the opening pattern formed in the oxide film J2 to form the p-type diffusion layer J3 and the p-type guard ring layer J4 in the outer peripheral region. Further, this opening pattern becomes an alignment target in the subsequent patterning.

  Next, as shown in FIG. 13B, after the p-type base region J5 is formed, the trench gate structure J6 is formed in the IGBT formation region, or the gate wiring J7, the emitter electrode J8, etc. are formed to form the MOS. Form the device.

  Then, as shown in FIG. 13C, after the support base J10 is attached to the main surface side (side on which the MOS device is formed) of the n-type semiconductor substrate J1 via an adhesive or the like, FIG. As shown in FIG. 4, the n-type semiconductor substrate J1 is thinned from the back surface side to obtain a desired thickness. At this time, the n-type semiconductor substrate J1 is thinned, but since the support base J10 is attached, handling is not performed in a thin film state. Further, as such a thinning method, for example, thinning by grinding or wet etching can be considered. However, when grinding is performed, a large amount of particles are generated.

Subsequently, as shown in FIG. 14A, n-type impurities are ion-implanted from the back side of the n-type semiconductor substrate J1. Then, as shown in FIG. 14B, after arranging the mask, it is patterned to open a desired position, and a p-type impurity is implanted from the opening, and after arranging the mask, it is patterned. After opening a desired position and injecting an n-type impurity from the opening, annealing is performed, so that in addition to the FS (field stop) layer J11, a p ⁺⁺ type collector layer J12, an n ⁺⁺ type cathode layer (First conductivity type layer) J13 is formed.

Next, as shown in FIG. 14C, after forming the back electrode J14 in contact with the p ⁺⁺ type collector layer J12 and the n ⁺⁺ type cathode layer J13, as shown in FIG. Remove J10. Thereby, a semiconductor device including the IGBT and the diode on the same chip is completed.
JP 2005-57235 A

However, according to the conventional manufacturing method as described above, after forming the MOS device on the main surface side of the n-type semiconductor substrate J1, in addition to the FS layer J11, the p ⁺⁺ type collector layer J12, the n ⁺⁺ type cathode layer J13 is formed. For this reason, annealing performed after ion implantation of n-type impurities or p-type impurities for forming them can be performed only by laser annealing. That is, a protective film and a wiring structure are provided on the main surface side of the n-type semiconductor substrate J1, for example, the protective film made of polyimide is 350 ° C., the wiring structure made of Al is 490 ° C., and the support base J10. Since the adhesive layer can only withstand high temperatures up to 200 ° C., it cannot be annealed so that the entire substrate becomes high temperature, and only laser annealing that can locally raise the temperature only on the back surface can be selected.

Since laser annealing is instantaneous annealing, the implanted impurities can be activated, but cannot be diffused, so that a withstand voltage leak is likely to occur. In particular, as described above, when the thinning from the back side of the n-type semiconductor substrate J1 is performed by grinding, a large amount of particles are generated, which plays a role of shielding at the time of ion implantation, and the FS layers J11, p ⁺ Defects in the ⁺ type collector layer J12 and the n ⁺⁺ type cathode layer J13 are generated, and the breakdown voltage leakage as described above is easily generated.

  An object of the present invention is to provide a method for manufacturing a semiconductor device that can perform annealing other than laser annealing and does not require handling in a thin film state.

  In order to achieve the above object, according to the first aspect of the present invention, a step of preparing a first conductivity type semiconductor substrate (30) having a main surface and a back surface opposite to the main surface; and a semiconductor substrate (30 ), A step of forming the collector layer (1a) and the first conductivity type layer (1b) on the back surface, and a support on the collector layer (1a) and first conductivity type layer (1b) side of the semiconductor substrate (30) The step of bonding the substrate (33), the step of thinning the main surface side of the semiconductor substrate (30) while being supported by the support substrate (33), and the thinning while being supported by the support substrate (33) Forming a base region (3), an emitter region (5), a trench (4), a gate insulating film (6), a gate electrode (7) and an upper electrode (12) on the main surface of the semiconductor substrate (30). And multiple heat A heat sink substrate (34) provided with a core (107) is prepared, and each heat sink (107) in the heat sink substrate (34) is bonded to the upper electrode (12), whereby the heat sink is attached to the semiconductor substrate (30). A step of attaching the substrate (34), a step of separating the support base (33) from the semiconductor substrate (30), and then dividing the plurality of heat sinks (107) into chips, and a heat sink (107) divided into chips. And a step of dicing the semiconductor substrate (30) in chip units to form the semiconductor chip (106).

  According to such a manufacturing method, since the collector layer (1a) in the IGBT formation region and the first conductivity type layer (1b) in the diode formation region are formed before forming the MOS device, annealing other than laser annealing can be performed. . Further, since the support base (33) is bonded before forming the MOS device, handling in a thin film state is not necessary. Furthermore, since the heat sink substrate (34) is attached before removing the support base (33), it is not necessary to handle in the thin film state even if the support base (33) is removed.

In the first aspect of the invention , in the step of attaching the heat sink substrate (34), a plurality of divided heat sinks (107) are provided as plate-shaped bases (34a) as the heat sink substrate (34). In the step of dividing the plurality of heat sinks (107) into chips by using the one attached to the semiconductor chip (106 ), the plurality of heat sinks (107) are separated from the base (34a) and divided into chips. In the step of forming a), dicing can be performed between the plurality of heat sinks (107) .

In this case, as described in claim 2 , in the step of attaching the heat sink substrate (34), the recess (34b) is formed as a base (34a) at a position corresponding to the location of the plurality of heat sinks (107). In the process of forming the heat sink substrate (34) by disposing each heat sink (107) in the recess (34b) and dividing the plurality of heat sinks (107) into chips, cooling processing is performed. By doing so, the plurality of heat sinks (107) can be separated from the base (34a) based on the difference in thermal expansion coefficient between the base (34a) and the plurality of heat sinks (107).

Further, as in the invention described in claim 3 , in the step of attaching the heat sink substrate (34), a plurality of divided heat sinks (107) are formed as plate-shaped bases (34a) as the heat sink substrate (34). In the step of dividing the plurality of heat sinks (107) into chips by using what is affixed to the base plate (34a ) between the plurality of heat sinks (107) when dicing the semiconductor substrate (30). ) Can be divided into chips by dicing at the same time.

In the invention according to claim 4, after the semiconductor chip (106) is formed by dicing, the heat sink (107) and the semiconductor substrate (30) are pasted to the adhesive tape (35) while the dicing is performed. Then, the process includes expanding the distance between the semiconductor chips (106) by expanding the adhesive tape (35).

  In this manner, the intervals between the semiconductor chips (106) can be increased substantially uniformly by expanding the adhesive tape (35). If each semiconductor chip (106) is sealed with the mold resin (115) in a state where this distance is secured, die mounting can be facilitated by increasing the distance between the semiconductor chips (106), and the semiconductor chip (106). ) Can be ensured.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a case where a semiconductor element in which an IGBT and a diode are integrated is applied as a switching element of an inverter circuit that drives a three-phase motor will be described as an example.

  FIG. 1 is a circuit diagram of an inverter circuit to which a semiconductor element provided in the semiconductor device of this embodiment is applied as a switching element.

  As shown in this figure, a U-phase, V phase constituted by two semiconductor elements 102 connected in series between a power supply line 100 to which a voltage Vcc from a power supply is applied and a GND line 101 connected to GND. Three circuits of phase and W phase are provided. Each semiconductor element 102 includes an n-channel type IGBT 103 and a diode 104 having a cathode connected to the collector of the IGBT 103 and an anode connected to the emitter. In each phase, the collector of the IGBT 103 in the upper arm and the cathode of the diode are connected to the power supply line 100, and the emitter of the IGBT 103 in the lower arm and the anode of the diode 104 are connected to the GND line 101. The collector of the IGBT 104 and the collector of the IGBT 103 of the lower arm and the cathode of the diode 104 are connected, and the lower arm and the upper arm are electrically connected to the three-phase motor 105 respectively. Has been.

  Two semiconductor elements 102 (for example, two semiconductor elements 102 in the U layer as shown by broken lines in the figure) provided in each phase in the inverter circuit having such a configuration are modularized to form one semiconductor device. It is configured.

  FIG. 2 is a cross-sectional view showing a structural example of the semiconductor element 102. FIG. 3 is a top view of the semiconductor chip 106 on which the semiconductor element 102 is formed. 4A and 4B are diagrams showing a detailed structure of the semiconductor device, where FIG. 4A is a layout diagram, FIG. 4B is a top view of FIG. 4A, FIG. 4C is a bottom view of FIG. (A) is AA 'sectional drawing, (e) is BB' sectional drawing of (a).

As shown in FIG. 2, in the semiconductor device of this embodiment, a cell region provided with the IGBT 103 and an outer peripheral region configured to surround the outer periphery thereof are formed. An FS layer (field stop layer) 2a composed of a high-concentration n-type impurity layer is provided on the surfaces of the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer (first conductivity type layer) 1b. At the same time, on the FS layer 2a, the p ⁺⁺ type collector layer 1a, the n ⁺⁺ type cathode layer 1b and the n ⁻ type drift layer 2 having a lower impurity concentration than the FS layer 2a are provided. The FS layer 2a is not necessarily required, but is provided for improving the breakdown voltage and steady loss performance by preventing the depletion layer from spreading and for controlling the injection amount of holes injected from the back side of the substrate. is there.

In the cell region, a p-type base region 3 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 2. Further, in the IGBT formation region in the cell region, a plurality of trenches 4 are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the trench 4 forms the p-type base region 3. Are separated into a plurality. Specifically, a plurality of trenches 4 are formed at a predetermined pitch (interval), and a stripe structure in which each trench 4 extends in parallel in the depth direction of FIG. After being installed, it is drawn around at the tip thereof to form an annular structure. And when it is set as an annular structure, the annular structure which each trench 4 comprises is arranged so that the longitudinal direction of adjacent multiple ring structures may become parallel, and a multiple ring structure may be constituted by making a plurality of sets one by one. Yes.

The p-type base region 3 is divided into a plurality of parts by the adjacent trenches 4, but at least a part of the p-type base region 3 becomes a channel p layer 3 a constituting the channel region, and n ⁺ A mold emitter region 5 is formed. In the present embodiment, the case where each divided p-type base region 3 becomes the channel p layer 3a is illustrated, but a part of the p-type base region 3 is a float layer in which the n ⁺ -type emitter region 5 is not formed. Also good.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed in contact with the side surface of the trench 4. More specifically, the structure extends in the shape of a rod along the longitudinal direction of the trench 4 and terminates inside the tip of the trench 4.

  Each trench 4 includes a gate insulating film 6 formed so as to cover the inner wall surface of each trench 4 and a gate electrode 7 formed of doped Poly-Si or the like formed on the surface of the gate insulating film 6. Embedded.

  Among these, the gate electrode 7 is electrically connected to each other in a cross section different from that in FIG. 1 and is connected to a doped Poly-Si layer 9 formed on the insulating film 8. A contact hole 10a is formed in the interlayer insulating film 10 on the doped Poly-Si layer 9, and the doped Poly-Si 9 and the gate wiring 11 to which a gate voltage is applied are connected through the contact hole 10a. Thus, each gate electrode 7 and the gate wiring 11 are electrically connected.

Furthermore, the n ⁺ -type emitter region 5 and the channel p layer 3a are electrically connected to the upper electrode 12 through a contact hole 10b formed in the interlayer insulating film 10, and the upper electrode 12 and the gate wiring 11 are protected from each other. 13 or the like. The IGBT 103 is configured by forming the lower electrode 14 on the back surface side of the p ⁺⁺ type collector layer 1a.

Further, in the diode formation region in the cell region, the trench 4 is not formed at a position corresponding to the n ⁺⁺ type cathode layer 1b. Therefore, the p type base region 3 is used as an anode, the n ⁻ type drift layer 2 and the n ⁺ type. A PN junction diode 104 is configured with the FS layer 2a and the n ⁺⁺ type cathode layer 1b as a cathode. The p-type base region 3 serving as an anode in the diode 104 is electrically connected to the upper electrode 12, and the n ⁺⁺ -type cathode layer 1 b serving as a part of the cathode is electrically connected to the lower electrode 14. ing.

  Therefore, the IGBT 103 and the diode 104 have a structure in which the emitter and the anode are electrically connected, and the collector and the cathode are electrically connected, so that they are connected in parallel in the same chip. .

On the other hand, in the outer peripheral region, a p-type diffusion layer 20 deeper than the p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2 so as to surround the outer periphery of the cell region. A p-type guard ring layer 21 is formed as a multiple ring structure so as to surround the outer periphery of the mold diffusion layer 20. Each p-type guard ring layer 21 is electrically connected to an outer peripheral electrode 22 arranged corresponding to each p-type guard ring layer 21 through a contact hole 10 c formed in the interlayer insulating film 10. Each outer peripheral electrode 22 is electrically isolated from each other and has a multiple ring structure like the p-type guard ring layer 21.

  As described above, the semiconductor element 102 in which the IGBT 103 and the diode 104 according to the present embodiment are integrated is configured.

  The semiconductor element 102 configured as described above is formed on a semiconductor chip 106 as shown in FIG. As shown in this figure, the semiconductor chip 106 is provided with a plurality of pads 106a to 106d. The pad 106 a occupies a large area in the semiconductor chip 106 and is used for connection to the upper electrode 12 electrically connected to the emitter of the IGBT 103 and the anode of the diode 104, and the pad 106 b is used to apply a gate voltage to the gate wiring 11 of the IGBT 103. The pad 106c is used for the emitter Kelvin. As shown by the broken line in FIG. 3, the entire back surface of the semiconductor chip 106 is a pad 106d, and is electrically connected to the collector of the IGBT 103 and the cathode of the diode 104. For connection to the lower electrode 14. Then, by electrically connecting a conductor to each of these pads 106a to 106d, electrical connection between each part in the semiconductor element 102 and the outside is achieved.

  Specifically, the semiconductor chip 106 of the upper arm is disposed with the upper electrode 12 on the front side of the paper and the lower electrode 14 on the other side of the paper in FIG. 4A, and the upper electrode 12 on the right side of the paper in FIG. 4D. The left electrode is arranged with the lower electrode 14 facing it.

  Regarding the semiconductor chip 106 of the upper arm, a heat sink 107 is connected to a pad 106 a provided on the upper electrode 12, and the heat sink 107 is connected to a lead 108 connected to the three-phase motor 105. A collector lead 109 is connected to a pad 106 d provided on the lower electrode 14. Further, the pad 106 b provided on the gate wiring 11 is connected to the gate lead 111 through the bonding wire 110. Then, the lead 108 is pulled out in the cross section of FIG. 4D, thereby making electrical connection with the three-phase motor 105. In the cross sections of FIGS. 4D and 4E, the collector lead 109 and the gate By pulling out the lead 111, a voltage Vcc from the power source is applied to the lower electrode 14 and a gate voltage can be applied through the gate wiring 11.

  On the other hand, the semiconductor chip 106 of the lower arm is disposed so that the front and back of the semiconductor chip 106 of the upper arm are reversed. That is, the semiconductor chip 106 of the lower arm is arranged with the lower electrode 14 on the front side of the paper and the upper electrode 12 on the opposite side of the paper in FIG. 4A, and the lower electrode 14 on the right side of the paper in FIG. Is arranged with the upper electrode 12 facing it.

  As for the semiconductor chip 106 of the lower arm, the heat sink 107 is connected to the pad 106 a provided on the upper electrode 12 and the heat sink 107 is connected to the GND line 101, similarly to the semiconductor chip 106 of the upper arm. It is connected to the emitter lead 112. A lead 108 connected to the three-phase motor 105 is connected to a pad 106 d provided on the lower electrode 14. Further, the pad 106 b provided on the gate wiring 11 is connected to the gate lead 114 via the bonding wire 113. Then, the lead 108 is pulled out in the cross section of FIG. 4D to make an electrical connection with the three-phase motor 105, and the gate lead 114 is pulled out in the cross section of FIG. 11, a gate voltage is applied, and the emitter lead 112 is drawn out in a cross section different from those in FIGS. 4D and 4E, whereby the lower electrode 14 is connected to GND.

  In such a configuration, the lead portions of the collector lead 109, the lead 108, the emitter lead 112, and the gate leads 111, 114 protrude, and in order to improve heat dissipation on both sides in the thickness direction of the semiconductor chip 106. By sealing with a mold resin 115 so that the surfaces of the collector lead 109, the lead 108 and the emitter lead 112 are exposed, a modularized semiconductor device is configured.

  Then, the manufacturing method of the semiconductor device which integrated IGBT and the diode of this embodiment is demonstrated. 5 and 6 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.

[Step shown in FIG. 5A]
First, an n-type silicon substrate 30 such as an FZ substrate having a warp of 200 μm or more is prepared, and n-type impurities are ion-implanted and annealed on the back surface opposite to the main surface of the n-type silicon substrate 30. . As a result, the n ⁺ -type FS layer 2a is formed on the back surface of the n-type silicon substrate 30, and the n ⁻ -type drift layer 2 is constituted by a portion of the n-type silicon substrate 30 other than the FS layer 2a.

[Step shown in FIG. 5B]
Next, after further ion-implanting p-type impurities using the mask on which the anode layer formation planned region of the FS layer 2a is opened, the cathode layer formation planned region is continued. Further, an n-type impurity is ion-implanted using a mask having an opening, and an annealing process is performed to form a p ⁺⁺ type collector layer 1a and an n ⁺⁺ type cathode layer 1b.

[Step shown in FIG. 5 (c)]
A bonding layer composed of Poly-Si or a silicon oxide film (SiO ₂ ) on the back side of the n-type silicon substrate 30, specifically, the surfaces of the p ⁺⁺ type collector layer 1 a and the n ⁺⁺ type cathode layer 1 b. 32 is deposited.

[Step shown in FIG. 5 (d)]
A support substrate 33 made of, for example, Si having a thickness of about 500 to 600 μm is bonded to the back surface side of the n-type silicon substrate 30 through the bonding layer 32. Although the support base 33 is bonded here, Si is deposited on the surface of the bonding layer 32 by CVD, epitaxially grown, or a support substrate made of another material is attached. For example, the support base 33 may be disposed on the back side of the n-type silicon substrate 30.

[Step shown in FIG. 5 (e)]
N-type silicon substrate 30 is thinned by grinding or etching from the main surface side. Thus, the n ⁻ type drift layer 2 is formed by the n type silicon substrate 30 with an appropriate thickness as the n ⁻ type drift layer 2.

[Step shown in FIG. 6A]
A p-type diffusion layer 20 and a p-type guard ring layer 21 are formed in the surface layer portion of the n ⁻ -type drift layer 2, and a p-type base region 3 is formed. Further, the trench 4, the n ⁺ -type emitter region 5, the gate insulating film 6, the gate electrode 7, the insulating film 8, the doped Poly-Si 9, the interlayer insulating film 10, the gate are formed on the IGBT forming region and the diode forming region by a known method. By forming the wiring 11, the upper electrode 12, and the protective film 13, a MOS device is formed. Also, the outer peripheral electrode 22 and the protective film 13 are formed in the outer peripheral region. In this figure, the structure of the MOS device is shown in a simplified manner, but in detail, a plurality of structures having the structure of FIG. 2 are formed.

[Step shown in FIG. 6B]
A plurality of heat sinks 107 are integrated on the main surface side of the n-type silicon substrate 30, specifically the surfaces of the upper electrode 12 and the protective film 13, and a plate-shaped heat sink substrate 34 is attached. On the back surface of the heat sink substrate 34, a convex portion is formed at a portion corresponding to the upper electrode 12, and the upper electrode 12 is brought into electrical and physical contact.

[Step shown in FIG. 6 (c)]
On the back side of the n-type silicon substrate 30, the support base 33 and the bonding layer 32 are removed to expose the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. At this time, since the heat sink substrate 34 is attached, the n-type silicon substrate 30 on which the MOS device or the like is formed can be handled without being handled in a thin film state.

For this step, any method may be used. For example, a method of removing the support substrate 33 and the bonding layer 32 by grinding or wet etching may be employed. In the case of wet etching, if the bonding layer 32 is made of Poly-Si, the etching is automatically stopped when the Poly-Si surface comes out, and then the poly-Si and SiO ₂ are selectively etched. Thus, the support base 33 and the bonding layer 32 can be removed with high accuracy. In addition, the support base 33 and the bonding layer 32 can be removed by a technique such as slice cut, smart cut, eltran, or laser lift-off.

[Step shown in FIG. 6 (d)]
Lower electrodes 14 are formed on the surfaces of the p ⁺⁺ type collector layer 1a and the n ⁺⁺ type cathode layer 1b. Finally, the n-type silicon substrate 30 on which the MOS device is formed together with the heat sink substrate 34 is diced and divided into chips. As a result, a structure in which the heat sink 107 is bonded onto the semiconductor chip 106 in FIGS. 4D and 4E is completed. In addition, if the part corresponding to the exposed part (pad 106b) of the gate wiring 11 other than the part corresponding to the upper electrode 12 in the heat sink substrate 34 is opened, it is only divided into chips by dicing cut. However, if the portion corresponding to the gate wiring 11 is not opened, the heat sink substrate 34 is diced and cut in advance in order to expose the portion corresponding to the exposed portion of the gate wiring 11 before dividing into chips. You may perform the process to do.

  Although not shown in the drawings, the pad 106b for applying a gate voltage to the gate wiring 11 and the gate lead 111 are bonded by a bonding wire 110. A collector lead 109 is bonded to the lower electrode 14 of the semiconductor chip 106 on which the upper arm semiconductor element 102 is formed. Further, the lead 108 is bonded to the upper electrode 12 of the semiconductor chip 106 on which the semiconductor element 102 of the upper arm is formed and the lower electrode 14 of the semiconductor chip 106 on which the semiconductor element 102 of the lower arm is formed. Further, an emitter lead 112 is connected to the upper electrode 12 of the semiconductor chip 106 on which the lower arm semiconductor element 102 is formed. Then, by performing resin molding or the like and sealing with the mold resin 115, the semiconductor device according to the present embodiment is completed.

As described above, according to the method of manufacturing a semiconductor device in which the IGBT and the diode described in the present embodiment are integrated, the FS layer 2a, the p ⁺⁺ type collector layer 1a, and the n ⁺⁺ type cathode are formed in advance before forming the MOS device. Since the layer 1b is formed, annealing other than laser annealing can be performed. Further, since the heat sink substrate 34 constituting the heat sink 107 is bonded before forming the MOS device, handling in a thin film state is not necessary. Then, by dicing and cutting the n-type silicon substrate 30 on which the MOS device is formed together with the heat sink substrate 34, the semiconductor chip 106 integrated with the heat sink 107 can be formed, and the semiconductor chip 106 can be handled together with the heat sink 107. Even in the subsequent steps, handling in the thin film state is not necessary. Even after dicing, for example, the semiconductor chip 106 having a size of about 10 mm □ and a thickness of about 0.03 to 0.2 mm is held by the heat sink 107 having a thickness of about 1 mm, so that handling can be easily performed.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, a part of the configuration of the semiconductor device is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different parts will be described.

  In the present embodiment, a semiconductor device in which all of the U phase, the V phase, and the W phase are modularized and integrated will be described. 7A and 7B are diagrams showing the detailed structure of the semiconductor device of this embodiment, where FIG. 7A is a layout diagram, FIG. 7B is a top view of FIG. 7A, FIG. 7C is a bottom view of FIG. d) is a cross-sectional view taken along the line CC ′ of (a), and (e) is a cross-sectional view taken along the line DD ″ of FIG.

  As shown in FIG. 7A, three semiconductor chips 106 are arranged on each of the upper and lower sides, the upper three are the three semiconductor chips 106 of the upper arm, and the lower three are the three semiconductor chips of the lower arm. 106. Then, each phase from the U phase to the W phase is configured with two semiconductor chips 106 arranged in the vertical direction as a set.

  As shown in FIGS. 7A to 7E, the arrangement of the semiconductor chips 106 of the U-phase to W-phase upper and lower arms is the same as that in the first embodiment (see FIG. 4). The lower electrode 14 of the semiconductor chip 106 in the upper arm of each phase is electrically connected to the common collector lead 109, and the upper electrode 12 of the semiconductor chip 106 in the lower arm of each phase is connected to the common emitter lead. 112 is electrically connected to 112. With such a structure, a semiconductor device is configured in which all six semiconductor elements 102 constituting the three phases from the U phase to the W phase are modularized into one. The other structure is the same as that of the first embodiment, and the connection form between each phase of the semiconductor chip 106 and various leads is the same as that of the first embodiment.

  Thus, a semiconductor device in which all six semiconductor chips 106 constituting each phase are integrated can be obtained.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, a part of the configuration of the semiconductor device is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different parts will be described.

  FIG. 8 is a circuit diagram of an inverter circuit to which the semiconductor element 102 provided in the semiconductor device according to the present embodiment is applied as a switching element. FIG. 9 is a cross-sectional view of the semiconductor device according to the present embodiment, showing a cross-sectional structure corresponding to FIG. 4D or FIG. 7D.

As shown in FIG. 8, the IGBT 103 provided in the three semiconductor elements 102 of the lower arm of each phase is configured as a p-channel type. Such a p-channel type IGBT 103 is basically obtained by reversing the conductivity type of each component shown in FIG. 2 described in the first embodiment. That is, in the first embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in this embodiment, the first conductivity type is p-type and the second conductivity type is n-type. In the structure, specifically, the IGBT formation region, an n ⁺⁺ type collector layer, a p ⁺ type FS layer, a p − type drift layer, an n type base region, and a p ⁺ type emitter region are formed thereon, In the diode formation region, a PN junction having a p ⁺⁺ type anode region, a p ⁺ type FS layer and a p− type drift layer as an anode and an n type base region as a cathode is formed.

  In such a semiconductor device, the emitter of the n-channel type IGBT 103 and the emitter of the p-channel type IGBT 103 are electrically connected. The IGBT 103 that is the lower arm has a structure different from that of the IGBT 103 that is the upper arm, and thus the semiconductor chips 106 having completely different configurations are manufactured. At this time, the basic structure of the IGBT 103 serving as the lower arm is the same as that of the IGBT 103 serving as the upper arm, and the emitters of the n-channel type and p-channel type IGBT 103 are connected to each other. For this reason, as shown in FIG. 9, the heat sink 107 connected to the n-channel type emitter via the upper electrode 12 and the heat sink 107 connected to the p-channel type emitter via the upper electrode 12 are both semiconductors. The heat sink 107 is disposed so as to be in the same direction with respect to the chip 106, and both the heat sinks 107 are bonded to the same lead 108.

  In this manner, a semiconductor device can be configured by combining the n-channel type and the p-channel type IGBT 103. The direction of the semiconductor chip 106 and the heat sink 107 in which the n-channel type IGBT 103 is formed can be matched with the direction of the semiconductor chip 106 and the heat sink 107 in which the p-channel type IGBT 103 is formed. Compared to the case, it is possible to facilitate the connection of the bonding wires 110 and 113 connected to the gate.

  In addition, although the case where the lower arm IGBT 103 is a p-channel type has been described here for the first embodiment, the lower arm IGBT 103 is similarly a p-channel type for the second embodiment. It is also good. In this case, the same effect as described above can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, a part of the semiconductor device manufacturing method is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different parts will be described.

  In the present embodiment, after performing the manufacturing process of FIGS. 5A to 5D and FIG. 6A of the first embodiment, the first implementation as the heat sink substrate 34 in the manufacturing process of FIG. Use a different form.

  FIG. 10 is a front view of the heat sink substrate 34 used in the present embodiment. As shown in this figure, the heat sink substrate 34 is configured by arranging a plurality of heat sinks 107 on the silicon substrate 34a with the silicon substrate 34a as a base. A plurality of recesses 34b formed at a pitch corresponding to each cell (semiconductor chip 106) is formed in the silicon substrate 34a, and a heat sink 107 is disposed in each recess 34b, whereby each cell (semiconductor chip 106) is formed. The heat sink 107 is disposed at a position corresponding to (). The heat sink 107 may be attached to the silicon substrate 34a by any method, but in order to reduce the influence of the difference in thermal expansion coefficient between the heat sink 107 and the silicon substrate 34a, It is preferable to apply a silicon resin material for absorbing thermal expansion to the substrate.

  After the heat sink substrate 34 is prepared, as shown in FIG. 11, the heat sink 107 is disposed facing the surface side of the n-type silicon substrate 30 after the formation of the MOS device, and each heat sink 107 is placed on the upper electrode 12 of each cell. Are joined to each other through a conductor material such as solder. At this time, when joining by soldering, for example, a reflow process of about 300 ° C. is performed, so that the heat sink substrate 34, the n-type silicon substrate 30 and the like are thermally expanded, but the base of the heat sink substrate 34 is also an n-type silicon substrate. 30 and the same thermal expansion coefficient, it is possible to prevent pitch deviation between the heat sinks 107 due to heating.

  Then, the heat sink 107 is separated from the silicon substrate 34a by performing, for example, a cooling process of −40 ° C. after the bonding. As described above, when the silicon resin material is arranged between the heat sink 107 and the recess 34b, the thermal expansion of the constituent material (for example, Cu) of the heat sink 107 is absorbed at the time of heating at 300 ° C., and −40 ° C. It becomes possible to easily separate the heat sink 107 from the silicon substrate 34a due to shrinkage of the constituent material of the heat sink 107 at the time of cooling.

After this, if necessary, measure the withstand voltage at low temperature. At this stage, the n-type silicon substrate 30 has not yet been diced. For this reason, the heat sink 107 is formed at a position corresponding to each semiconductor element 102 in the n-type silicon substrate 30 in a wafer state in which a plurality of semiconductor elements 102 are formed. Therefore, by setting the lower electrode 14 connected to the p ⁺⁺ collector layer 1a on the back surface side to a common potential and probing each emitter potential through each heat sink 107, the withstand voltage at low temperature can be measured.

  Further, if a probe capable of controlling each gate electrode 7 is provided for each semiconductor chip 106 and, for example, a common gate potential is applied, the on-characteristics of the IGBT can be measured.

  Finally, the n-type silicon substrate 30 on which the MOS device is formed is divided into chips by dicing cutting. As a result, a structure in which the heat sink 107 is bonded onto the semiconductor chip 106 in FIGS. 4D and 4E is completed.

  Thereafter, similarly to the first embodiment, a semiconductor device having the same structure as that of the first embodiment can be manufactured by performing various lead connection processes, a sealing process using the mold resin 115, and the like. . By using the manufacturing method as described above, the same effect as that of the first embodiment can be obtained.

  Further, in the manufacturing method of the present embodiment, a structure in which the heat sink 107 is originally separated is used. For this reason, unlike the case where the heat sink substrate 34 has an integrated structure of a plurality of heat sinks 107, it is not necessary to cut and separate the heat sink substrates 34 by dicing cut. This simplifies the shape of the substrate and prevents it from being affected by residues during dicing.

  Further, the silicon substrate 34a after the heat sink 107 is separated can be reused by reattaching the heat sink 107 again.

  Here, the case where the heat sink 107 is made of Cu, for example, has been described as an example. However, instead of Cu, a material having a small difference in thermal expansion coefficient from the constituent material of the base, such as Mo, is used. Even if the silicon substrate 34a is diced and cut, the thermal expansion coefficient can be matched. That is, Cu is about 17 ppm / ° C., Mo is about 5 ppm / ° C., and Si is 3 ppm / ° C. For this reason, by using Mo whose thermal expansion coefficient is closer to that of Si than Cu, distortion due to the difference in thermal expansion coefficient is reduced, so that dicing cut is performed together with the silicon substrate 34 a, and the silicon substrate 34 a is also part of the heat sink 107. It can also be used. Since silicon has a high thermal conductivity, the silicon substrate 34 a may be used as a part of the heat sink 107 in this way.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The present embodiment relates to a case where the manufacturing method described in the fourth embodiment is applied to a semiconductor device in which a plurality of semiconductor chips are integrated. The other parts are the same as those in the fourth embodiment, and therefore different parts are described. Only explained.

  In the present embodiment, the process shown in FIGS. 5A to 5D and FIG. 6A of the first embodiment is performed, and then the process shown in FIG. 11 of the fourth embodiment is further performed. As shown in FIG. 12A, a structure in which a heat sink 107 is bonded to the upper electrode 12 of each cell formed on the n-type silicon substrate 30 is created. That is, after preparing the heat sink substrate 34 in which a plurality of heat sinks 107 are arranged on the silicon substrate 34 a, each heat sink 107 is bonded to the upper electrode 12 of each cell formed on the n-type silicon substrate 30. Then, the heat sink 107 is separated from the silicon substrate 34a.

  Next, as shown in FIG. 12B, the n-type silicon substrate 30 is divided into chips by dicing and cutting. At this time, the distance between the semiconductor chips 106 is the separation width by dicing cut. Then, as shown in FIG. 12 (c), after the adhesive tape 35 is pasted with the dicing cut being performed, an expanding process is performed in which the adhesive tape 35 is pulled and stretched as shown in FIG. 12 (d). Do. Thereby, the intervals between the semiconductor chips 106 are spread almost uniformly. If each semiconductor chip 106 is sealed with the mold resin 115 in a state where this interval is secured, die mounting can be facilitated by increasing the interval of the semiconductor chip 106 and the insulation breakdown voltage of the semiconductor chip 106 can be secured. Is possible.

  Specifically, three semiconductor chips 106 each having the continuous IGBT shown in FIG. 12D are mounted on the leads 109 connected to the Vcc terminal to which the voltage Vcc shown in FIG. . As described above, when appropriate expansion is performed in consideration of the pressure resistance and the mounting clearance, mounting structures having different forms can be realized. The present invention can also be applied to devices having different electrical characteristics with a withstand voltage of 600 V and 1200 V by simply changing the expansion rate in a common form.

  The same applies to the mounting of each phase (U phase, V phase, W phase) on each output terminal. Instead of the lead 109 connected to the Vcc terminal, three semiconductor chips 106 in which IGBTs are continuously formed as shown in FIG. 12D are mounted on the lead 108 connected on the outer periphery (not shown). In this way, the inverter circuit of FIG. 1 can be configured.

  In addition, the process of expanding in the state which affixed the semiconductor chip 106 on such an adhesive tape 35 is not restricted to 4th Embodiment, It is applicable also to the said 1st-3rd Embodiment. it can.

(Other embodiments)
In each of the above-described embodiments, an n-channel type IGBT in which the first conductivity type is n-type and the second conductivity type is p-type is basically described as an example. A channel type IGBT can also be applied. In that case, in the IGBT formation region, an n ⁺⁺ type collector layer is formed, on which a p ⁺ type FS layer, a p − type drift layer, an n type base region, and a p ⁺ type emitter region are formed, and in the diode formation region Thus, a PN junction having the p ⁺⁺ type anode region, the p ⁺ type FS layer and the p − type drift layer as an anode and the n type base region as a cathode is formed.

In the present invention, the first conductivity type layer refers to the back side of the diode formation region, that is, the n ⁺⁺ type cathode layer 1b and the p channel type in the case of a diode formed on the same chip as the n channel type IGBT. In the case of a diode formed of the same chip as the IGBT, it means a p ⁺⁺ type anode region.

1 is a circuit diagram of an inverter circuit in which a semiconductor element 102 included in a semiconductor device according to a first embodiment of the present invention is applied as a switching element. 3 is a cross-sectional view showing a structural example of a semiconductor element 102. FIG. It is a top view of the semiconductor chip 106 in which the semiconductor element 102 is formed. 1A is a layout diagram, FIG. 2B is a top view of FIG. 1A, FIG. 3C is a bottom view of FIG. 1A, and FIG. -A 'sectional drawing, (e) is BB' sectional drawing of (a). It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 1st Embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; It is the figure which showed the detailed structure of the semiconductor device concerning 2nd Embodiment of this invention, (a) is a layout figure, (b) is a top view of (a), (c) is a bottom view of (a), (D) is CC 'sectional drawing of (a), (e) is DD' 'sectional drawing of (a). It is a circuit diagram of the inverter circuit to which the semiconductor element with which the semiconductor device concerning 3rd Embodiment of this invention is provided is applied as a switching element. It is sectional drawing of the semiconductor device shown in FIG. It is a front view of the heat sink board | substrate 34 used in 4th Embodiment of this invention. FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor device using the heat sink substrate 34 shown in FIG. 10. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning 5th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which integrated the conventional IGBT and the diode. It is sectional drawing which shows the manufacturing process of the semiconductor device which integrated IGBT and the diode which were shown in FIG.

Explanation of symbols

1a p ⁺⁺ type collector layer 1b n ⁺⁺ type cathode layer 2 n ⁻ type drift layer 2a FS layer 3 p type base region 4 trench 5 n ⁺ type emitter region 7 gate electrode 12 upper electrode 14 lower electrode 30 n type silicon substrate 32 Bonding layer 33 Support base 34 Heat sink substrate 35 Adhesive tape 102 Semiconductor element 103 IGBT
104 Diode 106 Semiconductor chip 107 Heat sink

Claims (4)

A first conductivity type layer (1b) provided in the diode formation region and a second conductivity type collector layer (1a) formed in the IGBT formation region;
A first conductivity type drift layer (2) disposed on the first conductivity type layer (1b) and the collector layer (1a);
A second conductivity type base region (3) formed on the drift layer (2);
A trench (4) formed to penetrate the base region (3) and reach the drift layer (2);
A first conductivity type emitter region (5) formed in contact with the side surface of the trench (4) in the base region (3);
A gate insulating film (6) formed on the surface of the trench (4);
A gate electrode (7) formed on the gate insulating film (6) in the trench (4);
An upper electrode (12) electrically connected to the base region (3) and the emitter region (5);
A lower electrode (14) formed on the back side of the collector layer (1a),
The collector layer (1a), the drift layer (2), the base region (3), the emitter region (5), and the gate electrode (in the trench (4)) provided in the IGBT formation region. 7) In the IGBT,
A diode is formed by a PN junction formed by the first conductivity type layer (1b) and the drift layer (2) provided in the diode formation region and the second conductivity type base region, and the IGBT and the diode And a method of manufacturing a semiconductor device integrated with
Providing a first conductivity type semiconductor substrate (30) having a main surface and a back surface opposite to the main surface;
Forming the collector layer (1a) and the first conductivity type layer (1b) on the back surface of the semiconductor substrate (30);
Bonding a support substrate (33) to the collector layer (1a) and the first conductivity type layer (1b) side of the semiconductor substrate (30);
Thinning the main surface side of the semiconductor substrate (30) in a state of being supported by the support base (33);
The base region (3), the emitter region (5), the trench (4), and the gate insulation are formed on the main surface of the thinned semiconductor substrate (30) while being supported by the support base (33). Forming a film (6), the gate electrode (7) and the upper electrode (12);
A heat sink substrate (34) provided with a plurality of heat sinks (107) is prepared, and each of the heat sinks (107) in the heat sink substrate (34) is bonded to the upper electrode (12), whereby the semiconductor substrate ( 30) attaching the heat sink substrate (34) to
Separating the support base (33) from the semiconductor substrate (30) and then dividing the plurality of heat sinks (107) into chips;
Forming a semiconductor chip (106) by dicing the semiconductor substrate (30) into chips in a state where the heat sink (107) divided into chips is provided ,
In the step of attaching the heat sink substrate (34), as the heat sink substrate (34), one in which the plurality of divided heat sinks (107) are attached to a plate-like base (34a) is used. ,
In the step of dividing the plurality of heat sinks (107) into chips, the plurality of heat sinks (107) are separated from the base (34a) to be divided into chips.
In the step of forming the semiconductor chip (106), the dicing is performed between the plurality of heat sinks (107) . In the step of affixing the heat sink substrate (34), as the base (34a), a substrate in which a recess (34b) is formed at a position corresponding to the arrangement location of the plurality of heat sinks (107) is used. The heat sink substrate (34) is configured by disposing each heat sink (107) in the recess (34b),
In the step of dividing the plurality of heat sinks (107) into chips, a cooling process is performed, so that the base (34a) is based on a difference in thermal expansion coefficient between the base (34a) and the plurality of heat sinks (107). The method of manufacturing a semiconductor device according to claim 1 , wherein the plurality of heat sinks are separated from the heat sink. A first conductivity type layer (1b) provided in the diode formation region and a second conductivity type collector layer (1a) formed in the IGBT formation region;
A first conductivity type drift layer (2) disposed on the first conductivity type layer (1b) and the collector layer (1a);
A second conductivity type base region (3) formed on the drift layer (2);
A trench (4) formed to penetrate the base region (3) and reach the drift layer (2);
A first conductivity type emitter region (5) formed in contact with the side surface of the trench (4) in the base region (3);
A gate insulating film (6) formed on the surface of the trench (4);
A gate electrode (7) formed on the gate insulating film (6) in the trench (4);
An upper electrode (12) electrically connected to the base region (3) and the emitter region (5);
A lower electrode (14) formed on the back side of the collector layer (1a),
The collector layer (1a), the drift layer (2), the base region (3), the emitter region (5), and the gate electrode (in the trench (4)) provided in the IGBT formation region. 7) In the IGBT,
A diode is formed by a PN junction formed by the first conductivity type layer (1b) and the drift layer (2) provided in the diode formation region and the second conductivity type base region, and the IGBT and the diode And a method of manufacturing a semiconductor device integrated with
Providing a first conductivity type semiconductor substrate (30) having a main surface and a back surface opposite to the main surface;
Forming the collector layer (1a) and the first conductivity type layer (1b) on the back surface of the semiconductor substrate (30);
Bonding a support substrate (33) to the collector layer (1a) and the first conductivity type layer (1b) side of the semiconductor substrate (30);
Thinning the main surface side of the semiconductor substrate (30) in a state of being supported by the support base (33);
The base region (3), the emitter region (5), the trench (4), and the gate insulation are formed on the main surface of the thinned semiconductor substrate (30) while being supported by the support base (33). Forming a film (6), the gate electrode (7) and the upper electrode (12);
A heat sink substrate (34) provided with a plurality of heat sinks (107) is prepared, and each of the heat sinks (107) in the heat sink substrate (34) is bonded to the upper electrode (12), whereby the semiconductor substrate ( 30) attaching the heat sink substrate (34) to
Separating the support base (33) from the semiconductor substrate (30) and then dividing the plurality of heat sinks (107) into chips;
Forming a semiconductor chip (106) by dicing the semiconductor substrate (30) into chips in a state where the heat sink (107) divided into chips is provided ,
In the step of attaching the heat sink substrate (34), as the heat sink substrate (34), one in which the plurality of divided heat sinks (107) are attached to a plate-like base (34a) is used. ,
In the step of dividing the plurality of heat sinks (107) into chips, when the semiconductor substrate (30) is diced, the base (34a) is simultaneously diced between the plurality of heat sinks (107). A method for manufacturing a semiconductor device, wherein the method is divided into chips . After the semiconductor chip (106) is formed by the dicing, the heat sink (107) and the semiconductor substrate (30) are attached to the adhesive tape (35) while the dicing is performed, and then the adhesive tape the method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that it includes the step of increasing the distance between the semiconductor chip (106) to each other by expanded (35).

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