WO2015040712A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2015040712A1
WO2015040712A1 PCT/JP2013/075235 JP2013075235W WO2015040712A1 WO 2015040712 A1 WO2015040712 A1 WO 2015040712A1 JP 2013075235 W JP2013075235 W JP 2013075235W WO 2015040712 A1 WO2015040712 A1 WO 2015040712A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
region
surface electrode
insulating film
semiconductor device
Prior art date
Application number
PCT/JP2013/075235
Other languages
French (fr)
Japanese (ja)
Inventor
茂男 遠井
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112013007447.8T priority Critical patent/DE112013007447B4/en
Priority to PCT/JP2013/075235 priority patent/WO2015040712A1/en
Priority to JP2015537502A priority patent/JP6046262B2/en
Priority to CN201380079685.7A priority patent/CN105556661B/en
Publication of WO2015040712A1 publication Critical patent/WO2015040712A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device using a solder joint for joining a surface electrode and a wiring metal such as a lead frame, and more particularly to a power device that conducts a large current.
  • solder bonding is used for bonding at the surface electrode of the power chip.
  • a lead frame or the like can be bonded to the surface electrode by using the solder bonding.
  • solder bonding it is necessary to form a metal layer (Ni or the like) for bonding with solder on the surface electrode (for example, aluminum electrode) of the semiconductor element.
  • the surface electrode When soldering the surface electrode as described above, under conditions involving heating or cooling such as power cycle or thermal cycle, the surface electrode from a structure such as a lead frame joined to the surface electrode due to a difference in thermal expansion coefficient. Mechanical stress (stress) is generated on the (aluminum electrode). The stress is concentrated particularly on the end portion of the bonding layer which is an alloy layer of a metal layer and solder.
  • the surface electrode located in the vicinity of the end portion of the bonding layer may be broken, and the gate structure formed thereunder may be broken. The breakage and breakage cause the semiconductor element to become inoperable.
  • the present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having high resistance under conditions involving heating or cooling when soldering surface electrodes. To do.
  • a semiconductor device includes a first conductivity type drift layer, a gate structure formed in a first region which is a partial region on the drift layer, the first region, and the drift layer.
  • a diode is formed in the region on the surface electrode and in the second region.
  • a semiconductor device includes a first conductivity type drift layer, a gate structure formed in a first region which is a partial region on the drift layer, the first region, and the drift A surface electrode, a bonding layer partially formed on the surface electrode, and a solder layer formed on the bonding layer, which are disposed to cover a second region, which is another region on the layer, A lead frame disposed on the solder layer and a wiring structure disposed on the second region, the bonding layer covering a region on the surface electrode corresponding to the first region; and An end portion of the bonding layer is located in a region on the surface electrode corresponding to the second region, the surface electrode is disposed so as to cover the wiring structure, and the wiring structure includes polysilicon and the polysilicon.
  • a semiconductor device includes a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and the base layer surface layer reaching the drift layer.
  • a surface electrode, an insulating layer partially formed on the surface electrode, an end portion of the insulating layer, and a region on the surface electrode where the insulating layer is not formed are formed. Formed on the bonding layer.
  • the solder layer characterized in that it comprises a lead frame disposed on said solder layer.
  • a semiconductor device includes a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and the base layer surface layer reaching the drift layer.
  • top surface the side surface, or the bottom surface are used. These terms are used to distinguish each surface for convenience, and are related to the actual vertical and horizontal directions. do not do.
  • FIG. 6 is a perspective view of a semiconductor device with a surface electrode soldered (before mold sealing) related to the base technology.
  • FIG. 7 is a cross-sectional view of the semiconductor device (before mold sealing) with the surface electrodes soldered.
  • the surface electrode 2 (for example, an aluminum electrode) is disposed on the upper surface of the semiconductor element, and the insulating layer 5 (for example, a polyimide layer) is disposed in the region on the semiconductor element other than the surface electrode 2 is disposed. ) Is formed.
  • the surface electrode 2 and the lead frame 1 are joined via the solder layer 3.
  • a bonding layer 4 that is an alloy of Ni or the like and solder is formed between the solder layer 3 and the surface electrode 2.
  • a semiconductor element is formed below the surface electrode 2.
  • the semiconductor element shown in this embodiment is an IGBT (Insulated Gate Bipolar Transistor), but the semiconductor element that can be applied as a semiconductor element is not limited to this.
  • the semiconductor element includes a collector electrode 15, a p-type collector layer 14 formed on the collector electrode 15, an n ⁇ type drift layer 12 formed on the collector layer 14, and an n + layer 11. , A p-type base layer 10, a gate electrode 9, a gate insulating film 8, an n + -type source layer 7, and an interlayer insulating film 6. The n + layer 11 may not be provided.
  • the n + layer 11 is formed on the drift layer 12.
  • the base layer 10 is formed on the n + layer 11.
  • a groove 13 reaching the drift layer 12 from the surface layer of the base layer 10 is formed, and a gate insulating film 8 is formed along the side surface and the bottom surface of the groove 13.
  • a gate electrode 9 is formed inside the gate insulating film 8 in the trench 13.
  • the source layer 7 is formed with the groove 13 in between on the surface of the base layer.
  • An interlayer insulating film 6 is formed so as to cover the trench 13 and a part of the source layer 7.
  • the region below the bonding layer 4 includes the surface electrode 2 and the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6. ) Is arranged.
  • the embodiment described below relates to a semiconductor device that solves the above problems.
  • FIG. 1 is a cross-sectional view of a semiconductor device in which surface electrodes according to the present embodiment are soldered.
  • symbol is attached
  • the gate structure of the semiconductor element (base layer 10, gate electrode 9, gate insulating film 8, n + type source layer 7).
  • a region where the insulating layer 6 is formed is an IGBT region, and a region where no gate structure is formed is a diode region.
  • the drift layer 12 and the base layer 10 are formed, and the collector layer 14 is not formed.
  • a PiN diode is formed by a PN junction between the drift layer 12 and the base layer 10.
  • the semiconductor device shown in FIG. 1 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting-IGBT) including an IGBT region and a diode region.
  • RC-IGBT Reverse Conducting-IGBT
  • the junction layer 40 is arranged above the IGBT region, and the end of the junction layer 40 is located above the diode region.
  • the area other than the IGBT area can be used as a diode area. Therefore, since the element area can be effectively used, an economical reverse conduction type IGBT can be realized.
  • the IGBT region and the diode region are not continuous and formed with a predetermined interval, but the interval does not exist and the IGBT region and the diode region are formed continuously. It may be.
  • the thickness of the base layer 10 in the interval is formed larger than the thickness of the base layer 10 in the IGBT region and the thickness of the base layer 10 in the diode region.
  • the thickness of the base layer 10 in the interval may be formed with the same thickness as the thickness of the base layer 10 in the IGBT region and the thickness of the base layer 10 in the diode region.
  • FIG. 2 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment.
  • symbol is attached
  • the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6) is formed.
  • the region is referred to as an IGBT region, and the region where no gate structure is formed is referred to as a diode region.
  • the drift layer 12A is formed, and the base layer 10 and the collector layer 14 are not formed.
  • a Schottky barrier diode SBD is formed by a Schottky junction between the drift layer 12 ⁇ / b> A and the surface electrode 2.
  • the junction layer 40 is disposed above the IGBT region, and the end portion of the junction layer 40 is located above the diode region.
  • the area other than the IGBT area can be used as a diode area. Therefore, since the element area can be effectively used, an economical reverse conduction type IGBT can be realized.
  • FIG. 3 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment.
  • symbol is attached
  • the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6) is formed.
  • the formed region is referred to as an IGBT region, and the region where no gate structure is formed is referred to as an invalid region.
  • the drift layer 12, the base layer 10, and the collector layer 14 are formed, but the collector layer 14 may not be formed.
  • a wiring structure including polysilicon 16 and an interlayer insulating film 17 formed so as to cover the polysilicon 16 is disposed on the invalid region. If a PiN diode is formed in the invalid region, it can be used as a temperature sensing diode, and the wiring structure can be used to connect between the temperature sensing diode and the pad.
  • the bonding layer 40 is disposed above the IGBT region, and the end of the bonding layer 40 is positioned above the invalid region.
  • the polysilicon 16 disposed below breaks and can be detected as an abnormality in temperature sensing diode characteristics. Therefore, it is possible to detect deterioration of the semiconductor element due to power cycle or thermal cycle.
  • FIG. 9 is a top view of the semiconductor device related to the base technology.
  • the semiconductor device related to the base technology when the temperature sensing diode 18 and the pad 19 are disposed as illustrated, the polysilicon 16a in the wiring structure is formed as illustrated.
  • FIG. 10 is a top view of the semiconductor device according to another aspect of the present embodiment.
  • the polysilicon 16 in the wiring structure extends along the end of the region where the bonding layer 40 is formed. It is formed as follows. More precisely, the polysilicon 16 is formed so as to be located below the end of the bonding layer 40.
  • the wiring aspect of a wiring structure is not restricted to what is shown by FIG. 10, The ratio of the part along the edge part of the area
  • the semiconductor device is formed in the first conductivity type (n-type) drift layer 12 and the first region (IGBT region) which is a partial region on the drift layer 12.
  • a surface electrode 2 disposed so as to cover the second region (diode region), which is the other region on the IGBT region and the drift layer 12, and a bonding layer 40 partially formed on the surface electrode 2.
  • a solder layer 3 formed on the bonding layer 40 and a lead frame 1 disposed on the solder layer 3.
  • the bonding layer 40 covers a region on the surface electrode 2 corresponding to the IGBT region, and an end portion of the bonding layer 40 is located in a region on the surface electrode 2 corresponding to the diode region. A diode is formed in the diode region.
  • the portion where the break reaches is the diode region. Is suppressed from being destroyed. Therefore, a high tolerance can be realized under conditions involving heating or cooling (power cycle or thermal cycle).
  • the diode region is formed at the location where the breakage reaches, the element area can be effectively utilized.
  • the gate structure reaches the base layer 10 of the second conductivity type (p-type) formed in the IGBT region on the drift layer 12 and the drift layer 12 from the surface layer of the base layer 10.
  • the groove 13 formed in this way, the gate insulating film 8 formed along the side and bottom surfaces of the groove 13, the gate electrode 9 formed inside the gate insulating film 8 in the groove 13
  • An n-type source layer 7 formed with the groove 13 interposed therebetween, and an interlayer insulating film 6 (first interlayer insulating film) formed to cover the groove 13 and a part of the source layer 7 are provided.
  • the base layer 10 is also formed in the diode region on the drift layer 12, and a PiN diode having a PN junction between the drift layer 12 and the base layer 10 is formed in the diode region. ing.
  • the semiconductor device includes a wiring structure disposed on the second region (invalid region).
  • the surface electrode 2 is disposed so as to cover the wiring structure, and the wiring structure includes polysilicon 16 and an interlayer insulating film 17 (second interlayer insulating film) formed so as to cover the polysilicon 16.
  • a Schottky barrier diode having a Schottky junction between the drift layer 12A and the surface electrode 2 is formed in the diode region.
  • the element area can be reduced by forming the Schottky barrier diode at the location where the break reaches, while suppressing the breakage of the gate structure due to the break starting from the end of the bonding layer 40. It can be used effectively.
  • FIG. 4 is a cross-sectional view of a semiconductor device in which surface electrodes according to the present embodiment are soldered.
  • symbol is attached
  • a junction is formed above a region where a gate structure (including a base layer 10, a gate electrode 9, a gate insulating film 8, an n + type source layer 7 and an interlayer insulating film 6) is formed.
  • Layer 4B and its ends are disposed.
  • the end portion of the bonding layer 4B is formed so as to cover the insulating layer 5 (polyimide) formed on the surface electrode 2.
  • the bonding layer 4B is formed after the insulating layer 5 is formed.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment.
  • symbol is attached
  • a junction is formed above a region where a gate structure (including a base layer 10, a gate electrode 9, a gate insulating film 8, an n + type source layer 7 and an interlayer insulating film 6) is formed. Layer 4 and its ends are arranged.
  • a dissimilar metal layer 41 made of a metal different from the surface electrode 2 is formed between the bonding layer 4 and the surface electrode 2.
  • a layer made of a metal having a smaller linear expansion coefficient than aluminum or Ni, such as titanium or tungsten is assumed.
  • the adhesion between the surface electrode 2 and the dissimilar metal layer 41 is weakened.
  • the semiconductor device is formed by reaching the drift layer 12 from the n-type drift layer 12, the p-type base layer 10 formed on the drift layer 12, and the surface layer of the base layer 10. Groove 13, gate insulating film 8 formed along the side and bottom surfaces of groove 13, gate electrode 9 formed inside gate insulating film 8 in groove 13, and groove 13 in base layer 10 surface layer.
  • the n-type source layer 7, the trench 13, and the interlayer insulating film 6 formed so as to cover a part of the source layer 7, the base layer 10, and the interlayer insulating film 6 are disposed so as to be sandwiched therebetween.
  • the stress concentration at the end of the bonding layer 4B is prevented from being directly transmitted to the underlying surface electrode 2. be able to. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
  • the semiconductor device reaches the inside of the drift layer 12 from the n-type drift layer 12, the p-type base layer 10 formed on the drift layer 12, and the base layer 10 surface layer.

Abstract

The present invention provides a semiconductor device having a high tolerance in conditions accompanying heating or cooling when a surface electrode is joined by means of soldering. The present invention is provided with: a drift layer (12) having a first conductivity type; a gate structure formed at a first region on the drift layer (12); a surface electrode (2) disposed covering a second region on the drift layer (12) and the first region; a joining layer (40) formed locally on the surface electrode (2); a solder layer (3) formed on the joining layer (40); and a read frame (1) disposed on the solder layer (3). The joining layer (4) covers a region on the surface electrode (2) corresponding to the first region, and the end of the joining layer (40) is positioned at a region on the surface electrode (2) corresponding to the second region. A diode is formed in the second region.

Description

半導体装置Semiconductor device
　本発明は、表面電極とリードフレーム等の配線金属との接合に、はんだ接合を用いる半導体装置に関するものであり、特に、大電流を通電するパワーデバイスに関するものである。 The present invention relates to a semiconductor device using a solder joint for joining a surface electrode and a wiring metal such as a lead frame, and more particularly to a power device that conducts a large current.
　従来から、パワーチップの表面電極における接合には、主にワイヤーボンドが用いられてきた。しかし、後工程のタクトタイムの短縮、および、半導体素子の冷却効率向上を目的に、表面電極における接合にはんだ接合を用いる場合も増えてきている（特許文献１参照）。当該はんだ接合を用いて、表面電極にリードフレーム等を接合させることができる。表面電極における接合にはんだ接合を用いる場合、半導体素子の表面電極（例えばアルミ電極）上に、はんだとの接合をなすための金属層（Ｎｉ等）を成膜する必要がある。 Conventionally, wire bonds have been mainly used for bonding at the surface electrode of the power chip. However, in order to shorten the tact time of the post process and improve the cooling efficiency of the semiconductor element, there is an increasing number of cases where solder bonding is used for bonding at the surface electrode (see Patent Document 1). A lead frame or the like can be bonded to the surface electrode by using the solder bonding. When solder bonding is used for bonding at the surface electrode, it is necessary to form a metal layer (Ni or the like) for bonding with solder on the surface electrode (for example, aluminum electrode) of the semiconductor element.
特許第４０７８９９３号公報Japanese Patent No. 4078993
　上記のように表面電極をはんだ接合する場合、パワーサイクルまたは熱サイクル等の加熱または冷却の伴う条件下では、熱膨張率の違いから、表面電極に接合されたリードフレーム等の構造物から表面電極（アルミ電極）に対して機械的なストレス（応力）が発生する。当該ストレスは、特に金属層とはんだとの合金層である接合層端部に集中する。 When soldering the surface electrode as described above, under conditions involving heating or cooling such as power cycle or thermal cycle, the surface electrode from a structure such as a lead frame joined to the surface electrode due to a difference in thermal expansion coefficient. Mechanical stress (stress) is generated on the (aluminum electrode). The stress is concentrated particularly on the end portion of the bonding layer which is an alloy layer of a metal layer and solder.
　そのため、接合層端部の近傍に位置する表面電極が破断され、さらに、その下に形成されたゲート構造が破壊されるおそれがある。当該破断および破壊は、半導体素子が動作不能等となる要因となる。 Therefore, the surface electrode located in the vicinity of the end portion of the bonding layer may be broken, and the gate structure formed thereunder may be broken. The breakage and breakage cause the semiconductor element to become inoperable.
　この解決方法として、接合層をポリイミドで覆う方法が提案されている。しかし当該方法を用いる場合には、ポリイミド塗布前に接合層を形成しておかなければならない。ポリイミド塗布前に接合層が形成されると、接合層表面がポリイミド塗布時に汚染され、はんだを用いたダイボンドでのボイドの要因となる可能性がある。 As this solution, a method of covering the bonding layer with polyimide has been proposed. However, when this method is used, a bonding layer must be formed before applying polyimide. If the bonding layer is formed before polyimide application, the surface of the bonding layer may be contaminated during polyimide application, which may cause voids in die bonding using solder.
　本発明は、上記のような問題を解決するためになされたものであり、表面電極をはんだ接合する場合に、加熱または冷却の伴う条件下において高い耐量を有する半導体装置を提供することを目的とする。 The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having high resistance under conditions involving heating or cooling when soldering surface electrodes. To do.
　本発明の一態様に関する半導体装置は、第１導電型のドリフト層と、前記ドリフト層上のうちの部分領域である第１領域に形成された、ゲート構造と、前記第１領域および前記ドリフト層上のうちの他の領域である第２領域を覆って配置された、表面電極と、前記表面電極上に部分的に形成された接合層と、前記接合層上に形成されたはんだ層と、前記はんだ層上に配置されたリードフレームとを備え、前記接合層は前記第１領域に対応する前記表面電極上の領域を覆い、かつ、前記接合層の端部は前記第２領域に対応する前記表面電極上の領域に位置し、前記第２領域において、ダイオードが形成されていることを特徴とする。 A semiconductor device according to one embodiment of the present invention includes a first conductivity type drift layer, a gate structure formed in a first region which is a partial region on the drift layer, the first region, and the drift layer. A surface electrode, a bonding layer partially formed on the surface electrode, and a solder layer formed on the bonding layer; A lead frame disposed on the solder layer, the bonding layer covering a region on the surface electrode corresponding to the first region, and an end of the bonding layer corresponding to the second region A diode is formed in the region on the surface electrode and in the second region.
　本発明の別の態様に関する半導体装置は、第１導電型のドリフト層と、前記ドリフト層上のうちの部分領域である第１領域に形成された、ゲート構造と、前記第１領域および前記ドリフト層上のうちの他の領域である第２領域を覆って配置された、表面電極と、前記表面電極上に部分的に形成された接合層と、前記接合層上に形成されたはんだ層と、前記はんだ層上に配置されたリードフレームと、前記第２領域上に配置された配線構造とを備え、前記接合層は前記第１領域に対応する前記表面電極上の領域を覆い、かつ、前記接合層の端部は前記第２領域に対応する前記表面電極上の領域に位置し、前記表面電極は、前記配線構造を覆って配置され、前記配線構造は、ポリシリコンと、前記ポリシリコンを覆って形成された第２層間絶縁膜とを備えることを特徴とする。 A semiconductor device according to another aspect of the present invention includes a first conductivity type drift layer, a gate structure formed in a first region which is a partial region on the drift layer, the first region, and the drift A surface electrode, a bonding layer partially formed on the surface electrode, and a solder layer formed on the bonding layer, which are disposed to cover a second region, which is another region on the layer, A lead frame disposed on the solder layer and a wiring structure disposed on the second region, the bonding layer covering a region on the surface electrode corresponding to the first region; and An end portion of the bonding layer is located in a region on the surface electrode corresponding to the second region, the surface electrode is disposed so as to cover the wiring structure, and the wiring structure includes polysilicon and the polysilicon. Second interlayer insulation formed over Characterized in that it comprises and.
　本発明の別の態様に関する半導体装置は、第１導電型のドリフト層と、前記ドリフト層上に形成された、第２導電型のベース層と、前記ベース層表層から前記ドリフト層内に達して形成された溝と、前記溝の側面および底面に沿って形成されたゲート絶縁膜と、前記溝内の前記ゲート絶縁膜の内側に形成されたゲート電極と、前記ベース層表層において前記溝を挟んで形成された、第１導電型のソース層と、前記溝と、前記ソース層の一部とを覆って形成された、層間絶縁膜と、前記ベース層および前記層間絶縁膜を覆って配置された、表面電極と、前記表面電極上に部分的に形成された絶縁層と、前記絶縁層の端部を覆い、かつ、前記表面電極上の前記絶縁層が形成されていない領域を覆って形成された接合層と、前記接合層上に形成されたはんだ層と、前記はんだ層上に配置されたリードフレームとを備えることを特徴とする。　 A semiconductor device according to another aspect of the present invention includes a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and the base layer surface layer reaching the drift layer. The formed groove, the gate insulating film formed along the side surface and the bottom surface of the groove, the gate electrode formed inside the gate insulating film in the groove, and the base layer surface layer sandwiching the groove An interlayer insulating film formed covering the first conductivity type source layer, the trench, and a part of the source layer, and the base layer and the interlayer insulating film. Further, a surface electrode, an insulating layer partially formed on the surface electrode, an end portion of the insulating layer, and a region on the surface electrode where the insulating layer is not formed are formed. Formed on the bonding layer. And the solder layer, characterized in that it comprises a lead frame disposed on said solder layer. *
　本発明の別の態様に関する半導体装置は、第１導電型のドリフト層と、前記ドリフト層上に形成された、第２導電型のベース層と、前記ベース層表層から前記ドリフト層内に達して形成された溝と、前記溝の側面および底面に沿って形成されたゲート絶縁膜と、前記溝内の前記ゲート絶縁膜の内側に形成されたゲート電極と、前記ベース層表層において前記溝を挟んで形成された、第１導電型のソース層と、前記溝と、前記ソース層の一部とを覆って形成された、層間絶縁膜と、前記ベース層および前記層間絶縁膜を覆って配置された、表面電極と、前記表面電極上に部分的に形成された、表面電極とは異なる金属からなる異種金属層と、前記異種金属層上に形成され、当該異種金属層が介在することにより前記表面電極との密着性が弱められた接合層と、前記接合層上に形成されたはんだ層と、前記はんだ層上に配置されたリードフレームとを備えることを特徴とする。 A semiconductor device according to another aspect of the present invention includes a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and the base layer surface layer reaching the drift layer. The formed groove, the gate insulating film formed along the side surface and the bottom surface of the groove, the gate electrode formed inside the gate insulating film in the groove, and the base layer surface layer sandwiching the groove An interlayer insulating film formed covering the first conductivity type source layer, the trench, and a part of the source layer, and the base layer and the interlayer insulating film. Further, the surface electrode, the dissimilar metal layer made of a metal different from the surface electrode, partially formed on the surface electrode, and the dissimilar metal layer formed on the dissimilar metal layer, the interposition of the dissimilar metal layer Low adhesion to surface electrode A bonding layer, and a solder layer formed on the bonding layer, characterized in that it comprises a lead frame disposed on said solder layer.
　本発明の上記態様によれば、表面電極をはんだ接合する場合に、加熱または冷却の伴う条件下において高い耐量を実現することができる。 According to the above aspect of the present invention, when a surface electrode is soldered, a high tolerance can be realized under conditions involving heating or cooling.
　本発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.
実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。It is sectional drawing of the semiconductor device which soldered the surface electrode regarding embodiment. 実施形態の他の態様に関する半導体装置の断面図である。It is sectional drawing of the semiconductor device regarding the other aspect of embodiment. 実施形態の他の態様に関する半導体装置の断面図である。It is sectional drawing of the semiconductor device regarding the other aspect of embodiment. 実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。It is sectional drawing of the semiconductor device which soldered the surface electrode regarding embodiment. 実施形態の他の態様に関する半導体装置の断面図である。It is sectional drawing of the semiconductor device regarding the other aspect of embodiment. 前提技術に関する、表面電極をはんだ接合した半導体装置の斜め俯瞰図である。It is a diagonal top view of the semiconductor device which soldered the surface electrode regarding a base technology. 前提技術に関する、表面電極をはんだ接合した半導体装置の断面図である。It is sectional drawing of the semiconductor device which soldered the surface electrode regarding the base technology. 前提技術の他の態様に関する、表面電極をはんだ接合した半導体装置の断面図である。It is sectional drawing of the semiconductor device which soldered the surface electrode regarding the other aspect of a premise technique. 前提技術に関する半導体装置の上面図である。It is a top view of the semiconductor device regarding a base technology. 実施形態の他の態様に関する半導体装置の上面図である。It is a top view of the semiconductor device regarding the other aspect of embodiment.
　以下、添付の図面を参照しながら実施形態について説明する。　 Hereinafter, embodiments will be described with reference to the accompanying drawings. *
　なお、本実施形態において、上面、側面または底面等の用語が用いられるが、これらの用語は、各面を便宜上区別するために用いられているものであり、実際の上下左右の方向とは関係しない。 In the present embodiment, terms such as the top surface, the side surface, or the bottom surface are used. These terms are used to distinguish each surface for convenience, and are related to the actual vertical and horizontal directions. do not do.
　図６は、前提技術に関する、表面電極をはんだ接合した（モールド封止前の）半導体装置の斜め俯瞰図である。また図７は、表面電極をはんだ接合した（モールド封止前の）当該半導体装置の断面図である。 FIG. 6 is a perspective view of a semiconductor device with a surface electrode soldered (before mold sealing) related to the base technology. FIG. 7 is a cross-sectional view of the semiconductor device (before mold sealing) with the surface electrodes soldered.
　図６に示される半導体装置においては、半導体素子上面に表面電極２（例えばアルミ電極）が配置され、表面電極２が配置された以外の半導体素子上の領域には、絶縁層５（例えばポリイミド層）が形成されている。表面電極２とリードフレーム１とがはんだ層３を介して接合されている。 In the semiconductor device shown in FIG. 6, the surface electrode 2 (for example, an aluminum electrode) is disposed on the upper surface of the semiconductor element, and the insulating layer 5 (for example, a polyimide layer) is disposed in the region on the semiconductor element other than the surface electrode 2 is disposed. ) Is formed. The surface electrode 2 and the lead frame 1 are joined via the solder layer 3.
　また、当該半導体装置の断面図（図７）によれば、はんだ層３と表面電極２との間に、Ｎｉ等とはんだとの合金である接合層４が形成されている。表面電極２の下方には半導体素子が形成されている。本実施形態において示される半導体素子はＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）であるが、半導体素子として適用されうるものはこれに限られない。 Further, according to the cross-sectional view of the semiconductor device (FIG. 7), a bonding layer 4 that is an alloy of Ni or the like and solder is formed between the solder layer 3 and the surface electrode 2. A semiconductor element is formed below the surface electrode 2. The semiconductor element shown in this embodiment is an IGBT (Insulated Gate Bipolar Transistor), but the semiconductor element that can be applied as a semiconductor element is not limited to this.
　当該半導体素子（ＩＧＢＴ）は、コレクタ電極１５と、コレクタ電極１５上に形成されたｐ型のコレクタ層１４と、コレクタ層１４上に形成されたｎ－型のドリフト層１２と、ｎ＋層１１と、ｐ型のベース層１０と、ゲート電極９と、ゲート絶縁膜８と、ｎ＋型のソース層７と、層間絶縁膜６とを備える。なお、ｎ＋層１１は備えられなくともよい。 The semiconductor element (IGBT) includes a collector electrode 15, a p-type collector layer 14 formed on the collector electrode 15, an n− type drift layer 12 formed on the collector layer 14, and an n + layer 11. , A p-type base layer 10, a gate electrode 9, a gate insulating film 8, an n + -type source layer 7, and an interlayer insulating film 6. The n + layer 11 may not be provided.
　ｎ＋層１１は、ドリフト層１２上に形成されている。そしてベース層１０は、ｎ＋層１１上に形成されている。 The n + layer 11 is formed on the drift layer 12. The base layer 10 is formed on the n + layer 11.
　ベース層１０表層からドリフト層１２内に達する溝１３が形成され、当該溝１３の側面および底面に沿って、ゲート絶縁膜８が形成されている。そして、溝１３内のゲート絶縁膜８の内側に、ゲート電極９が形成されている。 A groove 13 reaching the drift layer 12 from the surface layer of the base layer 10 is formed, and a gate insulating film 8 is formed along the side surface and the bottom surface of the groove 13. A gate electrode 9 is formed inside the gate insulating film 8 in the trench 13.
　また、ベース層表層において、ソース層７が溝１３を挟んで形成されている。そして、層間絶縁膜６が、溝１３とソース層７の一部とを覆って形成されている。 Further, the source layer 7 is formed with the groove 13 in between on the surface of the base layer. An interlayer insulating film 6 is formed so as to cover the trench 13 and a part of the source layer 7.
　上述のように、接合層４の下方領域には、表面電極２および半導体素子のゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が配置されている。 As described above, the region below the bonding layer 4 includes the surface electrode 2 and the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6. ) Is arranged.
　加熱または冷却を伴う条件下では、リードフレーム１と表面電極２との間の熱膨張率の違いによって表面電極２に対して機械的なストレスが発生し、表面電極２の破断、さらには、表面電極２の下方領域に配置されたゲート構造の破壊が生じるおそれがある。 Under conditions involving heating or cooling, mechanical stress is generated on the surface electrode 2 due to the difference in thermal expansion coefficient between the lead frame 1 and the surface electrode 2, and the surface electrode 2 is ruptured. There is a possibility that the gate structure arranged in the lower region of the electrode 2 is destroyed.
　この解決方法として、図８に示されるような、接合層４Ａを絶縁層５Ａ（例えばポリイミド層）で覆う方法が提案されている。しかし当該方法を用いる場合には、絶縁層５Ａを塗布する前に接合層４Ａを形成しておかなければならないという問題があった。 As this solution, a method of covering the bonding layer 4A with an insulating layer 5A (for example, a polyimide layer) as shown in FIG. 8 has been proposed. However, when this method is used, there is a problem that the bonding layer 4A must be formed before the insulating layer 5A is applied.
　以下に説明する実施形態は、上記のような問題を解決する半導体装置に関するものである。 The embodiment described below relates to a semiconductor device that solves the above problems.
　＜第１実施形態＞
　＜構成＞
　図１は、本実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。なお、図７と同一の構成要素には同一の符号を付し、適宜説明を省略する。 <First Embodiment>
<Configuration>
FIG. 1 is a cross-sectional view of a semiconductor device in which surface electrodes according to the present embodiment are soldered. In addition, the same code | symbol is attached | subjected to the component same as FIG. 7, and description is abbreviate | omitted suitably.
　図１に示された（表面電極２に覆われている）ドリフト層１２上の領域のうち、半導体素子のゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が形成された領域をＩＧＢＴ領域、ゲート構造が形成されていない領域をダイオード領域とする。 Among the regions on the drift layer 12 (covered by the surface electrode 2) shown in FIG. 1, the gate structure of the semiconductor element (base layer 10, gate electrode 9, gate insulating film 8, n + type source layer 7). In addition, a region where the insulating layer 6 is formed) is an IGBT region, and a region where no gate structure is formed is a diode region.
　ダイオード領域においては、ドリフト層１２およびベース層１０が形成され、コレクタ層１４は形成されない。ダイオード領域においては、ドリフト層１２とベース層１０との間のＰＮ接合によってＰｉＮダイオードが形成されている。 In the diode region, the drift layer 12 and the base layer 10 are formed, and the collector layer 14 is not formed. In the diode region, a PiN diode is formed by a PN junction between the drift layer 12 and the base layer 10.
　図１に示された半導体装置は、ＩＧＢＴ領域およびダイオード領域を備える逆導通型ＩＧＢＴ（ＲＣ－ＩＧＢＴ：Ｒｅｖｅｒｓｅ　Ｃｏｎｄｕｃｔｉｎｇ－ＩＧＢＴ）である。 The semiconductor device shown in FIG. 1 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting-IGBT) including an IGBT region and a diode region.
　図１に示されるように、ＩＧＢＴ領域上方には接合層４０が配置され、ダイオード領域上方には、接合層４０の端部が位置している。このように構成されることにより、接合層４０端部を起点に表面電極２に破断した場合でも、ゲート構造の破壊によるＩＧＢＴ素子の動作不能が発生しない。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 As shown in FIG. 1, the junction layer 40 is arranged above the IGBT region, and the end of the junction layer 40 is located above the diode region. With such a configuration, even when the surface electrode 2 is broken from the end of the bonding layer 40 as a starting point, the IGBT element is not disabled due to the breakdown of the gate structure. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　また、ＩＧＢＴ領域以外の領域はダイオード領域として活用することができる。よって、素子面積を有効に活用できるため、経済的な逆導通型ＩＧＢＴを実現することができる。 Also, the area other than the IGBT area can be used as a diode area. Therefore, since the element area can be effectively used, an economical reverse conduction type IGBT can be realized.
　なお図１においては、ＩＧＢＴ領域とダイオード領域とは連続しておらず、所定の間隔を空けて形成されているが、当該間隔が存在せず、ＩＧＢＴ領域とダイオード領域とが連続して形成されていてもよい。また図１においては、当該間隔におけるベース層１０の厚さが、ＩＧＢＴ領域におけるベース層１０の厚さおよびダイオード領域におけるベース層１０の厚さよりも厚く形成されている。しかし、当該間隔におけるベース層１０の厚さは、ＩＧＢＴ領域におけるベース層１０の厚さおよびダイオード領域におけるベース層１０の厚さと同様の厚さで形成されていてもよい。 In FIG. 1, the IGBT region and the diode region are not continuous and formed with a predetermined interval, but the interval does not exist and the IGBT region and the diode region are formed continuously. It may be. In FIG. 1, the thickness of the base layer 10 in the interval is formed larger than the thickness of the base layer 10 in the IGBT region and the thickness of the base layer 10 in the diode region. However, the thickness of the base layer 10 in the interval may be formed with the same thickness as the thickness of the base layer 10 in the IGBT region and the thickness of the base layer 10 in the diode region.
　＜変形例１＞
　図２は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図７と同一の構成要素には同一の符号を付し、適宜説明を省略する。 <Modification 1>
FIG. 2 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. 7, and description is abbreviate | omitted suitably.
　図２に示されたドリフト層上の領域のうち、半導体素子のゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が形成された領域をＩＧＢＴ領域、ゲート構造が形成されていない領域をダイオード領域とする。 In the region on the drift layer shown in FIG. 2, the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6) is formed. The region is referred to as an IGBT region, and the region where no gate structure is formed is referred to as a diode region.
　ダイオード領域においては、ドリフト層１２Ａが形成され、ベース層１０およびコレクタ層１４は形成されない。ダイオード領域においては、ドリフト層１２Ａと表面電極２との間のショットキー接合によってショットキーバリアダイオード（ＳＢＤ：Ｓｃｈｏｔｔｋｙ　Ｂａｒｒｉｅｒ　Ｄｉｏｄｅ）が形成されている。 In the diode region, the drift layer 12A is formed, and the base layer 10 and the collector layer 14 are not formed. In the diode region, a Schottky barrier diode (SBD) is formed by a Schottky junction between the drift layer 12 </ b> A and the surface electrode 2.
　図２に示されるように、ＩＧＢＴ領域上方には接合層４０が配置され、ダイオード領域上方には、接合層４０の端部が位置している。このように構成されることにより、接合層４０端部を起点に表面電極２に破断した場合でも、ゲート構造の破壊によるＩＧＢＴ素子の動作不能が発生しない。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 As shown in FIG. 2, the junction layer 40 is disposed above the IGBT region, and the end portion of the junction layer 40 is located above the diode region. With such a configuration, even when the surface electrode 2 is broken from the end of the bonding layer 40 as a starting point, the IGBT element is not disabled due to the breakdown of the gate structure. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　また、ＩＧＢＴ領域以外の領域はダイオード領域として活用することができる。よって、素子面積を有効に活用できるため、経済的な逆導通型ＩＧＢＴを実現することができる。 Also, the area other than the IGBT area can be used as a diode area. Therefore, since the element area can be effectively used, an economical reverse conduction type IGBT can be realized.
　＜変形例２＞
　図３は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図７と同一の構成要素には同一の符号を付し、適宜説明を省略する。 <Modification 2>
FIG. 3 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. 7, and description is abbreviate | omitted suitably.
　図３に示されたドリフト層１２上の領域のうち、半導体素子のゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が形成された領域をＩＧＢＴ領域、ゲート構造が形成されていない領域を無効領域とする。 In the region on the drift layer 12 shown in FIG. 3, the gate structure of the semiconductor element (including the base layer 10, the gate electrode 9, the gate insulating film 8, the n + type source layer 7 and the interlayer insulating film 6) is formed. The formed region is referred to as an IGBT region, and the region where no gate structure is formed is referred to as an invalid region.
　無効領域においては、ドリフト層１２、ベース層１０およびコレクタ層１４が形成されているが、コレクタ層１４は形成されていなくてもよい。また無効領域上には、ポリシリコン１６と、ポリシリコン１６を覆って形成された層間絶縁膜１７とを備える配線構造が配置されている。無効領域にＰｉＮダイオードが形成されていれば、それを温度センスダイオードとして活用することができ、また、配線構造は、当該温度センスダイオードとパッド間を結線するために用いることができる。 In the invalid region, the drift layer 12, the base layer 10, and the collector layer 14 are formed, but the collector layer 14 may not be formed. A wiring structure including polysilicon 16 and an interlayer insulating film 17 formed so as to cover the polysilicon 16 is disposed on the invalid region. If a PiN diode is formed in the invalid region, it can be used as a temperature sensing diode, and the wiring structure can be used to connect between the temperature sensing diode and the pad.
　図３に示されるように、ＩＧＢＴ領域上方には接合層４０が配置され、無効領域上方には、接合層４０の端部が位置している。このように構成されることにより、接合層４０端部を起点に表面電極２に破断した場合でも、ゲート構造の破壊によるＩＧＢＴ素子の動作不能が発生しない。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 As shown in FIG. 3, the bonding layer 40 is disposed above the IGBT region, and the end of the bonding layer 40 is positioned above the invalid region. With such a configuration, even when the surface electrode 2 is broken from the end of the bonding layer 40 as a starting point, the IGBT element is not disabled due to the breakdown of the gate structure. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　また、接合層４０端部を起点に表面電極２に破断が発生した場合に、下方に配置されたポリシリコン１６が破断し、温度センスダイオード特性の異常として検知することが可能となる。よって、パワーサイクルまたは熱サイクル等による半導体素子の劣化を検知することが可能となる。　 Further, when the surface electrode 2 breaks starting from the end of the bonding layer 40, the polysilicon 16 disposed below breaks and can be detected as an abnormality in temperature sensing diode characteristics. Therefore, it is possible to detect deterioration of the semiconductor element due to power cycle or thermal cycle. *
　図９は、前提技術に関する半導体装置の上面図である。前提技術に関する半導体装置では、温度センスダイオード１８およびパッド１９が図示されるように配置されている場合に、配線構造内のポリシリコン１６ａが図示されるように形成されている。 FIG. 9 is a top view of the semiconductor device related to the base technology. In the semiconductor device related to the base technology, when the temperature sensing diode 18 and the pad 19 are disposed as illustrated, the polysilicon 16a in the wiring structure is formed as illustrated.
　一方で図１０は、本実施形態の他の態様に関する半導体装置の上面図である。本実施形態に関する半導体装置では、温度センスダイオード１８およびパッド１９が図示されるように配置されている場合に、配線構造内のポリシリコン１６が、接合層４０が形成された領域の端部を沿うように形成されている。より正確には、接合層４０端部の下方に位置するように、ポリシリコン１６が形成されている。なお、配線構造の配線態様は図１０に示されるものに限られず、接合層４０が形成された領域の端部に沿う部分の割合が少なくてもよい。 On the other hand, FIG. 10 is a top view of the semiconductor device according to another aspect of the present embodiment. In the semiconductor device according to the present embodiment, when the temperature sense diode 18 and the pad 19 are arranged as illustrated, the polysilicon 16 in the wiring structure extends along the end of the region where the bonding layer 40 is formed. It is formed as follows. More precisely, the polysilicon 16 is formed so as to be located below the end of the bonding layer 40. In addition, the wiring aspect of a wiring structure is not restricted to what is shown by FIG. 10, The ratio of the part along the edge part of the area | region in which the joining layer 40 was formed may be small.
　＜効果＞
　本実施形態によれば、半導体装置が、第１導電型（ｎ型）のドリフト層１２と、ドリフト層１２上のうちの部分領域である第１領域（ＩＧＢＴ領域）に形成された、ゲート構造と、ＩＧＢＴ領域およびドリフト層１２上のうちの他の領域である第２領域（ダイオード領域）を覆って配置された、表面電極２と、表面電極２上に部分的に形成された接合層４０と、接合層４０上に形成されたはんだ層３と、はんだ層３上に配置されたリードフレーム１とを備える。 <Effect>
According to the present embodiment, the semiconductor device is formed in the first conductivity type (n-type) drift layer 12 and the first region (IGBT region) which is a partial region on the drift layer 12. A surface electrode 2 disposed so as to cover the second region (diode region), which is the other region on the IGBT region and the drift layer 12, and a bonding layer 40 partially formed on the surface electrode 2. And a solder layer 3 formed on the bonding layer 40 and a lead frame 1 disposed on the solder layer 3.
　接合層４０は、ＩＧＢＴ領域に対応する表面電極２上の領域を覆い、かつ、接合層４０の端部はダイオード領域に対応する表面電極２上の領域に位置する。そして、ダイオード領域において、ダイオードが形成されている。 The bonding layer 40 covers a region on the surface electrode 2 corresponding to the IGBT region, and an end portion of the bonding layer 40 is located in a region on the surface electrode 2 corresponding to the diode region. A diode is formed in the diode region.
　このような構成によれば、接合層４０端部を起点に表面電極２に破断が発生した場合でも、破断が到達する箇所（接合層４０に対応する領域）はダイオード領域であるため、ゲート構造が破壊されることが抑制される。よって、加熱または冷却の伴う条件下（パワーサイクルまたは熱サイクル等）において高い耐量を実現することができる。また、破断が到達する箇所にもダイオード領域が形成されているため、素子面積を有効に活用できる。 According to such a configuration, even when a break occurs in the surface electrode 2 starting from the end of the bonding layer 40, the portion where the break reaches (the region corresponding to the bonding layer 40) is the diode region. Is suppressed from being destroyed. Therefore, a high tolerance can be realized under conditions involving heating or cooling (power cycle or thermal cycle). In addition, since the diode region is formed at the location where the breakage reaches, the element area can be effectively utilized.
　また、本実施形態によれば、ゲート構造が、ドリフト層１２上のＩＧＢＴ領域に形成された、第２導電型（ｐ型）のベース層１０と、ベース層１０表層からドリフト層１２内に達して形成された溝１３と、溝１３の側面および底面に沿って形成されたゲート絶縁膜８と、溝１３内のゲート絶縁膜８の内側に形成されたゲート電極９と、ベース層１０表層において溝１３を挟んで形成された、ｎ型のソース層７と、溝１３と、ソース層７の一部とを覆って形成された、層間絶縁膜６（第１層間絶縁膜）とを備える。 In addition, according to the present embodiment, the gate structure reaches the base layer 10 of the second conductivity type (p-type) formed in the IGBT region on the drift layer 12 and the drift layer 12 from the surface layer of the base layer 10. In the surface layer of the base layer 10, the groove 13 formed in this way, the gate insulating film 8 formed along the side and bottom surfaces of the groove 13, the gate electrode 9 formed inside the gate insulating film 8 in the groove 13 An n-type source layer 7 formed with the groove 13 interposed therebetween, and an interlayer insulating film 6 (first interlayer insulating film) formed to cover the groove 13 and a part of the source layer 7 are provided.
　また、本実施形態によれば、ベース層１０は、ドリフト層１２上のダイオード領域においても形成され、ダイオード領域において、ドリフト層１２とベース層１０との間のＰＮ接合を有するＰｉＮダイオードが形成されている。 According to the present embodiment, the base layer 10 is also formed in the diode region on the drift layer 12, and a PiN diode having a PN junction between the drift layer 12 and the base layer 10 is formed in the diode region. ing.
　このような構成によれば、接合層４０端部を起点とする破断によってゲート構造が破壊されることを抑制しつつ、破断が到達する箇所にＰｉＮダイオードを形成することで、素子面積を有効に活用することができる。 According to such a configuration, it is possible to effectively reduce the element area by forming the PiN diode at the position where the break reaches while suppressing the breakage of the gate structure due to the break starting from the end of the bonding layer 40. Can be used.
　また、本実施形態によれば、半導体装置が、第２領域（無効領域）上に配置された配線構造を備える。 In addition, according to the present embodiment, the semiconductor device includes a wiring structure disposed on the second region (invalid region).
　表面電極２は、配線構造を覆って配置され、配線構造は、ポリシリコン１６と、ポリシリコン１６を覆って形成された層間絶縁膜１７（第２層間絶縁膜）とを備える。 The surface electrode 2 is disposed so as to cover the wiring structure, and the wiring structure includes polysilicon 16 and an interlayer insulating film 17 (second interlayer insulating film) formed so as to cover the polysilicon 16.
　このような構成によれば、接合層４０端部を起点に表面電極２に破断が発生した場合に下地のポリシリコン１６が破断し、温度センスダイオード特性の異常として検知することが可能となる。よって、加熱または冷却の伴う条件変化（パワーサイクルまたは熱サイクル等）による素子の劣化を検知することが可能となる。 According to such a configuration, when the surface electrode 2 is ruptured starting from the end of the bonding layer 40, the underlying polysilicon 16 is ruptured and can be detected as an abnormality in temperature sensing diode characteristics. Therefore, it is possible to detect the deterioration of the element due to a condition change (power cycle or thermal cycle) accompanying heating or cooling.
　また、本実施形態によれば、ダイオード領域において、ドリフト層１２Ａと表面電極２との間のショットキー接合を有するショットキーバリアダイオードが形成されている。 Further, according to the present embodiment, a Schottky barrier diode having a Schottky junction between the drift layer 12A and the surface electrode 2 is formed in the diode region.
　このような構成によれば、接合層４０端部を起点とする破断によってゲート構造が破壊されることを抑制しつつ、破断が到達する箇所にショットキーバリアダイオードを形成することで、素子面積を有効に活用することができる。 According to such a configuration, the element area can be reduced by forming the Schottky barrier diode at the location where the break reaches, while suppressing the breakage of the gate structure due to the break starting from the end of the bonding layer 40. It can be used effectively.
　＜第２実施形態＞
　＜構成＞
　図４は、本実施形態に関する表面電極をはんだ接合した半導体装置の断面図である。なお、図７と同一の構成要素には同一の符号を付し、適宜説明を省略する。 Second Embodiment
<Configuration>
FIG. 4 is a cross-sectional view of a semiconductor device in which surface electrodes according to the present embodiment are soldered. In addition, the same code | symbol is attached | subjected to the component same as FIG. 7, and description is abbreviate | omitted suitably.
　図４に示された半導体装置においては、ゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が形成された領域上方に、接合層４Ｂおよびその端部が配置されている。 In the semiconductor device shown in FIG. 4, a junction is formed above a region where a gate structure (including a base layer 10, a gate electrode 9, a gate insulating film 8, an n + type source layer 7 and an interlayer insulating film 6) is formed. Layer 4B and its ends are disposed.
　ただし、接合層４Ｂの端部は、表面電極２上に形成された絶縁層５（ポリイミド）を覆って形成されている。接合層４Ｂは、絶縁層５を形成した後に形成される。 However, the end portion of the bonding layer 4B is formed so as to cover the insulating layer 5 (polyimide) formed on the surface electrode 2. The bonding layer 4B is formed after the insulating layer 5 is formed.
　このように構成されることにより、接合層４Ｂ端部への応力集中が、当該端部下方に配置された表面電極２に直接伝わることを防ぎ、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 By being configured in this way, stress concentration at the end of the bonding layer 4B is prevented from being directly transmitted to the surface electrode 2 disposed below the end, and high resistance to power cycle or thermal cycle is realized. can do.
　＜変形例＞
　図５は、本実施形態の他の態様に関する半導体装置の断面図である。なお、図７と同一の構成要素には同一の符号を付し、適宜説明を省略する。 <Modification>
FIG. 5 is a cross-sectional view of a semiconductor device according to another aspect of the present embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. 7, and description is abbreviate | omitted suitably.
　図５に示された半導体装置においては、ゲート構造（ベース層１０、ゲート電極９、ゲート絶縁膜８、ｎ＋型のソース層７および層間絶縁膜６を含む）が形成された領域上方に、接合層４およびその端部が配置されている。 In the semiconductor device shown in FIG. 5, a junction is formed above a region where a gate structure (including a base layer 10, a gate electrode 9, a gate insulating film 8, an n + type source layer 7 and an interlayer insulating film 6) is formed. Layer 4 and its ends are arranged.
　ただし、接合層４と表面電極２との間には、表面電極２とは異なる金属からなる異種金属層４１が形成されている。異種金属層４１としては、チタンまたはタングステン等の、アルミニウムまたはＮｉ等に比べて線膨張率が小さい金属からなる層が想定される。異種金属層４１が形成されることにより、表面電極２と異種金属層４１との間の密着性が弱まる。 However, a dissimilar metal layer 41 made of a metal different from the surface electrode 2 is formed between the bonding layer 4 and the surface electrode 2. As the dissimilar metal layer 41, a layer made of a metal having a smaller linear expansion coefficient than aluminum or Ni, such as titanium or tungsten, is assumed. By forming the dissimilar metal layer 41, the adhesion between the surface electrode 2 and the dissimilar metal layer 41 is weakened.
　このように構成されることにより、接合層４端部を起点に表面電極２に破断した場合でも、表面電極２と異種金属層４１との間で剥離が生じ、ゲート構造の破壊が生じることを抑制できる。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 By being configured in this way, even when the surface electrode 2 is broken starting from the end of the bonding layer 4, peeling occurs between the surface electrode 2 and the dissimilar metal layer 41, and the gate structure is broken. Can be suppressed. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　＜効果＞
　本実施形態によれば、半導体装置が、ｎ型のドリフト層１２と、ドリフト層１２上に形成された、ｐ型のベース層１０と、ベース層１０表層からドリフト層１２内に達して形成された溝１３と、溝１３の側面および底面に沿って形成されたゲート絶縁膜８と、溝１３内のゲート絶縁膜８の内側に形成されたゲート電極９と、ベース層１０表層において溝１３を挟んで形成された、ｎ型のソース層７と、溝１３と、ソース層７の一部とを覆って形成された、層間絶縁膜６と、ベース層１０および層間絶縁膜６を覆って配置された、表面電極２と、表面電極２上に部分的に形成された絶縁層５と、絶縁層５の端部を覆い、かつ、表面電極２上の絶縁層５が形成されていない領域を覆って形成された接合層４Ｂと、接合層４Ｂ上に形成されたはんだ層３と、はんだ層３上に配置されたリードフレーム１とを備える。 <Effect>
According to this embodiment, the semiconductor device is formed by reaching the drift layer 12 from the n-type drift layer 12, the p-type base layer 10 formed on the drift layer 12, and the surface layer of the base layer 10. Groove 13, gate insulating film 8 formed along the side and bottom surfaces of groove 13, gate electrode 9 formed inside gate insulating film 8 in groove 13, and groove 13 in base layer 10 surface layer. The n-type source layer 7, the trench 13, and the interlayer insulating film 6 formed so as to cover a part of the source layer 7, the base layer 10, and the interlayer insulating film 6 are disposed so as to be sandwiched therebetween. The surface electrode 2, the insulating layer 5 partially formed on the surface electrode 2, and the region that covers the end of the insulating layer 5 and is not formed with the insulating layer 5 on the surface electrode 2 Bonding layer 4B formed to cover and solder formed on bonding layer 4B Comprising a 3, a lead frame 1 placed on the solder layer 3.
　このような構成によれば、絶縁層５成膜後に接合層４Ｂを成膜するようなプロセスフローであっても、接合層４Ｂ端部の応力集中が下地の表面電極２に直接伝わることを防ぐことができる。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 According to such a configuration, even in a process flow in which the bonding layer 4B is formed after the insulating layer 5 is formed, the stress concentration at the end of the bonding layer 4B is prevented from being directly transmitted to the underlying surface electrode 2. be able to. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　また、本実施形態によれば、半導体装置が、ｎ型のドリフト層１２と、ドリフト層１２上に形成された、ｐ型のベース層１０と、ベース層１０表層からドリフト層１２内に達して形成された溝１３と、溝１３の側面および底面に沿って形成されたゲート絶縁膜８と、溝１３内のゲート絶縁膜８の内側に形成されたゲート電極９と、ベース層１０表層において溝１３を挟んで形成された、ｎ型のソース層７と、溝１３と、ソース層７の一部とを覆って形成された、層間絶縁膜６と、ベース層１０および層間絶縁膜６を覆って配置された、表面電極２と、表面電極２上に部分的に形成された、表面電極２とは異なる金属からなる異種金属層４１と、異種金属層４１上に形成され、当該異種金属層４１が介在することにより表面電極２との密着性が弱められた接合層４と、接合層４上に形成されたはんだ層３と、はんだ層３上に配置されたリードフレーム１とを備える。　 Further, according to the present embodiment, the semiconductor device reaches the inside of the drift layer 12 from the n-type drift layer 12, the p-type base layer 10 formed on the drift layer 12, and the base layer 10 surface layer. The formed groove 13, the gate insulating film 8 formed along the side and bottom surfaces of the groove 13, the gate electrode 9 formed inside the gate insulating film 8 in the groove 13, and the groove in the surface layer of the base layer 10 13 covering the n-type source layer 7, the trench 13, and part of the source layer 7, and covering the base layer 10 and the interlayer insulating film 6. The dissimilar metal layer 41 formed on the dissimilar metal layer 41 and the dissimilar metal layer 41 made of a metal different from the surface electrode 2 partially formed on the surface electrode 2 and the dissimilar metal layer 41 Adhesion with the surface electrode 2 by interposing 41 It comprises a bonding layer 4 which is weakened, the solder layer 3 formed on the bonding layer 4, and the lead frame 1 placed on the solder layer 3. *
　このような構成によれば、接合層４端部を起点に表面電極２に破断が発生した場合でも、１層目の表面電極２と２層目の異種金属層４１との間で剥離が生じ、異種金属層４１の下にあるゲート構造の破壊までに至らない。よって、パワーサイクルまたは熱サイクル等に対し高い耐量を実現することができる。 According to such a configuration, even when the surface electrode 2 breaks from the end of the bonding layer 4, peeling occurs between the first surface electrode 2 and the second dissimilar metal layer 41. However, the gate structure under the dissimilar metal layer 41 is not destroyed. Therefore, it is possible to realize a high tolerance against power cycle or thermal cycle.
　上記実施形態では、各構成要素の材質、材料、実施の条件等についても記載しているが、これらは例示であって記載したものに限られるものではない。　 In the above-described embodiment, the material, material, conditions for implementation, etc. of each component are also described, but these are examples and are not limited to those described. *
　なお本発明は、その発明の範囲内において、各実施形態の自由な組み合わせ、あるいは各実施形態の任意の構成要素の変形、もしくは各実施形態において任意の構成要素の省略が可能である。　 In the present invention, within the scope of the invention, any combination of each embodiment, any modification of any component in each embodiment, or any component in each embodiment can be omitted. *
　本発明は詳細に説明されたが、上記した説明は、すべての局面において例示であって、本発明がそれに限定されるものではない。例示されていない無数の変形例が、本発明の範囲から外れずに想定され得るものと解される。 Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.
　１　リードフレーム、２　表面電極、３　はんだ層、４，４Ａ，４Ｂ，４０　接合層、５，５Ａ　絶縁層、６，１７　層間絶縁膜、７　ソース層、８　ゲート絶縁膜、９　ゲート電極、１０　ベース層、１１　ｎ＋層、１２，１２Ａ　ドリフト層、１３　溝、１４　コレクタ層、１５　コレクタ電極、１６，１６ａ　ポリシリコン、１８　温度センスダイオード、１９　パッド、４１　異種金属層。 1 lead frame, 2 surface electrode, 3 solder layer, 4, 4A, 4B, 40 bonding layer, 5, 5A insulating layer, 6, 17 interlayer insulating film, 7 source layer, 8 gate insulating film, 9 gate electrode, 10 base Layer, 11 n + layer, 12, 12A drift layer, 13 groove, 14 collector layer, 15 collector electrode, 16, 16a polysilicon, 18 temperature sense diode, 19 pad, 41 dissimilar metal layer.

Claims (8)

  1. 第１導電型のドリフト層（１２、１２Ａ）と、
    　前記ドリフト層（１２、１２Ａ）上のうちの部分領域である第１領域に形成された、ゲート構造と、
    　前記第１領域および前記ドリフト層（１２、１２Ａ）上のうちの他の領域である第２領域を覆って配置された、表面電極（２）と、
    　前記表面電極（２）上に部分的に形成された接合層（４０）と、
    　前記接合層（４０）上に形成されたはんだ層（３）と、
    　前記はんだ層（３）上に配置されたリードフレーム（１）とを備え、
    　前記接合層（４０）は前記第１領域に対応する前記表面電極（２）上の領域を覆い、かつ、前記接合層（４０）の端部は前記第２領域に対応する前記表面電極（２）上の領域に位置し、
    　前記第２領域において、ダイオードが形成されていることを特徴とする、
    半導体装置。     A first conductivity type drift layer (12, 12A);
    A gate structure formed in a first region which is a partial region on the drift layer (12, 12A);
    A surface electrode (2) disposed over the first region and a second region which is another region on the drift layer (12, 12A);
    A bonding layer (40) partially formed on the surface electrode (2);
    A solder layer (3) formed on the bonding layer (40);
    A lead frame (1) disposed on the solder layer (3);
    The bonding layer (40) covers a region on the surface electrode (2) corresponding to the first region, and an end portion of the bonding layer (40) is the surface electrode (2 corresponding to the second region). ) Located in the upper area,
    A diode is formed in the second region,
    Semiconductor device.
  2. 前記ゲート構造が、
    　前記ドリフト層（１２）上の前記第１領域に形成された、第２導電型のベース層（１０）と、
    　前記ベース層（１０）表層から前記ドリフト層（１２）内に達して形成された溝（１３）と、
    　前記溝（１３）の側面および底面に沿って形成されたゲート絶縁膜（８）と、
    　前記溝（１３）内の前記ゲート絶縁膜（８）の内側に形成されたゲート電極（９）と、
    　前記ベース層（１０）表層において前記溝（１３）を挟んで形成された、第１導電型のソース層（７）と、
    　前記溝（１３）と、前記ソース層（７）の一部とを覆って形成された、第１層間絶縁膜（６）とを備えることを特徴とする、
    請求項１に記載の半導体装置。     The gate structure is
    A second conductivity type base layer (10) formed in the first region on the drift layer (12);
    A groove (13) formed from the surface layer of the base layer (10) to the drift layer (12);
    A gate insulating film (8) formed along the side and bottom surfaces of the trench (13);
    A gate electrode (9) formed inside the gate insulating film (8) in the trench (13);
    A first conductivity type source layer (7) formed on the surface of the base layer (10) with the groove (13) interposed therebetween;
    A first interlayer insulating film (6) formed to cover the trench (13) and a part of the source layer (7),
    The semiconductor device according to claim 1.
  3. 　前記ベース層（１０）は、前記ドリフト層（１２）上の前記第２領域においても形成され、
    　前記第２領域において、前記ドリフト層（１２）と前記ベース層（１０）との間のＰＮ接合を有するＰｉＮダイオードが形成されていることを特徴とする、
    請求項２に記載の半導体装置。     The base layer (10) is also formed in the second region on the drift layer (12),
    In the second region, a PiN diode having a PN junction between the drift layer (12) and the base layer (10) is formed.
    The semiconductor device according to claim 2.
  4. 　前記第２領域において、前記ドリフト層（１２Ａ）と前記表面電極（２）との間のショットキー接合を有するショットキーバリアダイオードが形成されていることを特徴とする、
    請求項１または２に記載の半導体装置。     In the second region, a Schottky barrier diode having a Schottky junction between the drift layer (12A) and the surface electrode (2) is formed.
    The semiconductor device according to claim 1.
  5. 　第１導電型のドリフト層（１２、１２Ａ）と、
    　前記ドリフト層（１２、１２Ａ）上のうちの部分領域である第１領域に形成された、ゲート構造と、
    　前記第１領域および前記ドリフト層（１２、１２Ａ）上のうちの他の領域である第２領域を覆って配置された、表面電極（２）と、
    　前記表面電極（２）上に部分的に形成された接合層（４０）と、
    　前記接合層（４０）上に形成されたはんだ層（３）と、
    　前記はんだ層（３）上に配置されたリードフレーム（１）と、
    　前記第２領域上に配置された配線構造とを備え、
    　前記接合層（４０）は前記第１領域に対応する前記表面電極（２）上の領域を覆い、かつ、前記接合層（４０）の端部は前記第２領域に対応する前記表面電極（２）上の領域に位置し、
    　前記表面電極（２）は、前記配線構造を覆って配置され、
    　前記配線構造は、
    　ポリシリコン（１６）と、
    　前記ポリシリコン（１６）を覆って形成された第２層間絶縁膜（１７）とを備えることを特徴とする、
    半導体装置。     A first conductivity type drift layer (12, 12A);
    A gate structure formed in a first region which is a partial region on the drift layer (12, 12A);
    A surface electrode (2) disposed over the first region and a second region which is another region on the drift layer (12, 12A);
    A bonding layer (40) partially formed on the surface electrode (2);
    A solder layer (3) formed on the bonding layer (40);
    A lead frame (1) disposed on the solder layer (3);
    A wiring structure disposed on the second region,
    The bonding layer (40) covers a region on the surface electrode (2) corresponding to the first region, and an end portion of the bonding layer (40) is the surface electrode (2 corresponding to the second region). ) Located in the upper area,
    The surface electrode (2) is disposed over the wiring structure;
    The wiring structure is
    Polysilicon (16);
    A second interlayer insulating film (17) formed to cover the polysilicon (16),
    Semiconductor device.
  6. 第１導電型のドリフト層（１２）と、
    　前記ドリフト層（１２）上に形成された、第２導電型のベース層（１０）と、
    　前記ベース層（１０）表層から前記ドリフト層（１２）内に達して形成された溝（１３）と、
    　前記溝（１３）の側面および底面に沿って形成されたゲート絶縁膜（８）と、
    　前記溝（１３）内の前記ゲート絶縁膜（８）の内側に形成されたゲート電極（９）と、
    　前記ベース層（１０）表層において前記溝（１３）を挟んで形成された、第１導電型のソース層（７）と、
    　前記溝（１３）と、前記ソース層（７）の一部とを覆って形成された、層間絶縁膜（６）と、
    　前記ベース層（１０）および前記層間絶縁膜（６）を覆って配置された、表面電極（２）と、
    　前記表面電極（２）上に部分的に形成された絶縁層（５）と、
    　前記絶縁層（５）の端部を覆い、かつ、前記表面電極（２）上の前記絶縁層（５）が形成されていない領域を覆って形成された接合層（４Ｂ）と、
    　前記接合層（４Ｂ）上に形成されたはんだ層（３）と、
    　前記はんだ層（３）上に配置されたリードフレーム（１）とを備えることを特徴とする、
    半導体装置。     A first conductivity type drift layer (12);
    A second conductivity type base layer (10) formed on the drift layer (12);
    A groove (13) formed from the surface layer of the base layer (10) to the drift layer (12);
    A gate insulating film (8) formed along the side and bottom surfaces of the trench (13);
    A gate electrode (9) formed inside the gate insulating film (8) in the trench (13);
    A first conductivity type source layer (7) formed on the surface of the base layer (10) with the groove (13) interposed therebetween;
    An interlayer insulating film (6) formed to cover the groove (13) and a part of the source layer (7);
    A surface electrode (2) disposed over the base layer (10) and the interlayer insulating film (6);
    An insulating layer (5) partially formed on the surface electrode (2);
    A bonding layer (4B) formed so as to cover an end portion of the insulating layer (5) and a region on the surface electrode (2) where the insulating layer (5) is not formed;
    A solder layer (3) formed on the bonding layer (4B);
    A lead frame (1) disposed on the solder layer (3),
    Semiconductor device.
  7. 前記絶縁層（５）が、ポリイミド層であることを特徴とする、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the insulating layer is a polyimide layer.
  8. 第１導電型のドリフト層（１２）と、
    　前記ドリフト層（１２）上に形成された、第２導電型のベース層（１０）と、
    　前記ベース層（１０）表層から前記ドリフト層（１２）内に達して形成された溝（１３）と、
    　前記溝（１３）の側面および底面に沿って形成されたゲート絶縁膜（８）と、
    　前記溝（１３）内の前記ゲート絶縁膜（８）の内側に形成されたゲート電極（９）と、
    　前記ベース層（１０）表層において前記溝（１３）を挟んで形成された、第１導電型のソース層（７）と、
    　前記溝（１３）と、前記ソース層（７）の一部とを覆って形成された、層間絶縁膜（６）と、
    　前記ベース層（１０）および前記層間絶縁膜（６）を覆って配置された、表面電極（２）と、
    　前記表面電極（２）上に部分的に形成された、表面電極（２）とは異なる金属からなる異種金属層（４１）と、
    　前記異種金属層（４１）上に形成され、当該異種金属層（４１）が介在することにより前記表面電極（２）との密着性が弱められた接合層（４）と、
    　前記接合層（４）上に形成されたはんだ層（３）と、
    　前記はんだ層（３）上に配置されたリードフレーム（１）とを備えることを特徴とする、
    半導体装置。     A first conductivity type drift layer (12);
    A second conductivity type base layer (10) formed on the drift layer (12);
    A groove (13) formed from the surface layer of the base layer (10) to the drift layer (12);
    A gate insulating film (8) formed along the side and bottom surfaces of the trench (13);
    A gate electrode (9) formed inside the gate insulating film (8) in the trench (13);
    A first conductivity type source layer (7) formed on the surface of the base layer (10) with the groove (13) interposed therebetween;
    An interlayer insulating film (6) formed to cover the groove (13) and a part of the source layer (7);
    A surface electrode (2) disposed over the base layer (10) and the interlayer insulating film (6);
    A dissimilar metal layer (41) made of a metal different from the surface electrode (2), partially formed on the surface electrode (2);
    A bonding layer (4) formed on the dissimilar metal layer (41), wherein the dissimilar metal layer (41) is interposed to weaken adhesion to the surface electrode (2);
    A solder layer (3) formed on the bonding layer (4);
    A lead frame (1) disposed on the solder layer (3),
    Semiconductor device.
PCT/JP2013/075235 2013-09-19 2013-09-19 Semiconductor device WO2015040712A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE112013007447.8T DE112013007447B4 (en) 2013-09-19 2013-09-19 semiconductor device
PCT/JP2013/075235 WO2015040712A1 (en) 2013-09-19 2013-09-19 Semiconductor device
JP2015537502A JP6046262B2 (en) 2013-09-19 2013-09-19 Semiconductor device
CN201380079685.7A CN105556661B (en) 2013-09-19 2013-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/075235 WO2015040712A1 (en) 2013-09-19 2013-09-19 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2015040712A1 true WO2015040712A1 (en) 2015-03-26

Family

ID=52688397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/075235 WO2015040712A1 (en) 2013-09-19 2013-09-19 Semiconductor device

Country Status (4)

Country Link
JP (1) JP6046262B2 (en)
CN (1) CN105556661B (en)
DE (1) DE112013007447B4 (en)
WO (1) WO2015040712A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028069A (en) * 2015-07-21 2017-02-02 トヨタ自動車株式会社 Semiconductor device
JP2017162993A (en) * 2016-03-09 2017-09-14 トヨタ自動車株式会社 Switching element
WO2019049572A1 (en) * 2017-09-05 2019-03-14 富士電機株式会社 Silicon carbide semiconductor device and silicon carbide semiconductor device production method
US10943981B2 (en) 2017-08-24 2021-03-09 Flosfia Inc. Semiconductor device
US11245013B2 (en) 2017-09-05 2022-02-08 Fuji Electric Co., Ltd. Silicon carbide semiconductor device having a step film formed between a plating film and a first electrode
DE102017104715B4 (en) 2016-03-09 2022-09-08 Toyota Jidosha Kabushiki Kaisha switching device
DE102017104713B4 (en) 2016-03-09 2022-12-15 Denso Corporation switching device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346700B (en) * 2017-01-24 2021-10-12 株式会社电装 Semiconductor device and method for manufacturing the same
JP7248961B2 (en) 2017-08-24 2023-03-30 株式会社Flosfia semiconductor equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266483A (en) * 2006-03-29 2007-10-11 Sanyo Electric Co Ltd Semiconductor device and method for manufacturing same
JP2011066371A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same
JP2013004943A (en) * 2011-06-22 2013-01-07 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803667B2 (en) 2001-08-09 2004-10-12 Denso Corporation Semiconductor device having a protective film
JP4078993B2 (en) 2003-01-27 2008-04-23 三菱電機株式会社 Semiconductor device
JP2007142138A (en) 2005-11-18 2007-06-07 Mitsubishi Electric Corp Semiconductor device
JP4873002B2 (en) * 2008-12-12 2012-02-08 株式会社デンソー Manufacturing method of semiconductor device
US8507352B2 (en) 2008-12-10 2013-08-13 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
JP5279632B2 (en) * 2009-06-25 2013-09-04 三菱電機株式会社 Semiconductor module
DE102010038933A1 (en) * 2009-08-18 2011-02-24 Denso Corporation, Kariya-City Semiconductor chip and metal plate semiconductor device and method of manufacturing the same
JP2013045973A (en) * 2011-08-25 2013-03-04 Panasonic Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266483A (en) * 2006-03-29 2007-10-11 Sanyo Electric Co Ltd Semiconductor device and method for manufacturing same
JP2011066371A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same
JP2013004943A (en) * 2011-06-22 2013-01-07 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028069A (en) * 2015-07-21 2017-02-02 トヨタ自動車株式会社 Semiconductor device
JP2017162993A (en) * 2016-03-09 2017-09-14 トヨタ自動車株式会社 Switching element
CN107180863A (en) * 2016-03-09 2017-09-19 丰田自动车株式会社 Switch element
DE102017104716B4 (en) 2016-03-09 2020-06-18 Denso Corporation SWITCHING DEVICE
CN107180863B (en) * 2016-03-09 2020-08-11 株式会社电装 Switching element
DE102017104715B4 (en) 2016-03-09 2022-09-08 Toyota Jidosha Kabushiki Kaisha switching device
DE102017104713B4 (en) 2016-03-09 2022-12-15 Denso Corporation switching device
US10943981B2 (en) 2017-08-24 2021-03-09 Flosfia Inc. Semiconductor device
WO2019049572A1 (en) * 2017-09-05 2019-03-14 富士電機株式会社 Silicon carbide semiconductor device and silicon carbide semiconductor device production method
JPWO2019049572A1 (en) * 2017-09-05 2019-12-26 富士電機株式会社 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US11145724B2 (en) 2017-09-05 2021-10-12 Fuji Electric Co., Ltd. Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US11245013B2 (en) 2017-09-05 2022-02-08 Fuji Electric Co., Ltd. Silicon carbide semiconductor device having a step film formed between a plating film and a first electrode

Also Published As

Publication number Publication date
CN105556661B (en) 2018-07-24
CN105556661A (en) 2016-05-04
DE112013007447T5 (en) 2016-06-16
JPWO2015040712A1 (en) 2017-03-02
JP6046262B2 (en) 2016-12-14
DE112013007447B4 (en) 2022-01-27

Similar Documents

Publication Publication Date Title
JP6046262B2 (en) Semiconductor device
US10643967B2 (en) Power semiconductor device that includes a copper layer disposed on an electrode and located away from a polyimide layer and method for manufacturing the power semiconductor device
US20060017174A1 (en) Semiconductor device
US20120306087A1 (en) Semiconductor device including excess solder
US10115798B2 (en) Semiconductor device and method of manufacturing the same
JP6366723B2 (en) Semiconductor device and manufacturing method thereof
JP2017069569A (en) Semiconductor device
JP6192561B2 (en) Power semiconductor device
WO2017183580A1 (en) Semiconductor device, power module, and method for manufacturing same
JP6653199B2 (en) Semiconductor device
JP5899952B2 (en) Semiconductor module
JP7099115B2 (en) Semiconductor equipment
KR20050074893A (en) Semiconductor device
JP4586508B2 (en) Semiconductor device and manufacturing method thereof
JP2013113638A (en) Semiconductor device
JP2015144169A (en) semiconductor module
US10784255B2 (en) Diode having a plate-shaped semiconductor element
US9553067B2 (en) Semiconductor device
JP6316221B2 (en) Semiconductor device
TWI569396B (en) Chip structure having bonding wire
JP4649948B2 (en) Semiconductor device
KR20170014635A (en) Semiconductor package and method manufacturing the same
JP7274954B2 (en) semiconductor equipment
WO2023203688A1 (en) Semiconductor device and production method for semiconductor device
JP6269417B2 (en) Semiconductor device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201380079685.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13893984

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2015537502

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 112013007447

Country of ref document: DE

Ref document number: 1120130074478

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13893984

Country of ref document: EP

Kind code of ref document: A1