JP2008288476A - High breakdown voltage ic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor device capable of increasing dV/dt resistance and preventing malfunctions because of the latch-up of a parasitic element structure within a high potential island even in the case of using an insulation separation structure even when using a high breakdown voltage junction terminating structure which can be manufactured inexpensively. <P>SOLUTION: A high potential gate driving circuit part and a level shift circuit part are provided on the same other conductivity type semiconductor substrate 1, at least one lateral MOSFET is formed in the gate driving circuit part, and an embedded insulating film 3 for parasitic element suppression is provided selectively in a parallel direction on the main surface of the semiconductor substrate at the lower part of the source region 5 and drain region 7 of the lateral MOSFET. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high withstand voltage IC which is made into one chip by mounting semiconductor elements having different functions on the same semiconductor substrate, and further increases the function by using dielectric isolation (SOI) technology.

  Power devices such as IGBTs and power MOSFETs are generally used for speed control of various motors and dimming control of lighting devices. Conventionally, the power device itself has been controlled by an electronic circuit combining individual semiconductor elements and electronic components provided for each application. However, a power module in which the power device and the electronic circuit are incorporated in the same package as a module, High voltage ICs mounted on the same semiconductor substrate have come into practical use. With these semiconductor technologies, converters and inverters that employ high-voltage conversion technology and frequency conversion technology have made further progress toward miniaturization of equipment.

Conventionally, a layout in which a high potential portion and a low potential portion are electrically separated is employed in an integrated circuit or the like used as a high voltage driver for control driving such as a power supply device. As the insulation isolation structure between the high potential part and the low potential part, a structure using a pn junction (junction isolation structure) and a structure using a dielectric such as SiO ₂ (dielectric isolation structure) are generally used. In addition, a separation structure using a high-breakdown-voltage junction termination structure, which is a kind of junction separation structure and can reduce costs, has been developed. As a semiconductor device having such an isolation structure, an integrated circuit having a high potential portion and a low potential portion, particularly a circuit configuration composed of a high-voltage driver for control drive such as a power supply device is known. (Patent Document 2).

  In the junction isolation structure, for example, a wafer in which an n-type epitaxial layer is stacked on a p-type semiconductor substrate is used. A driver circuit comprising a p-type semiconductor layer island formed three-dimensionally by a pn junction accompanying the p-type semiconductor layer formed in the n-type epitaxial layer and a CMOS circuit further formed in the island. Are electrically separated. When a reverse bias voltage is applied to the pn junction between the n-type epitaxial layer and the p-type semiconductor substrate, the island of the p-type semiconductor layer is electrically isolated by the junction capacitance, thereby realizing a high breakdown voltage.

  In the junction isolation method, a buried region is formed in the lower part of the device, and a displacement current accompanying a sudden change in dV / dt applied to the pn junction at the time of on / off is absorbed by the buried region. Therefore, the dV / dt resistance is relatively low. Although there is an advantage of high, when a reverse bias voltage is applied, the electric field is evenly shared on the flat bottom surface of the pn junction, but the electric field tends to concentrate on the curvature portion of the junction end, and the breakdown voltage tends to decrease. There is. In order to alleviate the electric field concentration at the junction end, it is also preferable to adopt a known RESURF (REduced SURface Electric Field) structure shown in FIG.

  Furthermore, generally, each of the various pn junctions constituting the integrated circuit has a junction capacitance. When this pn junction capacitance is regarded as a capacitor, when a voltage with a sharp change (dV / dt) waveform is applied to the capacitor, a charging current (displacement current) flows over the entire junction surface of the pn junction. This displacement current causes a parasitic transistor formed in the semiconductor region to operate, causing a malfunction of the circuit and element destruction.

For example, in a large-capacity inverter device, the level of potential change, that is, dV / dt is generally about 30 kV / μs. In the high voltage IC, when the potential of the high potential island changes at the potential change level as described above during switching of the power device, a displacement current is generated in the depth direction of the semiconductor substrate, and the parasitic transistor in the high potential island is latched up. It becomes easy.
In addition, this junction isolation structure is characterized in that junction isolation can be manufactured at low cost by planar junction formed by ion implantation and thermal diffusion using an inexpensive normal silicon wafer without using an expensive epitaxial wafer. A separation structure that can be regarded as a kind of self-separation structure has also been developed (see, for example, Patent Document 1). Hereinafter, in this specification, the self-separation structure that can be manufactured at low cost will be referred to as a high-voltage junction termination structure.

On the other hand, the dielectric isolation structure has, for example, a laminated structure in which a silicon semiconductor layer serving as an active region is deposited thereon via a BOX layer (buried oxide film) such as a SiO ₂ film formed on a silicon substrate. Further, a predetermined functional circuit is provided in a silicon semiconductor layer electrically isolated by the BOX layer (buried oxide film), thereby electrically isolating the functional circuit (SOI structure). According to this dielectric isolation structure, a plurality of circuits that operate at different reference potentials can be provided in the same substrate for each insulated silicon semiconductor layer, so that a circuit including a high breakdown voltage can be easily designed. is there. Further, in this dielectric isolation structure, the SOI structure using a thick SiO ₂ film can easily obtain a dV / dt resistance of about 50 kV / μs, and does not generate a parasitic thyristor or a parasitic transistor. Although there is an advantage that there is no problem such as malfunction, a BOX layer (buried oxide film) with a thickness on the order of μm is required when the withstand voltage level exceeds 1000 V, so a substrate using a bonding technique must be used. As in the case of the junction separation structure using an epitaxial wafer, the problem of high wafer cost is inevitable.

In recent years, a SIMOX (Separated by Implanted Oxygen) technique for manufacturing a thin buried oxide (BOX) layer of about 100 nm has been developed, and an SOI substrate can be supplied at low cost. According to the SIMOX technology, for example, an acceleration energy is set to about 200 keV, oxygen atoms having a dose amount of about 2 × 10 ¹⁸ atoms / cm ² are ion-implanted, and heat treatment is performed at a high temperature to thereby form a buried oxide film (hereinafter referred to as BOX). Layer)). In this SIMOX method, the dose amount and the implantation energy can be accurately controlled, so that the thickness of the BOX layer and the thickness of the SOI layer can be uniformly formed with a required thickness. Further, according to this SIMOX technique, a buried oxide film can be partially formed in an arbitrary region, so that the capacity of the BOX layer can be reduced. However, simply reducing the thickness of the BOX layer causes a decrease in breakdown voltage, which makes it difficult to increase the breakdown voltage.

  Hereinafter, a specific circuit configuration example will be described with respect to a problem when the high-breakdown-voltage junction termination structure capable of an inexpensive process is used as an insulating isolation structure formed on a semiconductor substrate. FIG. 2 is a block circuit diagram of a control device using a high-breakdown-voltage IC unit for the circuit configuration of the lighting inverter device. This block circuit receives a signal from the input / output terminal I / O, and controls a control circuit 21 that determines the on / off timing of two IGBTs Q1 and Q2, which are power devices, and a low potential gate of the low potential side IGBT Q2. The driving circuit GDUL22, a high potential gate driving circuit GDUH23 for driving the high potential side IGBT Q1, and a level shift circuit 24 for converting the signal level to the high potential side GDUH23. Since the back electromotive force generated when the inductance is loaded flows through the IGBTs Q1 and Q2, diodes D1 and D2 are connected in parallel to form a half bridge circuit. Here, the high potential gate drive circuit GDUH 23 and the level shift circuit 24 are referred to as a high breakdown voltage IC unit 25. Further, among the block circuits of the lighting inverter device, the control circuit 21 for one phase of the bridge circuit, the low-potential gate drive circuit GDUL22, and the high-breakdown-voltage IC unit 25 are integrated on the same semiconductor substrate, and the high-breakdown-voltage IC semiconductor. FIG. 12 shows a plan view of the substrate. In an actual IC substrate, the three phases of the bridge circuit are integrated. Of these, the present invention to be described later relates to the high voltage IC section 25.

As the main power supply voltage, a direct current of 100 to 400 V is usually used. Assuming that main power supply voltage Vcc is 400 V, IGBT Q1 is turned on when, for example, 415 V including gate voltage V _DD 15 V is applied to the gate electrode of high potential side IGBT Q1. After the IGBT Q1 is turned off, the low-potential-side IGBT Q2 is turned on, whereby an AC rectangular wave corresponding to, for example, the gate switching period is generated at the output terminal _VOUT .

When the high potential side IGBT Q1 is turned on, the potential of the output terminal _VOUT is substantially equal to the potential of the main power supply voltage Vcc, and when the IGBT Q2 is turned on, the potential of the output terminal _VOUT is substantially equal to the GND potential. . Accordingly, the main power supply voltage Vcc and the gate drive voltage are added between the high-potential gate drive circuit GDUH 23 constituting the high-breakdown-voltage IC section 25 and other control circuit units such as a low-breakdown-voltage signal circuit and drive circuit. Pressure resistance is required. A predetermined control signal from the control circuit 21 such as a required signal processing circuit or drive circuit is sent to the high potential gate drive circuit GDUH 23 formed in this high potential island through the signal level shift circuit 24, and the high potential side IGBT Q1 is turned on / off in accordance with the predetermined control signal.
The above-described dielectric isolation structure, junction isolation, high voltage junction termination structure, and the like are required as a high voltage isolation structure that enables such a withstand voltage in a semiconductor substrate on which the high voltage IC portion 25 is mounted.

2 is a cross-sectional view of a semiconductor substrate when the high voltage IC portion 25 in the block circuit diagram showing the lighting inverter device of FIG. 2 is configured as a conventional high voltage IC portion 25 using a high voltage junction termination structure as an isolation structure. Is shown in FIG. Regions AB and A′-B ′ in FIG. 3 are portions corresponding to the high-voltage junction termination structure, and correspond to AB and A′-B ′ shown in the plan view of FIG. Furthermore, the region located in the BB ′ region is a high potential island (isolation region) corresponding to BB ′ in FIG. The potential of the high potential side terminal (V _DH ) taken out from the n-well region of this high potential island is the potential (GND) of the low potential side semiconductor substrate (Psub) 1 due to the high withstand voltage junction termination structure surrounding the periphery. Electrically separated. The potential V _DH on the high potential side of the high potential island is about 15 V to turn on the IGBT Q1 as described above with respect to the potential V _DL on the low potential side which is the other terminal (Vout) of the high potential island. The gate voltage (V _DD ) is increased.

In the AB region and the A′-B ′ region, which are high breakdown voltage junction termination structures in the high breakdown voltage IC shown in FIG. 3, the p-offset region 16 functioning as a RESURF structure is formed as an n well region (one conductivity type semiconductor). By providing it in (region) 2, it is possible to alleviate electric field concentration at the junction termination portion.
FIG. 7 is a cross-sectional view of the semiconductor substrate of the level-up element portion that constitutes a part of the AB region and the A′-B ′ region, which are high breakdown voltage junction termination structures in the high breakdown voltage IC portion 25. 12 shows a DD ′ cross section.

In order to transmit a signal from the substrate region (Psub) 1 on the low potential side (reference potential GND) to the high potential island 4 side shown in FIG. 3, as shown in FIG. , A′-B ′ is partly formed into an n-type high breakdown voltage MOSFET composed of drain drain-n ⁺ drain region 11b-n well region 11a-n well region 2-p well region 10a-n ⁺ source region 13-source S. On the high-potential island side, which is not shown in FIG. 7 and is located on the right side in the figure, with the gate voltage as an on / off signal, the product of the resistance R and the current connected to the drain Drain, that is, the potential difference is reduced. An input signal to the withstand voltage circuit section.

FIG. 8 shows a case where a p-type MOSFET composed of drain drain-p ⁺ drain region 12a-p well region 8-p offset region 16-n well region 2-n well region 11-p ⁺ source region 13a-source S is used. FIG. 13 is a cross-sectional view of a level-down element for transmitting a signal from a potential island side to a substrate region on a low potential side, and shows the CC ′ cross section of FIG. The level-down element (FIG. 8) and the level-up element (FIG. 7) are generally called a level shift circuit (signal transmission circuit) and each have a high breakdown voltage MOSFET structure.

High voltage IC configuration capable of preventing a reduction in breakdown voltage at low cost by connecting a high potential gate drive circuit in a high potential island electrically isolated by a high breakdown voltage junction termination structure to a high breakdown voltage level shift circuit Is described in a publicly known document (Patent Document 2).
Occurs when a reverse bias voltage is applied to the pn junction by providing a high-potential gate drive circuit electrically isolated by a high-voltage junction termination structure, a trench reaching the semiconductor substrate, and an electrode having a ground potential in the trench. There is also a description in a publicly known document indicating that the latch-up of the parasitic thyristor structure due to the charging current can be prevented (Patent Document 3).

In a semiconductor device including a vertical power element and a control circuit for controlling the power element on the same semiconductor substrate, a partial insulator layer is formed below the control circuit in a well region where the control circuit is provided. Thus, there is a description that the displacement current generated when the power element is turned off is blocked by an insulator layer to prevent word operation of the control circuit (Patent Document 4).
JP-A-9-55498 Japanese Patent Laid-Open No. 9-74198 JP 2005-191263 A Japanese Patent No. 2871939

  However, as described above, since the high-voltage junction termination structure uses an inexpensive normal silicon wafer instead of an expensive epitaxial wafer, an insulating isolation structure by planar bonding formed by thermal diffusion can be manufactured at low cost. For example, among the n-type MOSFET and the p-type MOSFET (FIG. 10) formed in the high potential island 4 (isolation region) (BB ′ in FIG. 3), for example, in FIG. When dt is applied between the region of the n well region 2 and the semiconductor substrate (Psub) 1 through the electrode terminal, for example, the source terminal S, the n base region 9 and the substrate potential (reference potential GND), the n well region 2 is depleted, Electrons flow laterally through the n-well region 2 as indicated by arrows and are discharged through the n-base region 9. Since the resistance component 19 in the n-well region 2 is used as a current path, the base potential of the parasitic transistor 20 rises, and the parasitic transistor 20 including the p-type offset region 5, the n-well region 2, and the p-type substrate region 1 is turned on. The problem of malfunction caused by parasitic elements that lead to malfunction still remains.

  The present invention has been made in view of the above points. The object of the present invention is to provide a high dV / dt resistance even in the case of using an insulation isolation structure with a high voltage junction termination structure that can be manufactured at low cost. It is an object of the present invention to provide a high voltage IC capable of preventing malfunction due to latch-up of a parasitic element structure in a potential island.

  According to the first aspect of the present invention, in order to achieve the object of the present invention, one of the main terminals is connected to the high potential side (Vcc) of the high voltage power source, and the main terminal is connected to the load side. A high-voltage IC for driving the gate of the power device to which the other of the power devices is connected, wherein the current is supplied by a low-voltage power supply with the other main terminal of the power device as a reference (Vout) A level shift that converts a signal from a circuit unit and a control circuit supplied with a current from a low voltage power source with a low potential side (GND) of the high voltage power source as a reference into a signal to the high potential gate drive circuit unit A high-potential gate drive circuit portion and a level shift circuit portion formed in one well-type well region provided on a surface layer of the other-conductivity-type semiconductor substrate. The And at least one lateral MOSFET is formed in the gate driving circuit section, and selectively in a direction parallel to the main surface of the semiconductor substrate in the well region, and a source region of at least one lateral MOSFET of the lateral MOSFET, and A high breakdown voltage IC having a buried insulating film for suppressing parasitic elements below the drain region.

According to the invention of claim 2, the buried insulating film extends to a base region of one conductivity type that is an outer periphery of the high-potential gate drive circuit unit, and the high-potential gate drive circuit is The high breakdown voltage IC according to claim 1, which is a region surrounded by the buried insulating film and the base region.
According to a third aspect of the present invention, in the high breakdown voltage IC according to the first aspect, the buried insulating film is in contact with the lower end surfaces of the source region and the drain region of the lateral MOSFET. .

  According to a fourth aspect of the present invention, the buried insulating film is in contact with a lower end surface of a one-conductivity type base region that is an outer periphery of the high-potential gate drive circuit unit. 2. High voltage IC according to 2.

  According to the present invention, even when an insulation isolation structure using a high voltage junction termination structure that can be manufactured at low cost is used, dV / dt resistance is high, and malfunction due to latch-up of a parasitic element structure in a high potential island can be prevented. A high voltage IC can be provided.

Hereinafter, a method for manufacturing a high voltage IC according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1-1 is a cross-sectional view of a main part of a high voltage IC according to Example 1 of the present invention, and FIG. 1-2 is a cross-sectional view of a main part showing a BOX layer at a different position of the high voltage IC according to Example 1 of the present invention. 4 is a cross-sectional view of a semiconductor substrate showing a portion of a BOX layer of a high voltage IC according to a second embodiment of the present invention, and FIG. 5 is a semiconductor showing a portion of a BOX layer of the high voltage IC according to a third embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor substrate showing a portion of a BOX layer of a high voltage IC according to a fourth embodiment of the present invention. FIG. 11 is a sectional view of the BOX layer of the high voltage IC according to a fifth embodiment of the present invention. It is the top view (a) which shows the high voltage | pressure-resistant IC which shows a range, and principal part sectional drawing (b).

  The high voltage IC according to the present invention is related to the improvement of the high voltage IC portion 25 in the block circuit shown in FIG. In addition to the high voltage junction termination structure for electrically isolating and isolating the high potential island (isolation region) from the low potential region (potential GND of the p-type silicon substrate) around the high potential island (isolation region), With respect to a structure in which the operation of the parasitic element can be suppressed by providing a BOX layer below the low breakdown voltage lateral MOSFET structure in the island, FIG. FIG. 2 shows a cross-sectional view of a main part of a semiconductor substrate on which a BOX layer is formed. The high breakdown voltage IC includes an n-type semiconductor region (n-well region) 2 having a diffusion depth of about 6 μm formed in a surface layer of a p-type silicon substrate (psub) 1 and a part of the surface of the n-well region 2. A basic structure is a partial SOI structure including an active region made of an n-type semiconductor region 4 having a depth of about 3 μm provided via a BOX layer (buried oxide film) 3 having a thickness of 50 nm.

The main part of the manufacturing process of the high voltage IC according to the first embodiment of the present invention (the manufacturing process of the BOX layer and the lateral MOSFET structure in the high potential island) will be described below. Oxygen ions are implanted into the p-type silicon semiconductor substrate 1 having an impurity concentration of 6 × 10 ¹³ cm ⁻³ with an implantation energy of 180 keV and a dose of 5 × 10 ¹⁷ cm ⁻² , and heat treatment is performed at a temperature of about 1350 ° C. for about 2 hours. Then, the BOX layer 3 having a thickness of 50 nm is formed as an SOI structure at a depth of 0.3 μm from the surface of the semiconductor substrate. Next, phosphorus is implanted at an implantation energy of 280 keV and a dose of 1 × 10 ¹² cm ⁻² and heat-treated at a temperature of about 950 ° C. for about 60 minutes. ^{Subsequently,} a p-type silicon layer having an impurity concentration of 6 × 10 ¹³ cm ⁻³ is deposited to a thickness of 3 μm using an epitaxial growth method at a substrate temperature of 900 ° C. Subsequently, phosphorus is implanted at an implantation energy of 150 keV and at a dose of 5 × 10 ¹² cm ⁻² , and heat-treated at a temperature of about 1150 ° C. for about 200 minutes, and the region including the BOX layer (buried oxide film) 3 and the silicon substrate The n-well region 2 having a surface concentration of 3 × 10 ¹⁵ cm ⁻³ and a junction depth Xj of about 6 μm can be uniformly formed across both regions. In the p-type offset regions 5 and 7 serving as the drain or source region, boron is implanted at an implantation energy of 50 keV at a dose of 1 × 10 ¹³ cm ⁻² , and heat-treated at a temperature of about 1100 ° C. for about 300 minutes. Is 9 × 10 ¹⁶ cm ⁻³ and the junction depth Xj is 3 μm.

In the n-type base regions 9 and 11, phosphorus is implanted at an implantation energy of 150 keV and a dose amount of 7 × 10 ¹² cm ⁻² , and heat-treated at a temperature of about 1100 ° C. for about 300 minutes, and the surface concentration is 7 × 10 ¹⁶ cm ^{−. 3.} An impurity concentration distribution with a junction depth Xj of 3 μm is obtained.
Next, the p ⁺ source and drain contact regions 6 and 8 formed on the surfaces of the p-type offset regions 5 and 7 and the surfaces of the n-type base regions 9 and 11 are formed using a general semiconductor process. A p-type MOSFET structure comprising n ⁺ contact regions 10 and 12, gate insulating film 13, gate polysilicon 14, source electrode terminal S, gate electrode terminal G, drain electrode terminal D, and silicon oxide film (LOCOS) 15 was fabricated. . According to the high breakdown voltage IC of Example 1 shown in FIG. 1-1 described above, the BOX layer having a thickness of 50 nm is formed so as to be in contact with the lower end surfaces of the p-type MOSFET structure and the n-type base regions 9 and 11 on the outer periphery thereof. Therefore, as described in the above section of the problem to be solved, even if dV / dt is applied between the source electrode terminal S and the psub (p-type semiconductor substrate) 1 in FIG. The above-described BOX layer 3 newly provided as -1 can prevent the generation of a parasitic transistor and solve the malfunction problem. Further, the thickness of the BOX layer 3 needs to be a thickness that can be formed by the SIMOX method. However, even if the thickness of the BOX layer 3 is as thin as 50 nm, for example, the breakdown voltage is maintained by the high breakdown voltage junction isolation structure. In FIG. 1-1, the BOX layer 3 having a thickness of 50 nm is configured to be in contact with the p-type MOSFET structure and the lower end surfaces of the n-type base regions 9 and 11 on the outer periphery thereof. A lateral MOSFET structure in which the mold base regions 9 and 11 are not formed may be employed. In that case, the BOX layer is arranged up to the lower end surface of the p-type MOSFET structure.

As a result, in the conventional example without the BOX layer shown in FIG. 10, the dV / dt withstand voltage at 175 ° C. was 20 kV / μs, but by providing the BOX layer, the high breakdown voltage IC of Example 1 shown in FIG. Then, it improved to 30 kV / μs.
However, in FIG. 1-1, the BOX layer 3 is disposed so as to be in contact with the bottom surfaces of the p-type offset regions 5 and 7 and the n-type base regions 9 and 11, thereby completely providing the parasitic element (transistor structure) function. However, as shown in FIG. 1-2, the BOX layer 3 may be provided in the n-well region 2 below the p-type offset regions 5 and 7 and the bottom surfaces of the n-type base regions 9 and 11. The further away the BOX layer 3 is, the smaller the electric resistance flowing in the lateral direction in the n-well region becomes. Therefore, the influence of the parasitic element increases, but it can be separated to such an extent that malfunction does not substantially cause a problem. Similarly, the range in which the BOX layer 3 is arranged in the direction parallel to the main surface of the substrate in the n-well region 2 may be arranged in such a range that malfunction does not substantially become a problem.

  Since the back electromotive force generated by di / dt at the time of L load becomes a form in which the diode is forward-biased, the negative voltage withstand capability can be improved by reducing the current value. In the high voltage IC of the present invention, when a voltage of -70 V was applied, the substrate current was 3.5 A, which was 3.5 A in the past.

  Example 2 of the high voltage IC according to the present invention is an application example of a BOX layer to a low voltage n-type MOSFET structure in a high potential island, and FIG. 4 shows a semiconductor of a high voltage IC used in the description of Example 2. It is principal part sectional drawing of a board | substrate. A Bi-CMOS structure is made possible by forming an n-type MOSFET structure in an n-well region to which a reverse bias of several tens of volts is applied. The difference from the first embodiment is that a BOX layer (buried oxide film) 33 is formed at the boundary between the p well region 49 and the n well region 2 provided in the surface layer of the n well region 2 and an n source region composed of an n type offset region. 35, the n drain region 37, and the p base regions 34 and 36 located around these regions are arranged in a range that covers them. In the second embodiment, a conventional parasitic transistor (thyristor) including the substrate (Psub) 1, the n well region 2, the p well region 49, the n source region 35 including the n type offset region or the n drain region 37 in FIG. The purpose is to prevent latch-up. According to the high breakdown voltage IC (FIG. 4) of Example 2 of the present invention, the dV / dt resistance at 175 ° C. was 30 kV / μs. The conventional high voltage IC shown in FIG. 9 is improved from the dV / dt resistance, 20 kV / μs.

  In FIG. 4, the BOX layer 33 is disposed so as to be in contact with the lower end surface of the p-well region 49. For the same reason as in the first embodiment, the BOX layer 33 is separated downward from the lower end surface to such an extent that malfunction does not substantially cause a problem. It may be.

  In FIG. 5 according to the third embodiment, n base regions 50 and 51 for discharging electrons from the n well region 2 to GND are further provided on the outer periphery of the n-type MOSFET (FIG. 4) of the second embodiment. It is principal part sectional drawing of the semiconductor substrate which shows having changed into the structure which prevents the latchup which uses the p well area | region 49 by the current path to another element as an emitter. According to the high voltage IC of Example 3, the dV / dt resistance at 175 ° C. was 40 kV / μs. This is an improvement over the conventional dV / dt withstand capability without a BOX layer, 20 kV / μs.

  In FIG. 5, the BOX layer 33 is disposed so as to be in contact with the lower end surface of the p-well region 49. However, for the same reason as in the first embodiment, the BOX layer 33 is not affected so much that malfunction is not a problem. May be separated downward from the lower end surface, and for the same purpose, the range in the direction parallel to the main surface of the substrate can be adjusted.

  FIG. 6 shows a cross-sectional view of a main part of a semiconductor substrate used for explanation in Example 4 according to the high voltage IC of the present invention. The high breakdown voltage IC includes an n-type semiconductor region (n-well region) 2 having a diffusion depth of about 6 μm formed in a surface layer of a p-type silicon substrate (psub) 1 and a partial surface layer of the n-well region 2. And a partial SOI structure including an active region made of an n-type semiconductor region 2-1 having a depth of about 3 μm provided via a BOX layer (buried oxide film) 3 having a thickness of 50 nm.

The main part of the manufacturing process of the high voltage IC according to Example 4 of the present invention (the manufacturing process of the BOX layer and the high potential island part will be described below). The configuration having the BOX layer (buried oxide film) 3 as the SOI structure is shown in FIG. Since the manufacturing process is basically the same as that shown in FIG. 3 except for the difference from 3, only the position of the BOX layer will be described and the others will be omitted.
In the first embodiment, the BOX layer 3 is formed only under the low breakdown voltage lateral MOSFET structures 5, 7, 9, 11 in the high potential island (isolation region) 4 as shown in FIG. Although the structure is such that the operation of the parasitic element can be suppressed by being provided partially, in the fourth embodiment, a BOX layer is provided below the entire high potential island (isolation region) 4 as shown in FIG. Is different.

  By arranging the BOX layer as described above, the dV / dt resistance at 175 ° C. was 20 kV / μs in the conventional example without the BOX layer, but the dV / dt resistance is higher in the high voltage IC of Example 4. It improved to 50 kV / μs. It can be seen that it is superior to the dV / dt resistance of 30 kV / μs in the case of Example 1.

  The high breakdown voltage IC of the fifth embodiment is intended to improve the negative voltage tolerance including the level shift circuit element, and is intended to prevent malfunction. FIG. 11A is a plan view showing the range in which the SOI layer (BOX layer) in the high voltage IC is arranged with a broken line in the high voltage IC of the fifth embodiment. FIG. 11B is an enlarged cross-sectional view of the D-D ′ portion of FIG. As shown in FIG. 11B, a parasitic transistor composed of a p-type semiconductor substrate (psub) 1, an n-well region 2, and a p-well region 10a is easy to operate, but by providing a BOX layer 3, a horizontal line indicated by an arrow is provided. A problem that the directional current flows to the drain terminal Drain and causes the malfunction due to the operation of the parasitic transistor can be suppressed to an extent that there is substantially no problem by increasing the lateral current path and reducing the resistance. In the fifth embodiment, the high breakdown voltage junction termination structures AB and A′-B ′ including the level shift circuits CC ′ and DD ′ and the high potential island (isolation region) BB ′ below both. By disposing the BOX layer 3 in the n-well region 2, the malfunction start voltage has been improved from -30V to -60V.

  The present invention according to the first to fifth embodiments described above shows an application example of a BOX layer (buried oxide film) to a circuit provided in a high potential isolation region and a high breakdown voltage junction isolation region. The thickness of the BOX layer (buried oxide film) is 50 nm in the embodiment of the present invention, but it may be several 100 nm which is the upper limit of the SIMOX method. In the above description, n-type silicon is used as the one-conductivity-type semiconductor substrate, but it may be p-type. Any semiconductor such as silicon, SiC, diamond, etc. can be used.

It is principal part sectional drawing of the high voltage | pressure-resistant IC concerning Example 1 of this invention. It is principal part sectional drawing which shows the BOX layer of the different position of the high voltage | pressure-resistant IC concerning Example 1 of this invention. It is a block circuit diagram of the inverter apparatus for illumination using high voltage | pressure-resistant IC. It is sectional drawing of the semiconductor substrate of the high voltage | pressure-resistant IC shown in FIG. It is sectional drawing of the semiconductor substrate which shows the part of the BOX layer of the high voltage | pressure-resistant IC concerning Example 2 of this invention. It is sectional drawing of the semiconductor substrate which shows the part of the BOX layer of the high voltage | pressure-resistant IC concerning Example 3 of this invention. It is sectional drawing of the semiconductor substrate which shows the part of the BOX layer of the high voltage | pressure-resistant IC concerning Example 4 of this invention. It is sectional drawing of the semiconductor substrate which shows a level-up circuit part. It is sectional drawing of the semiconductor substrate which shows a level down circuit part. It is sectional drawing of the semiconductor substrate for demonstrating operation | movement of the parasitic transistor in the low voltage | pressure-resistant n-type MOSFET structure in an isolation region. It is sectional drawing of the semiconductor substrate for demonstrating operation | movement of the parasitic transistor in the low voltage | pressure-resistant p-type MOSFET structure in an isolation region. It is a top view of the high voltage | pressure-resistant IC which shows the range of the BOX layer of the high voltage | pressure-resistant IC concerning Example 5 of this invention. 1 is a plan view of a semiconductor substrate showing a control circuit portion, a low potential gate drive circuit portion, and a high potential gate drive circuit portion for one phase, which is a high voltage IC according to the present invention.

Explanation of symbols

1. p-type silicon substrate (psub)
2, n-type semiconductor region, n-well region 3, 33 buried oxide film (BOX layer)
4, n-type active region, isolation region 5, 7 p-type offset region 9, 11 n-type base region 6, 8 p ⁺ contact region 10, 12 n ⁺ contact region 13 gate oxide film 14 gate electrode 15 thick insulating layer, Thick silicon oxide film (LOCOS)
21 Control Circuit 22 Low Potential Gate Drive Circuit 23 High Potential Gate Drive Circuit 24 Level Shift Circuit 25 High Voltage IC
35, 37 n offset region 49 p well region 50, 51 n base layer.

Claims (5)

A high voltage IC for driving the gate of a power device having one of the main terminals connected to the high potential side (Vcc) of the high voltage power supply and the other of the main terminals connected to the load side, A high-potential gate drive circuit section that is supplied with current by a low-voltage power supply that uses the other main terminal as a reference (Vout), and a current that is supplied by a low-voltage power supply that uses the low-potential side (GND) of the high-voltage power supply as a reference And a level shift circuit section for converting a signal from the control circuit to a signal to the high potential gate drive circuit section on the same other conductivity type semiconductor substrate, on the surface layer of the other conductivity type semiconductor substrate The high-potential gate drive circuit unit and the level shift circuit unit are formed in one conductivity type well region provided, and at least one lateral MOSFET is formed in the gate drive circuit unit. A buried insulating film for suppressing parasitic elements, selectively in a direction parallel to the main surface of the semiconductor substrate in the region, and below the source region and drain region of at least one lateral MOSFET of the lateral MOSFET. High-voltage IC that features. The buried insulating film extends to a base region of one conductivity type that is an outer periphery of the high-potential gate driving circuit unit, and the high-potential gate driving circuit is a region surrounded by the buried insulating film and the base region. The high voltage IC according to claim 1. 2. The high breakdown voltage IC according to claim 1, wherein the buried insulating film is in contact with a lower end surface of a source region and a drain region of the lateral MOSFET. 3. The high breakdown voltage IC according to claim 2, wherein the buried insulating film is in contact with a lower end surface of a base region of one conductivity type which is an outer periphery of the high potential gate drive circuit unit. 5. The high breakdown voltage IC according to claim 1, wherein the buried insulating film is an insulating film formed by a SIMOX method.

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