JP2013058789A - Self-scanning light-emitting element array, optical writing head and image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self-scanning light-emitting element array which achieves a high output.SOLUTION: A self-scanning light-emitting element array comprises: a semiconductor substrate; islands Sn-1, Sn, Sn+1, Sn+2 formed on the semiconductor substrate; light-emitting part thyristors Ln-1, Ln, Ln+1, Ln+2 each including semiconductor layers of a pnpn structure laminated in the islands; shift part thyristors Tn-1, Tn, Tn+1, Tn+2 each including semiconductor layers of a pnpn structure laminated in the islands; parasitic thyristors PTn, PTn+1, PTn+2, PTn+3 each formed directly under a p-n junction coupling diode laminated in the islands; and current confinement layers formed in the islands. The current confinement layer includes an oxidation region and a non-oxidation region, and the oxidation region is formed directly under a cathode layer of the parasitic thyristor.

Description

  The present invention relates to a self-scanning light emitting element array, an optical writing head, and an image forming apparatus.

  A surface light emitting element array is used for a writing head such as a contact image sensor or a printer. A typical surface light emitting element array is configured by integrating a plurality of light emitting elements arranged linearly on one substrate. As a typical surface light emitting device, a light emitting diode (LED), a light emitting thyristor, and a laser diode are known. Among them, a light emitting thyristor is one in which a compound semiconductor layer such as GaAs or AlGaAs is stacked in a pnpn structure, and a driving current is applied to a gate to cause a current to flow between an anode and a cathode to emit light. Patent Document 1 discloses a self-scanning light-emitting element array in which such light-emitting thyristors are integrated on a substrate and each light-emitting thyristor is sequentially turned on.

JP-A-1-238996

  An object of the present invention is to provide a self-scanning light-emitting element array, an optical writing head, and an image forming apparatus that achieve high output.

According to another aspect of the present invention, a light emitting unit thyristor and a shift unit thyristor are provided in a semiconductor stacked structure including a current confining layer, and the light emitting unit thyristor is formed by oxidizing the current confining layer from a side surface of the stacked structure. A self-scanning light-emitting element array having a structure, wherein the shift unit thyristor is formed at a position where a region of the current confinement layer located between an anode and a cathode of the shift unit thyristor is not oxidized by the oxidation.
The self-scanning light emitting element array according to claim 1, wherein the shift unit thyristor is formed at a position farther from the side surface of the stacked structure than the light emitting unit thyristor.
A third aspect of the present invention is an optical writing head using the self-scanning light emitting element array according to the first or second aspect.
According to a fourth aspect of the present invention, there is provided an image forming apparatus comprising the optical writing head according to the third aspect.

According to the first aspect, it is possible to suppress a decrease in the switching operation of the shift unit thyristor due to the formation of the current confinement structure.
According to claim 2, it is possible to suppress the parasitic thyristor from transitioning to the ON state.

1 is a plan view of a self-scanning light emitting thyristor array according to a first embodiment of the present invention. They are A1-A1 sectional view taken on the line of FIG. 1, A2-A2 sectional view, and A3-A3 sectional view. 3 is an equivalent circuit of the self-scanning light-emitting thyristor array according to the first embodiment of the present invention. It is a figure which shows the electric potential distribution of the gate when the shift part thyristor Tn is ignited. It is a figure which shows the voltage waveform of the signal applied from the outside. FIG. 3 is a diagram for explaining another oxidation method according to the first embodiment of the present invention. It is the top view of the self-scanning light emitting thyristor array which concerns on the 2nd Example of this invention, and its BB sectional drawing. It is the top view of the self-scanning light emitting thyristor array which concerns on the 3rd Example of this invention, and its BB sectional drawing. It is a figure which shows the operating point analysis of parasitic thyristor PTn + 1. It is a figure which shows the operating point analysis of parasitic thyristor PTn + 2. It is a figure which shows the operating point analysis of parasitic thyristor PTn + 2 when gate load resistance is made small to _{RG '} . It is a figure which shows the relationship between a cathode potential and a time change. It is an example which shows the structure of the optical writing head which applied the self-scanning light emitting element array of a present Example. This is an example in which the optical writing head using the self-scanning light emitting element array of this embodiment is applied to an optical printer.

  A light-emitting element array in which a large number of light-emitting elements are integrated on the same substrate is used as a light source used in a print head for an LED printer in combination with a drive circuit or the like. As a light emitting element, for example, in a light emitting element array in which light emitting diodes (LEDs) are arranged one-dimensionally, a signal corresponding to an image signal must be supplied to each LED from an external driving circuit. The same number of bonding pads as those for supplying power to the LEDs are required on the substrate. However, since the bond pad usually has a large area, the area of the light emitting element array chip is necessarily increased. When the chip area is increased, the number of chips that can be obtained from one wafer is reduced, which limits the cost reduction.

  For example, in a 1200 dpi print head of an A3 printer, the number of one-dimensionally arranged LEDs is 14,000 or more, and it is necessary to bond the same number of wires to bond pads. As the number of wire bondings increases, the cost for manufacturing the light emitting element array increases. Furthermore, in order to improve the quality of printed images, when creating a high-resolution light-emitting array, the number of wire bonds increases as the number of bond pads increases, and the cost increases as the chip area increases. In addition to this, there is a limit to the bond pad layout itself on the chip.

  In a self-scanning light-emitting element array in which light-emitting thyristors having a three-terminal structure are sequentially fired, when the substrate is an anode, the uppermost n layer is a cathode, and the p layer immediately below the cathode layer is a gate, If no current flows to the gate, no current flows between the anode and the cathode. A self-scanning light emitting device (hereinafter referred to as SLED (Self-scanning Light Emitting Device)) is a shift unit thyristor in which a thyristor having such properties is one-dimensionally arrayed as a switch element, and further, the thyristor is used as a light emitting element. And a light emitting unit thyristor arrayed one-dimensionally on the same substrate.

  In the SLED, there is no need to provide a bond pad corresponding to each light emitting thyristor, and by sequentially supplying a rectangular voltage to the bond pads arranged on one side or both sides of the chip, the light emitting unit thyristors are sequentially fired from the end. (Self-scanning). Therefore, in the SLED, even if the resolution is increased, the bond pad can be brought close to the end of the chip, and the increase in the number of bond pads and the resulting increase in the chip area and the increase in the number of wire bonds can be avoided. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, an SLED having a light-emitting thyristor having a pnpn structure is illustrated. The semiconductor layer constituting pnpn is made of a III-V group compound semiconductor. In this embodiment, GaAs, AlGaAs, and AlAs are used as the compound semiconductor. It should be noted that the scale of the drawings is emphasized for easy understanding of the features of the invention and is not necessarily the same as the scale of an actual device.

  FIG. 1 is a plan view of a part of the SLED according to the first embodiment of the present invention, and FIG. 2 is an A1-A1 line, an A2-A2 line, and an A3-A3 line of one island of the SLED shown in FIG. Sectional drawing and FIG. 3 are equivalent circuits of SLED shown in FIG.

First, referring to FIG. 3, there is shown an equivalent circuit for four light emitting elements as a part of the SLED 10. Ln-1, Ln, Ln + 1, Ln + 2 are light emitting unit thyristors, Tn-1, Tn, Tn + 1, Tn + 2 are shift unit thyristors, Gn-1, Gn, Gn + 1, Gn + 2 are Common gate for light emitting thyristor and shift thyristor, _RG is gate load resistance, Dn-2, Dn-1, Dn, Dn + 1 are coupling diodes, PTn-1, PTn, PTn + 1, PTn + 2 are A parasitic thyristor formed immediately below the cathode electrode of the coupling diode, Φ1 is an odd bit transfer line, Φ2 is an even bit transfer line, ΦI is a light emission signal line, and VGA is a gate line. Here, n is a positive integer. In the following description, the light emitting unit thyristor, the shift unit thyristor, and the parasitic thyristor are collectively referred to as the light emitting unit thyristor Li, the shift unit thyristor Ti, and the parasitic thyristor PTi.

  The SLED transfer function will be briefly described. Now, it is assumed that the shift unit thyristor Tn is in the on state. At this time, the potential of the gate Gn of the shift unit thyristor Tn is raised to about −0.2 V, and a potential difference of about 1.5 V corresponding to the diffusion potential is generated at both ends of the coupling diode Dn. Therefore, Gn + 1 = Gn−1.5V = −1.7V and Gn + 2 = Gn + 1−1.5V = −3.2V.

  FIG. 4 shows the potential distribution of the gate when the shift unit thyristor Tn is ignited. FIG. 5 shows a voltage waveform of the gate line VGA supplied to the gate, and a rectangular voltage having a period T supplied to the odd-numbered bit transfer line Φ1, the even-numbered bit transfer line Φ2, and the light emission signal line ΦI. The time during which both the odd-numbered bit transfer line Φ1 and the even-numbered bit transfer line Φ2 are at the low level is referred to as the overlap time, and this is represented by ta.

  If the voltage of the gate line VGA and the voltage supplied to the transfer lines Φ1, Φ2, and ΦI are −3.3V, only about 0.1V is applied between the gate and cathode of the shift unit thyristor Tn + 2. In order to turn on the thyristor, it is necessary that at least a voltage higher than the diffusion potential be applied between the gate and the cathode, and a current higher than the holding current flow between the cathode and the anode. For this reason, the shift unit thyristor Tn + 2 cannot be ignited. On the other hand, a reverse bias is applied to the diode Dn-1 on the left side of the gate Gn, so that the potential of the gate Gn-1 is about the voltage of the gate line VGA (about -3.3 V), so that the shift unit thyristor Tn- 1 cannot be turned on. Thus, when the odd bit transfer line Φ1 is −3.3V and the shift unit thyristor Tn is on, if the even bit transfer line Φ2 is lowered from 0V to −3.3V, only the adjacent shift unit thyristor Tn + 1 is present. Fire. Thereafter, when the odd-bit transfer line Φ1 is raised to 0V, the shift unit thyristor Tn is turned off, and the on-state transfer from the shift unit thyristor Tn to Tn + 1 becomes possible.

  When the shift unit thyristor Tn is on, the gate potential Gn is raised to the highest voltage. Therefore, when the odd-bit transfer line Φ1 is lowered from 0V to −3.3V, only the light emitting unit thyristor Ln is turned on to emit light. In other words, the row of the thyristor of the shift unit is sequentially transferred from the left to the right, and only the light-emitting unit thyristor of the bit in which the shift unit thyristor is in the ON state is input with the 0, 1 data input to the external emission signal line ΦI To determine whether to turn it on. As a result, the 0, 1 data is converted into light emitting or non-light emitting information.

  FIG. 1 is a plan view of an element array corresponding to the 4-bit element shown in FIG. The SLED is formed by epitaxially growing a semiconductor layer having a pnpn structure on a p-type GaAs semiconductor substrate so as to lattice match with the p-type GaAs semiconductor substrate. On the semiconductor substrate, islands or mesas corresponding to the respective elements are formed by etching the semiconductor layer. In FIG. 1, four islands Sn-1, Sn, Sn + 1, Sn + 2 are formed corresponding to the circuit of FIG. 3, and these islands Sn-1, Sn, Sn + 1, Sn + 2 are formed. Are arranged linearly. In one island, a light emitting thyristor Li, a shift thyristor Ti, and a parasitic thyristor PTi immediately below the coupling diode Di are formed.

  2A, 2B, and 2C show the light emitting unit thyristor Ln + 1, the shift unit thyristor Tn + 1, and the parasitic thyristor PTn + 2 immediately below the coupling diode Dn + 1 formed on the island Sn + 1. Each of the cross-sectional structures is shown. As shown in FIG. 2A, an anode layer 22 containing p-type AlGaAs having a predetermined film thickness and a predetermined dopant concentration, a predetermined film thickness and a predetermined dopant concentration are formed on a p-type GaAs substrate 20. A gate layer 24 made of n-type AlGaAs having a predetermined thickness, a gate layer 26 made of p-type AlGaAs having a predetermined dopant concentration, and an n-type GaAs having a predetermined thickness and a predetermined dopant concentration. A cathode layer 28L made of AlGaAs is formed. The island Sn + 1, that is, the mesa M, is processed into a rectangular shape by etching the semiconductor layer from the p-type gate layer 26 to a part of the anode layer 22 or the substrate 20, and the top layer of the island Sn + 1. Are separately separated in the light emitting unit thyristor Ln + 1, the shift unit thyristor Tn + 1, and the parasitic thyristor PTn + 2. The cathode layer 28L of the light emitting unit thyristor Ln + 1 is formed on the bottom side of the island Sn + 1, and a cathode electrode 32L electrically connected to the cathode layer 28L is formed on the cathode layer 28L. The cathode electrode 32L is preferably processed into a frame shape, and a rectangular light emission port 34 for emitting light is formed at the center of the cathode electrode 32L. A common anode electrode 40 that supplies a ground potential is formed on the back surface of the substrate 20.

  In the island Sn + 1, a current confinement layer 30 made of p-type AlAs or p-type AlGaAs having an Al composition ratio of, for example, 98% or more is inserted into a part of the anode layer 22. Preferably, the current confinement layer 30 is sandwiched in the anode layer 22 by an AlGaAs layer having a relatively small Al composition. Further, the Al composition of AlAs or AlGaAs constituting the current confinement layer 30 is significantly larger than the Al composition of the other semiconductor layers 24, 26, and 28L. In this way, when the current confinement layer 30 is oxidized, an oxidized region 30A and a non-oxidized region 30B that are selectively oxidized are formed in the current confinement layer 30. The oxidation of the current confinement layer 30 is performed using, for example, water vapor oxidation annealing, whereby a part of the current confinement layer 30 exposed on the side surface of the mesa M is oxidized. For example, when the current confinement layer 30 is oxidized from all the side surfaces of the rectangular mesa M shown in FIG. 1, oxidation proceeds from the side surface of the mesa M by a certain distance, and the oxidized region 30A reflecting the outer shape of the mesa M A non-oxidized region 30B surrounded by the oxidized region 30A is formed. A line K indicated by a broken line in each island represents a boundary between the oxidized region 30A and the non-oxidized region 30B.

  The non-oxidized region 30B overlaps immediately below the cathode layer 28L of the light emitting unit thyristor Ln. Here, the overlap means that the cathode layer 28L overlaps with the non-oxidized region 30B when the cathode layer 28L is projected from above the substrate. The cathode layer 28L may overlap with the whole non-oxidized region 30B and overlap with a part of the oxidized region 30A. However, preferably, the area ratio in which the cathode layer 28L and the non-oxidized region 30B overlap is larger than the area ratio in which the cathode layer 28L and the oxidized region 30A overlap. Since the oxidized region 30A is an electrically high-resistance region and the non-oxidized region 30B is a conductive region, carriers (holes) having a lower mobility than electrons injected from the anode electrode 40 are generated in the non-oxidized region 30B. And is injected into the n-type gate layer 24 in a high density state. As shown in FIG. 2A, by forming the oxidized region 30A on the outer periphery of the mesa M, the carriers are suppressed from being trapped in the surface level on the side surface of the mesa M, and the leakage current is suppressed. As a result, the recombination probability between holes and electrons in the gate layers 24 and 26 is increased, the luminous efficiency is improved, and high output can be achieved.

  As shown in FIG. 2B, the shift unit thyristor Tn + 1 shares the light emitting unit thyristor Ln + 1 and the semiconductor layers 22, 24, and 26, and the uppermost cathode layer 28T is the light emitting unit thyristor Ln + 1. It is separated from the cathode layer 28L. Here, the cathode layer 28T is formed in a rectangular shape substantially at the center of the island Sn + 1, and a rectangular cathode electrode 32T is formed on the cathode layer 28T. The non-oxidized region 30B of the current confinement layer 30 overlaps immediately below the cathode layer 28T, and more preferably, the oxidized region 30A is not formed immediately below the cathode layer 28T. If the oxidized region 30A is formed directly under the cathode layer 28T, the resistance between the anode and the cathode is increased, which is not preferable. For this reason, it is made to overlap with the non-oxidized region 30B so that the influence of the oxidized region 30A due to the current confinement layer 30 does not occur in the shift portion thyristor Tn + 1.

  The coupling diode Dn + 1 is formed on the island Sn + 1. As shown in FIG. 2C, the coupling diode Dn + 1 is constituted by a PN junction of the gate layer 26 and the cathode layer 28PT. The anode of the coupling diode Dn + 1 is connected to the gate Gn + 1 common to the light emitting unit thyristor Ln + 1 and the shift unit thyristor Tn + 1. An n-type gate layer 24 and a p-type anode layer 22 are further formed immediately below the coupling diode Dn + 1. A parasitic thyristor PTn + 2 having a pnpn structure is formed there. The oxidized region 30A overlaps immediately below the cathode layer 28PT of the parasitic thyristor PTn + 2, and more preferably, the oxidized region 30A completely overlaps immediately below the oxidized region 30A. By preventing a current path from being formed immediately below the cathode layer 28PT, the resistance of the parasitic thyristor PTn + 2 is increased so that the parasitic thyristor PTn + 2 cannot be easily ignited.

An odd-bit transfer line Φ1 is connected to the cathode electrode 32T of the shift unit thyristor of the odd-bit islands Sn and Sn + 2, and to the cathode electrode 32T of the shift-unit thyristor of the even-bit islands Sn-1 and Sn + 1. The even bit transfer line Φ2 is connected. A light emission signal line ΦI is connected to the cathode electrode 32L of the light emitting unit thyristor. An island SR connected to the gate line VGA is formed on the substrate. The gate line VGA is electrically connected to the p-type gate layer 26 of the island SR via the contact electrode CT, and the gate load resistance _RG is formed using the p-type gate layer 26. The output terminal of the gate load resistor _RG is connected to the common gate electrode via the contact CT1, and is connected to the cathode electrode 32PT of the adjacent coupling diode.

  The n-type cathode layer, which is the uppermost layer of the light emitting thyristor Li, the shift thyristor Ti, and the parasitic thyristor PTi, has a different size and a different distance from the side surface of the mesa where the current confinement layer 30 is exposed. Depending on the position of each thyristor, the area ratio of the current confinement layer 30 to the oxidized region 30A (the overlapping area ratio between the cathode layer and the oxidized region) differs. Preferably, the parasitic thyristor PTi is mostly overlapped with the oxidation region 30A immediately below the cathode layer, and in order for the parasitic thyristor PTi to turn on, the carriers must pass through a current path that bypasses the oxidation region 30A. As a result, the resistance value increases.

  On the other hand, in the shift portion thyristor Ti, since most of it does not overlap with the oxidized region 30A, preferably directly below the cathode layer, the switching structure thyristor Ti does not differ from the conventional structure without the current confinement layer 30 and there is no difference in switching operation. . Further, even if the light emitting portion thyristor Li is oxidized from the three side surfaces of the rectangular island, only the peripheral portion thereof directly overlaps with the oxidized region 30A immediately below the cathode layer, and the remaining central portion remains as the non-oxidized region 30B. As a result, there is no problem in the light emission operation, and carriers are concentrated in the center of the light emitting part due to the current confinement structure, so that non-radiative recombination at the interface state of the mesa side surface is suppressed, and the light emitting thyristor has a high level. Output is achieved.

  As described above, in this embodiment, by providing a current confinement structure in the island including the light emitting unit thyristor Li, the shift unit thyristor Ti, and the coupling diode Di, the parasitic diode directly below the cathode of the coupling diode unit without changing the self-scanning function. By increasing the time constant of the cathode potential drop of the thyristor, it is possible to prevent the parasitic thyristor from firing during self-scanning, and at the same time, without increasing the switching speed of the shift thyristor, Output can be achieved.

  In the above example, the current confinement layer is oxidized from the four sides of the rectangular mesa M. However, the present invention is not limited to this, and other oxidations may be used. FIG. 6 illustrates one island Si including the light emitting thyristor Li, the shift thyristor Ti, and the parasitic thyristor PTi. FIG. 6A shows that the current confinement layer 30 is oxidized from only one side surface 50 of the island Si. An example is shown. When the distance from the edge of the cathode layer of the parasitic thyristor PTi to the side surface 50 is d1, and the distance from the edge of the cathode layer of the shift thyristor Ti to the side surface 50 is d2, the oxidation distance D from the side surface 50 of the oxidation region 30A is , D1 <D ≦ d2, more preferably D≈d2. As a result, the on-resistance of the parasitic thyristor PTi can be increased, while the switching speed can be maintained without increasing the on-resistance of the shift unit thyristor Ti. Further, even in the light emitting unit thyristor Li, trapping of carriers that do not contribute to light emission on the side surface 50 is suppressed.

  FIG. 6B shows an example in which the current confinement layer 30 is oxidized simultaneously from two opposing side surfaces 50 and 52 of the island Si. Also in this case, preferably, the oxidation distance D of the oxidation region 30A is less than or equal to the distance d2 (D ≦ d2) of the cathode layer of the shift portion thyristor Ti. The oxidation time can be shortened by simultaneous oxidation. Further, in the light emitting unit thyristor Li, carriers can be confined in the center as compared with the case of FIG.

  FIG. 6C shows an example in which the current confinement layer 30 is oxidized from the upper side surface 54 of the island S1. When the distance from the edge of the cathode layer to the side surface 54 of the parasitic thyristor PTi is d1, and the width in the direction extending to the side surface 50 of the cathode layer is d3, the oxidation distance D from the side surface 54 of the oxidized region 30A is D ≧ d1 + d3. It is desirable to be. Thereby, the on-resistance of the parasitic thyristor PTi can be increased.

  FIG. 6D shows an example in which the current confinement layer 30 is oxidized from two sides of the side surface 56 facing the side surface 54 of the island Si. In this case, the oxidation distance D of the oxidation region 30A is at least larger than the distance d1 from the edge of the cathode layer of the parasitic thyristor PTi to the side surface 54. On the other hand, since the oxidized region 30A is formed from the side surface 58 toward the light emitting thyristor Li, the upper limit of the oxidation distance D is that the light output of the light emitting unit thyristor Li is higher than that when the current confinement layer 30 is not formed. It is determined within the range of improvement.

  Further, although not shown here, oxidation may be simultaneously performed from three side surfaces of the island Si. For example, oxidation may be performed simultaneously from the side surfaces 50, 52, and 54. When the current confinement layer 30 is oxidized, the current confinement layer 30 needs to be exposed on the side surface of the mesa M. Therefore, the mesa M needs to be etched to a depth reaching the current confinement layer 30 on the side surface to be oxidized.

  In the above example, the current confinement layer 30 is formed in the anode layer 22. However, the current confinement layer 30 may be formed at a different position. For example, it may be formed at the boundary between the n-type gate layer 24 and the anode layer 22. Furthermore, in this embodiment, the planar shape of the island Si is rectangular, but this is only an example, and other shapes such as a circular shape, an elliptical shape, a trapezoidal shape, and other polygonal shapes may be used.

  Next, a second embodiment of the present invention will be described. In the first embodiment, the current confinement layer is oxidized from the side surface of the island (mesa). However, in the second embodiment, an etching groove is formed in the vicinity of the parasitic thyristor, so that the anode of the parasitic thyristor is formed. -A high resistance region is formed between the cathodes.

  FIG. 7A shows a plan view of one island used in the SLED according to the second embodiment, and FIG. 7B is a cross-sectional view taken along the line BB. In the second embodiment, one elongated groove 60 is formed from the side surface 50 toward the inside in the island Si having the light emitting unit thyristor Li, the shift unit thyristor Ti, and the parasitic thyristor PTi. The groove 60 extends adjacent to and substantially parallel to the cathode layer 28PT of the parasitic thyristor PTi, and more preferably, the distance from the side surface 50 of the cathode layer 28PT of the parasitic thyristor PTi is d4. Has a length equal to or greater than d4. As shown in FIG. 7B, the groove 60 is formed by etching the semiconductor layer up to at least the current confinement layer 30.

  In the second embodiment, the island Si is selectively oxidized using at least the groove 60. By this oxidation, the current confinement layer 30 is oxidized from the groove 60 toward the inside. The oxidation region 30A has a rectangular shape as indicated by the broken line K in FIG. 7A, and the oxidation region 30A is formed entirely under the cathode layer of the parasitic thyristor PTi by appropriately selecting the oxidation time. Is done. As a result, almost the entire current path between the anode and cathode of the parasitic thyristor PTi is blocked by the oxidation region 30A, so that the on-resistance of the parasitic thyristor PTi increases. In the second embodiment, the oxidation of the island Si may be simultaneously performed from the groove 60 and the side surface 54 facing the groove 60, thereby shortening the oxidation time. Further, this does not prevent oxidation from the side surfaces 50, 52, and 56 of the island Si on which the light emitting portion thyristor Li is formed.

  Next, a third embodiment of the present invention will be described. In the structures of the first and second embodiments, the anode electrode of the coupling diode Di and the gate electrode of the shift unit thyristor and the light emitting unit thyristor are shared, but in the third embodiment, the anode electrode and the gate electrode are combined. To separate.

  FIG. 8 shows a plan view of one island used in the SLED according to the third embodiment. As shown in the figure, the island Si is substantially separated into two islands Sia and Sib by a groove 62. The groove 62 is formed by etching so as to have a depth that reaches at least the current confinement layer 30. On one island Sia, a coupling diode Di is formed, and an anode electrode 64 of the coupling diode is connected to the gate Gi. On the other island Sib, a shift portion thyristor Ti and a light emitting portion thyristor Li are formed, a common gate electrode 66 is formed thereon, and the gate electrode 66 is connected to the anode electrode 64.

  In the third embodiment, the entire current confinement layer 30 on the island Sia is oxidized. This oxidation may be performed from the groove 62 or may be performed simultaneously from the four side surfaces of the island Sia. Further, the current confinement layer 30 of the island Sib may be oxidized by a certain distance from the outer periphery of the island Sib. In this case, in the shift thyristor Ti, as in the first embodiment, the cathode layer The current confinement layer 30 directly below is a non-oxidized region, and a part of the periphery of the island Sib is oxidized in the light emitting unit thyristor Li. According to the third embodiment, since the pnpn structure formed immediately below the cathode electrode 70 of the coupling diode Di of the island Sia is completely cut off by the oxidized region 30A of the current confinement layer 30, this parasitic thyristor PTi. Will never turn on.

  Next, the on condition of the parasitic thyristor PTi will be examined. As shown in FIG. 1, when the shift unit thyristor Tn, the light emitting unit thyristor Ln, and the coupling diode Dn are formed in the island of the same gate, and the coupling diode Dn is composed of a pn junction at the top of the thyristor structure pnpn, A parasitic thyristor PTn + 1 is formed immediately below the cathode electrode of the coupling diode Dn. The parasitic thyristor PTn + 1 is originally an element that is not necessary for the transfer function, but may be turned on depending on the voltage values of the gates Gn and Gn + 1.

Therefore, next, consider the on-condition of the parasitic thyristor PTi. Since Gn + 1−Gn≈−1.5 V (diffusion potential), all thyristors PTi can be ignited with respect to voltage values. However, for ignition, a current greater than the holding current must flow as shown in FIG. Here, when Φ1 = Φ2 = ΦI = VGA = −3.3V and the shift unit thyristor Tn is on, the gate Gn = −0.2V and Gn + 1 = −1.7V. At this time, the parasitic thyristor PTn + 1 can be fired at the gate load resistance RG = 15 kΩ from the result of the operating point analysis of FIG. When the thyristor PTn + 1 is ignited, its cathode potential Gn + 1 is raised to -1.5V. Since the adjacent parasitic thyristor PTn + 2 has a gate potential of −1.5 V, it is considered that it cannot be ignited from the result of the operating point analysis of FIG. 10 (from the region below the threshold current value I _BO). Cannot transition to straight line part). In the figure, Vn + 1 and Vn + 2 are the cathode-anode voltages of the parasitic thyristors PTn + 1 and PTn + 2, respectively, and In + 1 and In + 2 are the currents flowing through them. It is the current that flows in the direction indicated by the dashed arrow.

  The ON / OFF speed of the shift unit thyristor Ti affects the SLED transfer speed. The ON / OFF speed is determined by the time from when the ON signal is received until the cathode potential of the thyristor drops to a level that can be fired. The time constant of the transient characteristics depends on the resistance value and capacitance on the circuit. Determined. Therefore, in order to improve the transfer speed, for example, it is conceivable to lower the gate load resistance RG in the current path of FIG.

However, when the gate load resistance R _G is lowered to R _{G ′} , the operating point is located in the current value greater than the holding current or in the negative resistance region as shown in the operating point analysis of FIG. 11, and the thyristor PTn. +2 will turn ON. In the ON state, the gate Gn + 2 is pulled up to about the diffusion potential of about −1.5 V, so that Tn + 2 adjacent to the two shift unit thyristors Tn that are on also satisfies the on condition. The same thing happens for Tn + 2m (m is an integer) connected to the same transfer line, and the self-scanning function in which only the thyristor adjacent to the shift unit thyristor that is turned on satisfies the on condition cannot be developed. For this reason, if the gate load resistance value _RG is lowered to improve the speed, a transfer failure may occur.

  When the shift unit thyristor Tn is turned on, the possibility that the two adjacent shift unit thyristors Tn + 2 are also turned on is that the parasitic thyristor PTn + 2 is turned on. Consider preventing this. First, consider the time variation of the cathode potential when the shift unit thyristor Tn + 1 is turned on. FIG. 12 shows the relationship between the cathode potential and the change with time. When the gate potential is -1.5V, the thyristor can be ignited by setting the cathode potential to -3.0V or more, provided that the moment when the cathode potential reaches -3.0V is the previous shift unit thyristor Tn. Is in the ON state, and the gate potential of the shift unit thyristor Tn + 1 must be in the overlap time ta where the gate potential is kept at -1.5 V (see FIG. 12). Whether the cathode potential reaches −3.0 V within the overlap time ta depends on the time constant of the cathode potential drop and the voltage value applied outside the resistor RI. In order to prevent the parasitic thyristor PTn + 2 from transitioning to the ON state, the time constant of the cathode potential drop of the thyristor PTi existing immediately below the cathode electrode of the coupling diode Di is increased, that is, the on-resistance of this thyristor. Increase However, when a resistor is inserted in series with the parasitic thyristor PTi, it must be inserted somewhere in the row of coupled diodes in FIG. 1, but a space is provided for arranging a resistor through which a current flows in the lateral direction. It is difficult. On the other hand, it is conceivable to change the epitaxial configuration and increase the resistance value. However, if this is done, the on-resistance of the light emitting unit thyristor will increase, and the voltage value for obtaining the same amount of light will increase. This is not preferable because power consumption increases.

  The pnpn regions (where the n-type top layer is present) of the light emitting thyristor Li, the shift thyristor Ti, and the parasitic thyristor PTi are different in size, and the distance from the mesa surface where the current confinement layer is exposed. Therefore, in each thyristor Li, Ti, PTi, the ratio of the oxidized area of the current confinement layer to the cathode layer is different. Since most of the pnpn structure of the parasitic thyristor PTi is covered by the oxidized region 30A, in order for this to turn on, carriers must pass through a current path that bypasses the oxidized region 30A. The resistance value increases accordingly.

Thus, in this embodiment, when the gate load resistance _RG is decreased to improve the transfer operation speed, the shift unit thyristor cannot be sequentially fired, that is, when the shift unit thyristor Tn is on, only Tn + 1 is required. In addition, it is possible to solve the problem that the two adjacent shift unit thyristors Tn + 2 may be turned on.

  The self-scanning light emitting element array as described above is used, for example, in an optical writing head of an optical printer. FIG. 13 shows an example of an optical writing head using a self-scanning light emitting element array. A plurality of light emitting element array chips 71 in which light emitting thyristors are arranged in a row on a chip mounting substrate 70 are mounted in the main scanning direction, and on the optical path of light emitted by the light emitting elements of the light emitting element array chip 71, An erecting equal-magnification rod lens array 72 that is long in the main scanning direction is fixed by a resin housing 73. A photosensitive drum 74 is provided on the optical axis of the rod lens array 72. Further, a heat sink 75 for releasing heat of the light emitting element array chip 71 is provided on the base of the chip mounting substrate 70, and the housing 73 and the heat sink 75 are fixed by a fastener 76 with the chip mounting substrate 70 interposed therebetween. ing.

  FIG. 14 shows an optical printer using the optical writing head shown in FIG. An optical writing head 100 is installed in the optical printer. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 102. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged by the charger 104. Then, the optical writing head 100 irradiates the photosensitive member with the light of the dot image to be printed, neutralizes the charge where the light hits, and forms a latent image. Subsequently, the developing device 106 applies toner to the photoconductor according to the charged state on the photoconductor. The transfer device 108 transfers the toner onto the paper 112 sent from the cassette 110. The sheet is heated and fixed by the fixing device 114 and sent to the stacker 116. On the other hand, the drum that has been transferred is neutralized by the erasing lamp 118 over the entire surface, and the remaining toner is removed by the cleaner 120. Such an optical writing head can be used not only for a printer but also for an image forming apparatus such as a facsimile machine and a copying machine.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims. Deformation / change is possible.

10: SLED
20: Semiconductor substrate 22: p-type anode layer 24: n-type semiconductor layer (gate layer)
26: p-type semiconductor layer (gate layer)
28L, 28T, 28PT: cathode layer 30: current confinement layer 30A: oxidized region 30B: non-oxidized regions 32L, 32T, 32PT: cathode electrode 34: light exit port 36: gate electrode 40: anode electrodes 50, 52, 54, 56 : Side surface 60, 62: Groove
Li: Light emitting unit thyristor
Ti: Shift thyristor
PTi: Parasitic thyristor
Di: Coupling diode K: Boundary between oxidized region and non-oxidized region

Claims (4)

A light emitting unit thyristor and a shift unit thyristor are provided in a semiconductor laminated structure including a current confinement layer,
The light emitting unit thyristor has a current confinement structure formed by oxidizing the current confinement layer from a side surface of the stacked structure,
The shift unit thyristor is a self-scanning light emitting element array in which a region of the current confinement layer located between an anode and a cathode of the shift unit thyristor is formed at a position not oxidized by the oxidation. The self-scanning light-emitting element array according to claim 1, wherein the shift unit thyristor is formed at a position farther from a side surface of the stacked structure than the light-emitting unit thyristor. An optical writing head using the self-scanning light emitting element array according to claim 1. An image forming apparatus comprising the optical writing head according to claim 3.

Images