JP4367191B2 - Self-scanning light emitting device array - Google Patents

Description

  The present invention relates to a self-scanning light-emitting element array, and more particularly to a self-scanning light-emitting element array that can be used in an optical printer or the like to enable high definition.

  The basic electric circuit of the self-scanning light emitting element array is disclosed in Patent Document 1 and Patent Document 2. The self-scanning light emitting element arrays described in these documents use a three-terminal light emitting thyristor having a PNPN structure.

  In the circuit configuration of the self-scanning light-emitting element array disclosed in Patent Document 1, resistance coupling is used as a coupling method between the transfer thyristors. Therefore, at least three transfer clock lines are required. In the self-scanning light-emitting element array disclosed in Fig. 2, the coupling method between transfer thyristors is changed to diode coupling, thereby reducing the minimum number of transfer clock lines to two and simplifying the circuit configuration. Realized.

FIG. 1 shows a part of an equivalent circuit of a self-scanning light-emitting element array disclosed in Patent Document 2 and a part of a pattern on an upper surface of the self-scanning light-emitting element array chip. As shown in FIG. 1A, the gate electrode G of the transfer thyristor T is coupled by a diode D. L indicates a light emitting unit thyristor, and RL indicates a gate load resistance. The gate load resistor is connected to the power supply voltage _VGA line. The cathodes of the transfer thyristors T are alternately connected to the transfer clock pulse φ1 and φ2 lines.

  The transfer thyristor T and the light emitting unit thyristor L are configured by using a three-terminal thyristor having a PNPN structure, and the pattern configuration on the chip upper surface is as shown in FIG. In FIG. 1B, portions corresponding to the elements shown in FIG. 1A are denoted by the symbols used in FIG.

The diode D is manufactured using the upper two layers of the PNPN structure, and the cathode electrode 6 and the anode electrode 8 appear on the upper surface. The cathode electrode 6 of one adjacent diode D, the anode electrode 8 of the other diode D, and the gate electrode G of the transfer thyristor are connected by an Al wiring 10 through a contact hole opened above each. . The shape of the Al wiring is Z-shaped as can be seen from the figure.
Japanese Patent Laid-Open No. 1-238962 “Light Emitting Element Array and Driving Method thereof” Japanese Patent Laid-Open No. 2-14584 “Light Emitting Element Array”

  The conventional self-scanning light emitting element array shown in FIG. 1 has the following problems. That is, when the self-scanning light emitting element array is used for an optical printer or the like, the light emitting point (light emitting portion thyristor) pitch is being miniaturized, for example, 2400 dpi, for the purpose of high-definition image printing. Therefore, the width of one light emitting unit thyristor in the transfer direction of the light emitting unit thyristor, that is, the main scanning direction (chip long side direction) must be reduced. On the other hand, in order to reduce the manufacturing cost of the self-scanning light emitting element array chip, the chip size in the direction perpendicular to the main scanning direction, that is, the length in the sub-scanning direction (the short side length of the chip) must be reduced. It is coming.

In the conventional diode-coupled self-scanning light-emitting element array shown in FIG. 1, the diodes D must be arranged in the main scanning direction, and the cathode electrode 6 and the anode electrode 8 are arranged in the main scanning direction. Therefore, there is a limit to reducing the chip size in the main scanning direction. In other words, from the viewpoint of patterning technology, in order to fabricate an element using a conventional wet etching technology, there is no margin between designed patterns in consideration of side etching during wet etching. Furthermore, in order to increase the reliability of long-term operation, conditions such as completely covering the contact holes opened on the anode and cathode of the diode with Al wiring must be satisfied. More specifically, the size of one side of the contact hole should be at least 2 μm, the distance between the contact hole edge and the Al wiring edge should be 3 μm or more, and the variation of alignment should be taken into consideration such as ± 1 μm. is there. Therefore, in order to employ a configuration in which the diodes are arranged side by side in the main scanning direction, the use of a resolution of 1200 dpi with a light emitting point pitch of 21.15 μm in the main scanning direction is the limit that can be produced by the conventional technology. For this reason, in order to further increase the resolution, for example, 2400 dpi or the like, a device on an electric circuit or a layout pattern is required.

  In addition, although an Au electrode is generally used as the electrode of the self-scanning light emitting element array, the Au—Al alloy formed at the contact portion of the Au electrode and the Al wiring is likely to cause a failure of the electrical circuit opening. It has become clear that there is a need to reduce the number of Au-Al junctions.

  The present invention has been made paying attention to such a conventional problem, and its purpose is to make the length in the main scanning direction (long side length of the chip) equal to that of the current 1200 dpi chip, that is, the current chip. It is an object of the present invention to provide a structure of a self-scanning light-emitting element array that can easily manufacture a chip with higher resolution (for example, 2400 dpi) without increasing the size.

  Another object of the present invention is to provide a structure of a self-scanning light-emitting element array that can further reduce the length in the sub-scanning direction (the short side length of the chip).

  Still another object of the present invention is to provide a self-scanning light-emitting element array having a structure in which the number of contact portions is reduced in order to reduce the opening failure of the contact hole portions.

  The present invention relates to a self-scanning light-emitting element array using a PNPN-structured three-terminal light-emitting thyristor, a transfer section in which a plurality of three-terminal light-emitting thyristors for transfer are arranged in the main scanning direction, and a plurality of light-emitting three A light emitting section having terminal light emitting thyristors arranged in the main scanning direction and each gate connected to a gate of a plurality of corresponding three terminal light emitting thyristors for transfer, and adjacent light emission of the plurality of arranged light emitting thyristors. The gates of the thyristors are connected by alternately using coupling diodes and coupling resistors.

  Further, the cathodes or anodes of the plurality of light emitting thyristors in the transfer unit are alternately connected with two-phase clock pulse lines, the gates are connected to a power source through load resistors, and the cathodes or anodes of the plurality of light emitting thyristors in the light emitting unit are connected. The anode is connected to the light emission signal line.

  According to the present invention, the coupling diode is formed from the upper two semiconductor layers of the PNPN structure, and the coupling resistor is formed from the second semiconductor layer from the top of the PNPN structure.

  According to the present invention, in the above configuration, each gate electrode of a light emitting thyristor for transfer is formed on each of a plurality of islands formed by etching, and a coupling diode is formed on every other island. The gate electrode on the island where the coupling diode is formed is a dummy gate electrode, and the coupling resistor is formed between the island where the dummy gate electrode is located and the previous island of this island. It is characterized by that.

  In the present invention, the gate electrode of every other light emitting thyristor for transfer is formed every other plurality of islands formed by etching, and a coupling diode is formed on the remaining islands. The coupling resistor is formed between an island having the coupling diode and an island in front of the island, and the gate electrode and the coupling diode are arranged in the main scanning direction.

  According to the present invention, a self-scanning light-emitting element array can be realized in which the length in the main scanning direction, and further the length in the sub-scanning direction can be shortened compared to the conventional one, and thus high resolution can be achieved. it can. Further, since the number of contact portions can be reduced, it is possible to reduce the open failure of the contact hole portion.

  Examples of the self-scanning light emitting element array of the present invention will be described. In the following embodiments, a case of an anode common type self-scanning light emitting element array will be described, but the present invention can also be applied to a cathode common type self-scanning light emitting element array.

FIG. 2 is a diagram showing a part of an equivalent circuit of a self-scanning light emitting element array according to an embodiment of the present invention. In the figure, T (−2) to T (+3) indicate transfer thyristors, and L (−2) to L (+3) indicate light emitting unit thyristors. These thyristors are arranged in a line in the main scanning direction. G (−2) to G (+3) denote the gates of the transfer thyristors T (−2) to T (+3). RL indicates the load resistance of the gate electrode of the transfer thyristor, D (−2), D (0), and D (+2) are diodes that couple the gates, and R (−1), R (+1), and R ( +3) indicates a resistance for coupling between the gates. V _GA indicates a power supply voltage. Two transfer clock pulse φ1 and φ2 lines are connected to every other element to the cathode electrode of each transfer thyristor. The cathode of the light emitting unit thyristor is connected to the light emission signal phi _I lines. φ _S is a start pulse.

  As is apparent from the above configuration, the gates of the transfer thyristors are alternately coupled by diodes and resistors.

The operation will be described assuming that the power supply voltage _VGA is -5V. First, it is assumed that the transfer clock pulse φ2 is at a low level (L level) and the transfer thyristor T (0) is ON. At this time, due to the characteristics of the three-terminal thyristor, the gate G (0) is pulled up to near zero volts. Since the V _GA is set to -5V, the resistor RL, the coupling diode ..., D (-2), D (0), D (+2), ..., and the coupling resistor ..., R (-1), R (+1 ), R (+3),..., The gate voltage of each transfer thyristor is determined.

When the next transfer clock pulse φ1 is set to the L level, it is applied to the thyristors T (+1), T (−1), T (+3), T (−3), etc. adjacent to the thyristor T (0). However, the thyristor with the lowest ON voltage under certain conditions can be T (+1). The reason is as follows. Considering the gate voltages of thyristors T (−1) and T (+1) closest to thyristor T (0), the gate G (−1) has R (−1) / (RL + R (−1)) × V. _When the ON voltage of the coupling diode D (0) is VD (0), the voltage of −VD (0) is applied to the gate G (+1). R (n-1) / (RL + R (n-1)) × | V _GA |> | VD (n) |
n = 0, ± 2, ± 4, ... (1)
If the resistance value of the resistor R (−1) is set so as to satisfy the above, the thyristor T (+1) is preferentially turned on in the comparison between the transfer thyristor T (−1) and T (+1). . In the above equation (1), R (n-1) represents the resistance value of the resistor R (n-1), and RL represents the resistance value of the load resistor RL.

  The gate voltage of the transfer thyristor arranged in the right direction from the transfer thyristor T (+1) gradually decreases depending on the voltage drop due to the coupling resistor and the ON voltage of the coupling diode. On the other hand, to the left of the transfer thyristor T (-1), the effect of increasing the voltage does not work due to the unidirectionality and asymmetry of the diode characteristics of the coupling diode, and the gate of the transfer thyristor connected to the φ1 line. A voltage approximately equal to the power supply voltage of −5 V is applied to the capacitor.

That is, if the resistance of R (−1) is set so that R (−1) / (RL + R (−1)) × | V _GA |> | VD (0) |, it is connected to the φ1 line. Among the transfer thyristors, the voltage applied to the gate of the thyristor T (+1) is the highest, and the ON voltage is the lowest. Accordingly, when the clock pulse φ1 is set to L level when the thyristor T (0) is in the ON state, the thyristor T (1) on the right side is always turned on, and the transfer operation can be performed.

Next, consider a case where the thyristor T (+1) is ON. As described above, the gate G (+1) is pulled up to near zero volts due to the characteristics of the three-terminal thyristor. Since the V _GA is set to -5V, the load resistor RL, the coupling diode ..., D (-2), D (0), D (+2), ..., and the coupling resistor R ..., (- 1), R ( +1), R (+3),..., The gate voltage of each transfer thyristor is determined.

  When the next transfer clock pulse φ2 is set to L level, it is applied to thyristors T (0), T (+2), T (−2), T (+4) and the like adjacent to thyristor T (+1). The element having the lowest ON voltage under a certain condition can be the thyristor T (+2). The reason is as follows. As the thyristor T (+1) that is currently turned on moves to the right, the gate voltage of the transfer thyristor gradually decreases depending on the voltage drop due to the coupling resistor and the ON voltage of the coupling diode. . On the other hand, in the left direction of the thyristor T (+1), there is no effect of increasing the voltage due to the unidirectionality and asymmetry of the diode characteristics of the coupling diode, and the gate of the transfer thyristor connected to the φ2 line is A voltage approximately equal to the power supply voltage of −5 V is applied. That is, among the transfer thyristors connected to the φ2 line, the voltage applied to the gate of the thyristor T (+2) is the highest and the ON voltage is the lowest. Therefore, if the clock pulse φ2 is set to L level when the thyristor T (+1) is ON, the thyristor T (+2) on the right side is always turned ON. In this case, if the resistance value of the coupling resistor R (+1) is too large, the ON voltage of the thyristor T (+2) becomes high. Therefore, a small resistance value is selected with R (n) satisfying the expression (1). This is necessary in order not to increase the operating voltage.

  From the above, in the self-scanning light emitting element array in which the gates of the transfer thyristors are alternately connected by diodes and resistors, the clock pulses φ1 and φ2 are alternately set to the L level to transfer the thyristors in a fixed direction. It can be operated.

  FIG. 3 shows a top view of a self-scanning light emitting element array chip manufactured based on the equivalent circuit shown in FIG. Portions corresponding to the elements shown in FIG. 2 are shown with the symbols used in FIG.

  Since the transfer thyristor and the light emitting unit thyristor of the self-scanning light emitting element array of this embodiment are manufactured using the PNPN structure, the coupling thyristor and the coupling resistance, and the load resistance use a part of the PNPN structure. Are made.

  The load resistor RL and the coupling resistors R (−1) and R (+1) are formed using the second P-type semiconductor layer from the top of the PNPN structure. The coupling diodes D (−2), D (0), and D (+2) are formed using N-type and P-type semiconductor layers in the upper two layers of the PNPN structure. The coupling diode is made of an element in which a cathode electrode is formed on a cathode-etched island in order to create an inspection signal and a self-scanning light emitting element array. As can be seen from FIG. 3, every other coupling diode is formed on the island.

  On the other hand, the coupling resistor is formed between an island where the coupling diode is not formed and an island where the coupling diode is formed. Such a resistor can be created simultaneously when the island is etched.

  In the figure, reference numeral 12 denotes an Al wiring connecting the cathode electrode 6 of the diode and the gate electrode of the transfer thyristor. The shape of the Al wiring 12 is rectangular.

  In this embodiment, the gate electrode is formed on each island as in the conventional pattern shown in FIG. 1. However, the gate electrode is actually made to function on the island where the coupling diode is not formed. Only the gate electrode. Therefore, the gate electrode of the island where the coupling diode is manufactured is a dummy. In FIG. 3, this dummy gate electrode is indicated by 14. Therefore, the dummy gate electrode may not be provided.

  A semiconductor resistor exists between the gate electrode and the light emitting unit thyristor. Since this semiconductor resistance is inserted in series with the load resistance RL, the gate electrode may be extended to the transfer unit thyristor side in order to reduce the semiconductor resistance. Thus, the gate electrode also has a function of adjusting the semiconductor resistance.

  According to the self-scanning light-emitting element array chip of this embodiment, the number of coupling diodes can be halved compared to the conventional chip shown in FIG. 1, and only the cathode electrode is the electrode of the coupling diode. The size of the diode portion in the main scanning direction should be smaller than that of the conventional diode pattern shown in FIG. 1 where the cathode and anode electrodes are arranged in the main scanning direction in the coupling diode portion. Can do. Therefore, the chip size in the main scanning direction can be reduced as a whole. Since the shape of the Al wiring is rectangular unlike the Z shape of the Al wiring in FIG. 1, it is possible to cope with a reduction in the element width in the main scanning direction with a margin.

  According to the present embodiment, the gate coupling diode portion of the thyristor can be simplified in terms of pattern, so that the margin between the designed patterns is significantly increased.

  In addition, according to this embodiment, as described above, the number of coupling diodes can be reduced by half compared to the conventional self-scanning light emitting element array, and only the cathode electrode is formed as the electrode of the coupling diode. Therefore, the number of electrodes of the coupling diode is reduced to ¼ compared with the conventional one. In addition, the number of gate electrodes is reduced to ½ compared to the conventional one. Therefore, in the self-scanning light-emitting element array of this embodiment, the number of coupling portions between the Au electrode and the Al wiring is reduced, so that it is possible to reduce failures due to the electrical circuit opening due to the Au—Al alloy.

  In FIG. 4, the dummy gate electrode 14 in FIG. 3 is omitted, and the gate electrodes G (−1) and G (+1) and the cathode electrodes of the coupling diodes D (0) and D (+2) are subjected to main scanning. They are arranged in the direction. By adopting this pattern, the chip short side length can be reduced by 15 μm as compared with Example 2, and the chip area can be reduced, that is, the cost can be reduced.

  With the structure of this example, the 2400 dpi self-scanning light emitting element array could be designed with a margin in the pattern. In addition, a self-scanning light-emitting element array could be produced without any problem without changing the conventional 1200 dpi patterning conditions, and the transfer operation could be confirmed.

  An optical head for an optical printer is configured by arranging a plurality of self-scanning light emitting element array chips described in the first and second embodiments, and an optical printer using such an optical printer head will be described. FIG. 5 shows a configuration of an optical printer including the optical printer head 40. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 42. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged with the electric charge 44. Then, the optical printer head 40 irradiates the photosensitive member with the light of the dot image to be printed, and neutralizes the charging where the light hits. Subsequently, the developing unit 48 applies toner to the photoconductor according to the charged state on the photoconductor. Then, the toner is transferred onto the paper 54 sent from the cassette 52 by the transfer device 50. The sheet is heated and fixed by the fixing device 46 and sent to the stacker 58. On the other hand, the drum after the transfer is neutralized by the erasing lamp 60 over the entire surface, and the toner remaining on the cleaner 62 is removed.

It is a figure which shows a part of equivalent circuit of the conventional self-scanning light emitting element array, and a part of pattern of the upper surface of a self-scanning light emitting element array chip | tip. It is a figure which shows a part of equivalent circuit of the self-scanning light emitting element array which is one Example of this invention. FIG. 3 is a top view of a self-scanning light emitting element array chip manufactured based on the equivalent circuit shown in FIG. 2. It is a top view of the self-scanning light emitting element array chip of another configuration. It is a figure which shows the structure of an optical printer.

Explanation of symbols

T transfer thyristor L light emitting unit thyristor RL load resistance G gate electrode D diode V _GA power supply voltage φ1, φ2 clock pulse φ _I light emission signal 6 cathode electrode 8 anode electrode 10, 12 Al wiring

Claims (8)

In a self-scanning light emitting element array using a PNPN structure three-terminal light emitting thyristor,
A transfer unit in which a plurality of three-terminal light-emitting thyristors for transfer are arranged in the main scanning direction;
A plurality of three-terminal light-emitting thyristors for light emission arranged in the main scanning direction, and a light-emitting unit in which each gate is connected to the gate of the corresponding plurality of three-terminal light-emitting thyristors for transfer,
A self-scanning light-emitting element array, wherein gates of adjacent light-emitting thyristors of the plurality of light-emitting thyristors arranged are connected by alternately using coupling diodes and coupling resistors. The cathodes or anodes of the plurality of light emitting thyristors of the transfer unit are alternately connected to two-phase clock pulse lines, and the gate is connected to a power source through a load resistor,
2. The self-scanning light-emitting element array according to claim 1, wherein cathodes or anodes of a plurality of light-emitting thyristors of the light-emitting unit are connected to a light-emitting signal line. When the nth light emitting thyristor is turned on among the plurality of light emitting thyristors of the transfer unit, the resistance value R (n−1) of the (n−1) th coupling resistor is:
R (n-1) / (RL + R (n-1)) × | V _GA |> | VD (n) |
However, n = 0, ± 2, ± 4, ...
RL is the resistance value of the load resistor,
V _GA is the voltage of the power source,
VD (n) is the ON voltage of the nth coupling diode,
The self-scanning light-emitting element array according to claim 2, wherein the self-scanning light-emitting element array is selected so as to satisfy. The coupling diode is formed of two upper semiconductor layers of the PNPN structure,
4. The self-scanning light emitting element array according to claim 1, wherein the coupling resistor is formed of a second semiconductor layer from the top of the PNPN structure. Each of the plurality of islands formed by etching is formed with each gate electrode of the light emitting thyristor for transfer,
The coupling diode is formed on every other island, and the gate electrode on the island where the coupling diode is formed is a dummy gate electrode,
5. The self-scanning light-emitting element array according to claim 4, wherein the coupling resistor is formed between an island having the dummy gate electrode and an island preceding the island. A gate electrode of every other light emitting thyristor for transfer is formed on every other island formed by etching,
The coupling diode is formed on the remaining island,
The coupling resistor is formed between an island having the coupling diode and an island in front of the island,
The self-scanning light-emitting element array according to claim 4, wherein the gate electrode and the coupling diode are arranged in a main scanning direction. An optical printer head comprising the self-scanning light emitting element array according to claim 1. An optical printer comprising the optical printer head according to claim 7.

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