JPH11330541A - End face light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an end face light emitting element which raises the light takeout efficiency and increases the quantity of emitted light. SOLUTION: This element is provided with a p-type semiconductor layer 31 in the region far from a light emission end face 38 besides being between an n-type semiconductor substrate 30 and an n-type semiconductor layer 32. When forward voltage is applied between an anode electrode and a cathode electrode, the pn junction between a p-type semiconductor layer 31 and an n-type semiconductor layer 32 is biased reversely, consequently the current can not flow in this pn junction. Accordingly, the inrush current from an anode electrode 36 flows concentrically near the light emission end face 38. As a result, the center of light emission comes close to the light emission end face 38, consequently the light takeout efficiency improves, and the quantity of emitted light increases.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an edge light emitting device, and more particularly to an edge light emitting device having a high light extraction efficiency.

[0002]

2. Description of the Related Art An edge light emitting element is advantageous in terms of high density because it does not have a light emitting portion from which light output is taken out and an electrode on the same surface, and is suitable for a light source (optical print head) of an optical printer or the like. ing.

FIG. 1 shows the principle of an optical printer having an optical print head. A photoconductive material (photoconductor) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 2. This drum rotates at the speed of the print. The surface of the photosensitive member of the rotating drum is uniformly charged by the charger 4. Then, light of a dot image to be printed is irradiated onto the photoreceptor by the optical print head 6 to neutralize the charging at the place where the light is applied. Subsequently, toner is applied to the photoconductor by the developing device 8 according to the charged state on the photoconductor. Then, the transfer device 10 transfers the toner onto the paper 14 sent from the cassette 12. The paper is fixed by applying heat or the like in a fixing device 16 and sent to a stacker 18. On the other hand, the drum on which the transfer has been completed is the erase lamp 20.
The charge is neutralized over the entire surface, and the remaining toner is removed by the cleaning device 22.

[0004] Such an optical print head uses an edge light emitting element array in which a large number of edge light emitting elements are linearly arranged.

[0005] As a typical example of the edge light emitting element,
Although there is an edge light emitting diode, the inventors of the present application have paid attention to a light emitting thyristor having a PNPN structure as a constituent element of a light emitting element array, and have already applied for a patent (Japanese Patent Application Laid-Open No. 1-238962; JP-A-2-
No. 14584, JP-A-2-92650, JP-A-2-9
No. 2651), which shows that the light source for an optical printer can be easily mounted, the pitch of the light emitting elements can be reduced, and a compact light emitting element array can be manufactured. Such a light emitting element array can be configured as an edge emitting thyristor array.

[0006]

However, in both the end face light emitting diode and the end face light emitting thyristor, the light emitted from the portion far from the light emitting end face does not contribute much to the light output, and the light extraction efficiency is poor. .

FIG. 2 shows a cross section of a conventional edge light emitting diode. An N-type semiconductor layer 32, P
A semiconductor layer 34 is stacked, and an anode electrode 36 is provided on the N-type semiconductor layer 34. On the back surface of the P-type semiconductor substrate 30, a cathode electrode (not shown) is provided.

The injection current I from the anode electrode 36 flows uniformly in the P-type semiconductor layer 34 and the N-type semiconductor layer 32 toward the cathode electrode, and electrons from the N-type semiconductor layer 32 It emits light by combining with holes.

In this case, the light emitted from the portion far from the light emitting end face 38 does not contribute much to the light output from the light emitting end face.
This is because components passing through the light-emitting layer, particularly on the shorter wavelength side, are greatly absorbed.

Therefore, there is a problem that the light extraction efficiency with respect to the injection current is not good. This problem is the same for the edge emitting thyristor.

An object of the present invention is to provide an edge light emitting device having an improved light extraction efficiency and an increased amount of emitted light.

[0012]

According to the present invention, there is provided an edge light emitting device in which at least two semiconductor layers are stacked on a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate and the semiconductor substrate are provided immediately above the semiconductor substrate. A semiconductor layer of a second conductivity type opposite to the first conductivity type, provided between the first conductivity type semiconductor layer and a region far from the light emitting end face; I do.

When the edge light emitting device is a diode, the first conductive type semiconductor substrate is provided on the first conductive type semiconductor substrate.
Semiconductor layer and a second semiconductor layer of a second conductivity type opposite to the first conductivity type are sequentially stacked, and between the semiconductor substrate and the first semiconductor layer, light is emitted. The semiconductor device includes a semiconductor layer of the second conductivity type provided in a region far from the end face.

When the edge light emitting device is a thyristor, the first conductive type semiconductor substrate is provided on the first conductive type semiconductor substrate.
Semiconductor layer, a second semiconductor layer of a second conductivity type opposite to the first conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type Are sequentially laminated, and a second conductive type semiconductor layer is provided between the semiconductor substrate and the first semiconductor layer in a region far from the light emitting end face.

[0015]

FIG. 3 is a sectional view of an edge light emitting diode according to an embodiment of the present invention. In the structure shown in FIG. 2, a P-type semiconductor layer 31 is provided in a region between the N-type semiconductor substrate 30 and the N-type semiconductor layer 32 and farther from the light emitting end face 38.

According to the edge light emitting diode having such a structure, when a forward voltage is applied between the anode electrode and the cathode electrode, the PN junction between the P-type semiconductor layer 31 and the N-type semiconductor layer 32 is reversed. As a result of the bias, no current can flow through this PN junction. Therefore, the injection current I from the anode electrode 36 flows intensively near the light emitting end face 38 as shown in FIG. As a result, the light emission center approaches the light emitting end face 38, so that the light extraction efficiency is improved and the amount of emitted light is increased.

FIG. 4 is a sectional view of an edge emitting thyristor according to another embodiment of the present invention. On an N-type semiconductor substrate 40, a P-type semiconductor layer 41, an N-type semiconductor layer 42, a P-type semiconductor layer 44, an N-type semiconductor layer 46, and a P-type semiconductor layer 48 are sequentially stacked. An anode electrode 50 is formed on the P-type semiconductor layer 48.
However, a gate electrode 52 is provided on the N-type semiconductor layer 46, and a cathode electrode (not shown) is provided on the back surface of the N-type semiconductor substrate 40.

The P-type semiconductor layer 41 provided between the P-type semiconductor substrate 40 and the N-type semiconductor layer 42 is provided in a region farther from the light emitting end face 54.

According to the edge emitting thyristor having such a structure, when a forward voltage is applied between the anode electrode and the cathode electrode, the PN junction between the P-type semiconductor layer 41 and the N-type semiconductor layer 42 is reversed. As a result of the bias, no current can flow through this PN junction. Therefore, the injection current I from the anode electrode 50 flows intensively near the light emitting end face 54 as shown in FIG. Thereby, as a result of the light emission center approaching the light emitting end face 54, the light extraction efficiency is improved, and the light emission amount is increased.

While the embodiments of the edge light emitting diode and the edge light emitting thyristor have been described above, it is apparent that the present invention can be realized even if the conductivity types of the semiconductor substrate and the semiconductor layer are reversed in the configuration shown. It is.

Next, a self-scanning edge emitting device array using the edge emitting thyristor shown in FIG. 4 will be described.

First, the self-scanning edge light emitting element array 3
Two basic structures will be described.

FIG. 5 is an equivalent circuit diagram of the first basic structure of the self-scanning edge light emitting element array. As a light emitting element,
The edge emitting thyristors T (-2) to T (+2) are used, and the light emitting thyristors T (-2) to T (+2) are provided with gate electrodes G _{-2 to} G ₊₂ , respectively. A power supply voltage V _GK is applied to each gate electrode via a load resistor _RL .
Also, each of the gate electrodes G _-2 ~G ₊₂ is electrically connected via a resistor R _I to produce the interaction. In addition, three transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are connected to the anode electrode of each single light emitting thyristor, respectively.
Connected every other element (as repeated).

In operation, first, the transfer clock φ ₃
Becomes high level, and the light-emitting thyristor T (0) is turned on. At this time, from the characteristics of the three-terminal thyristor,
The gate electrode G ₀ is lowered to zero volts nearby. Assuming that the power supply voltage V _GK is 5 volts, the gate voltage of each light emitting thyristor is determined from the network of the load resistance R _L and the interaction resistance R _I. Then, the light emitting thyristor T (0)
, The gate voltage of the element close to
As the distance from (0) increases, the gate voltage increases. This can be expressed as:

V _G0 <V _G1 = V _G−1 <V _G2 = V _G−2 (1) The difference between these voltages is the load resistance R _L and the interaction resistance R _I
Can be set by appropriately selecting the value of.

It is known that the turn-on voltage V _ON on the anode side of the three-terminal thyristor is higher than the gate voltage by the diffusion potential V _dif .

V _ON ≒ V _G + V _dif (2) Therefore, if the voltage applied to the anode is set higher than the turn-on voltage V _ON , the light emitting thyristor is turned on.

[0028] Now a state where the light-emitting thyristor T (0) is turned on to apply a high-level voltage V _H to the next transfer clock pulse phi _1. This clock pulse φ ₁ simultaneously applies to the light emitting thyristors T (+1) and T (−2),
When the value of the high level voltage V _H is set in the following range, only the light emitting thyristor T (+1) can be turned on.

V _G−2 + V _dif > V _H > V _{G + 1} + V _dif (3) The light emitting thyristors T (0) and T (+1) are simultaneously turned on. When the cut high-level voltage of the clock pulse phi _3, so that the light-emitting thyristor T (0) is able to transfer it becomes ON state and OFF.

As described above, in the self-scanning edge light emitting element array, the light emitting thyristors can have a transfer function by connecting the gate electrodes of the respective light emitting thyristors by the resistor network.

From the above-described principle, if the high-level voltages of the transfer clocks φ ₁ , φ ₂ , φ ₃ are set so as to slightly overlap each other in order, the ON state of the light emitting thyristor is sequentially transferred. . That is, the light emitting points are sequentially transferred, and a self-scanning edge light emitting element array can be realized.

FIG. 6 is an equivalent circuit diagram of the second basic structure of the self-scanning edge light emitting element array. This self-scanning edge light emitting element array uses a diode as a method of electrical connection between the gate electrodes of the light emitting thyristor. The light-emitting thyristors T (−2) to T (+2) are arranged in a line. G _{-2 to} G ₊₂ are light-emitting thyristors T
(-2) to T (+2) represent respective gate electrodes.
R _L represents the load resistance of the gate electrode, and D _{−2 to} D ₊₂ represent diodes that perform electrical interaction. V _GK represents a power supply voltage. The anode electrode of each single light emitting thyristor
The transfer clock lines (φ ₁ , φ ₂ ) are connected every other element.

The operation will be described. Transfer clock phi ₂ becomes high level first, and the light-emitting thyristor T (0) is turned on. At this time, due to the characteristics of the three-terminal thyristor, the gate electrode G ₀ is lowered to near zero volt. Assuming that the power supply voltage V _GK is 5 volts, the gate voltage of each light emitting thyristor is determined from the network of the resistor R _L and the diodes D _{-2 to} D ₊₂ . Then, the gate voltage of the element close to the light emitting thyristor T (0) decreases most, and thereafter the gate voltage increases as the distance from T (0) increases.

However, due to the unidirectionality and asymmetry of the diode characteristics, the effect of lowering the voltage works only to the right of T (0). That is, the gate electrode G ₁ is set to a voltage higher than G ₀ by the forward rise voltage V _{dif of the} diode, and the gate electrode G ₂ is set to a voltage higher than G _{1 by} the forward rise voltage V _{dif of the} diode. Is done. On the other hand, the gate electrode G on the left side of T (0)
_{At -1,} no current flows because the diode D _-1 is reverse-biased, and therefore has the same potential as the power supply voltage V _GK .

Next transfer clock pulse φ₁ Is the closest
Light emitting thyristors T (1), T (-1), and T (3)
And T (−3), among which:
The element with the lowest turn-on voltage is T (1), and T (1)
The turn-on voltage of (1) is about G ₁ Gate voltage + V_dif 
Where V is_dif About twice as large as Next turn electricity
The element with low pressure is T (3), and V_dif About four times
You. The on-voltage of T (-1) and T (-3) is about V_GK+ V
_dif Becomes

[0036] From the above, by setting the high-level voltage of the transfer clock pulses between about 2 times the V _dif of approximately 4 times the V _dif, it is possible to turn on only the light-emitting thyristor T (1), A transfer operation can be performed.

FIG. 7 shows a self-scanning edge light emitting element array.
FIG. 11 is an equivalent circuit diagram of a third basic structure. This self-scanning end
The surface light emitting element array includes switch elements T (-1) to T (-1).
(2) From the light emitting elements for writing L (-1) to L (2)
Become. The configuration of the switch element uses diode connection.
An example is shown. Gate electrode G of switch element_-1~
G ₁ Is also connected to the gate of the light emitting element for writing.
The write signal S is applied to the anode of the light emitting element for writing._in
Has been added.

The operation of the self-scanning edge light emitting element array will be described below. Now, assuming that the transfer element T (0) is in the ON state, the voltage of the gate electrode G ₀ falls below V _GK (here, 5 volts) and becomes almost zero volts. Therefore, the voltage of the write signal S _in becomes PN
If the junction diffusion potential (about 1 volt) or higher, the light emitting element L (0) can be in a light emitting state.

[0039] In contrast, the gate electrode G _-1 is about 5 volts, the gate electrode G ₁ is about 1 volt. Therefore, the writing voltage of the light emitting element L (-1) is about 6 volts,
The write voltage of the light emitting element L (1) is about 2 volts.
Now, the voltage of the write signal S _in which can write only in the light emitting element L (0) is a range of about 1 to 2 volts. When the light emitting element L (0) is turned on, that is, when the light emitting element enters a light emitting state, the voltage of the write signal S _in line is fixed at about 1 volt, so that an error that another light emitting element is selected can be prevented. it can.

The light emission intensity is determined by the amount of current flowing _{in the} write signal _Sin, and an image can be written at an arbitrary intensity. Further, in order to transfer the light emitting state to the next element, it is necessary to once lower the voltage of the write signal S _in line to zero volt and turn off the light emitting element once.

The self-scanning edge light emitting element array as described above is integrated on a semiconductor wafer, cut out into one semiconductor chip (hereinafter, referred to as a light emitting element array chip), and a required number of these chips are arranged and long. Make a scale.

FIG. 8 is a perspective view showing an example of an optical print head using a self-scanning edge light emitting element array. A self-scanning edge light emitting element array 62 and a selfoc lens array 63 (a selfoc lens is a registered trademark of Nippon Sheet Glass Co., Ltd.) are attached and mounted on a printed wiring board 61.

The self-scanning end face light emitting element array 62 is constituted by arranging light emitting element array chips 69 continuously and linearly. For example, if one light emitting element array chip is 1200 DPI and 256 light emitting elements are arranged, the chip length is about 5.4 mm. The size of the light emitting point of the light emitting element is, for example, 5 μm.
× 1 μm.

On the other hand, the SELFOC lens array 63
A predetermined number of SELFOC lenses 64 are
It is configured by continuously arranging the selfoc lens array units 66 arranged and fixed thereon in a linear manner.

The light from the light emitting end face of the light emitting element forms an image on the surface of the photosensitive drum 2 by the selfoc lens 64.

According to the optical print head using the edge emitting thyristor array as described above, since the light intensity of each edge emitting element is increased, it is possible to maintain print quality with low power consumption.

[0047]

According to the edge emitting device of the present invention, the injected power can be concentrated near the light emitting end face, so that the amount of light extracted from the light emitting end face can be increased, and therefore the light extraction efficiency can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of an optical printer.

FIG. 2 is a sectional view of a conventional edge light emitting diode.

FIG. 3 is a sectional view of an edge light emitting diode according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of an edge emitting thyristor according to another embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a first basic structure of the self-scanning edge emitting element array.

FIG. 6 is an equivalent circuit diagram of a second basic structure of the self-scanning edge light emitting element array.

FIG. 7 is an equivalent circuit diagram of a third basic structure of the self-scanning edge light emitting element array.

FIG. 8 is a perspective view showing an example of an optical print head using a self-scanning edge light emitting element array.

[Explanation of symbols]

 30, 40 N-type semiconductor substrate 32, 42, 46 N-type semiconductor layer 31, 34, 41, 44, 48 P-type semiconductor layer 36, 50 Anode electrode 38, 54 Light emitting end face 52 Gate electrode 61 Printed wiring board 62 Self-scanning Mold end face light emitting element array 63 Selfoc lens array 64 Selfoc lens 66 Selfoc lens array unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Takeshi Yamashita 3-5-11 Doshomachi, Chuo-ku, Osaka-shi, Osaka Inside Nippon Sheet Glass Co., Ltd. (72) Inventor: Harunobu Yoshida 3 Doshomachi, Chuo-ku, Osaka-shi, Osaka 5-11-11 Nippon Sheet Glass Co., Ltd. (72) Inventor Masaru Kobayashi 3-5-11 Doshomachi, Chuo-ku, Osaka-shi, Osaka Inside Nippon Sheet Glass Co., Ltd.

Claims (3)

[Claims] A semiconductor substrate of a first conductivity type;
In the edge-emitting device in which the two semiconductor layers are stacked, the edge-emitting device is provided between the semiconductor substrate and the semiconductor layer of the first conductivity type provided immediately above the semiconductor substrate, and is provided in a region far from the light-emitting end surface. An edge light emitting device comprising a semiconductor layer of a second conductivity type opposite to the first conductivity type. 2. A first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type opposite to the first conductivity type on a semiconductor substrate of the first conductivity type. In the edge light emitting diode sequentially laminated, between the semiconductor substrate and the first semiconductor layer,
An end surface light emitting diode comprising a semiconductor layer of the second conductivity type provided in a region far from the light emitting end surface. 3. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type opposite to the first conductivity type on a semiconductor substrate of the first conductivity type, In an edge light-emitting thyristor in which a third semiconductor layer of a first conductivity type and a fourth semiconductor layer of a second conductivity type are sequentially stacked, between the semiconductor substrate and the first semiconductor layer So,
An edge emitting thyristor comprising a semiconductor layer of a second conductivity type provided in a region far from the light emitting end face.