JP2011054754A - Semiconductor element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which suppresses a variation of a line width of wiring formed by wet etching. <P>SOLUTION: This method for manufacturing a semiconductor element includes the steps of: forming an electrode 11 on a semiconductor layer 14; forming an interlayer insulating film 12 which has a wiring connection hole 12a reaching the electrode 11 on the semiconductor layer 14, and is formed with a cavity part 12b around the wiring connection hole 12a, depositing wiring materials 18 from on the interlayer insulating film 12 and forming a cavity part 18a in the wiring materials 18 corresponding to the cavity part 12b of the interlayer insulating film 12, forming a resist film 19 for forming wiring 13 connected to the electrode 11 through the wiring connection hole 12a on the wiring materials 18 so as to coat the cavity part 18a formed in the wiring materials 18, and performing the wet etching with the resist film 19 as a mask to remove the wiring materials 18 selectively to form the wiring 13. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a light emitting element such as a light emitting thyristor, there is a wiring structure including an electrode provided on a semiconductor layer and a wiring connected to the electrode through a contact hole opened in an insulating film on the electrode (for example, a patent) References 1 and 2).

  In Patent Document 1, in a mesa-type surface light emitting device, a gold (Au) electrode is formed on a semiconductor layer of a light emitting portion, the entire light emitting surface is covered with an insulating film, and a contact hole is formed in the insulating film. It describes that aluminum (Al) is deposited from above and Al wiring is formed by patterning Al by wet etching. In addition, since the Al wiring passes through the step of the mesa, it is necessary to form it as thick as about 1 μm in order to prevent disconnection, and there is a description that the patterning accuracy of the Al film having such a thickness is not good (about ± 1 μm). is there. The reason is that, when etching Al, etching of the side surface of the wiring portion proceeds while the unnecessary portion of Al is removed, and the etching amount of this side surface varies. And in patent document 1, in order to suppress the variation in the light output due to the variation in the width of the Al wiring, the mask dimension when patterning Al by wet etching is set under specific conditions, and the width of the Al wiring is set to the Au electrode. It has been proposed to make it smaller than the width of.

  Patent Document 2 describes that the overlap width between the peripheral portion of the Au electrode and the insulating film is 1 μm or less in order to suppress the deterioration of the reliability of the light emitting element due to the alloying of the Au electrode and the Al wiring. Yes.

  Further, as described in, for example, Patent Documents 3 to 11, a self-scanning light-emitting element array (SLED: Self-) having a structure in which a plurality of light-emitting thyristors are arranged and having a function of sequentially self-scanning light-emitting points. scanning Light-emitting Device) is known.

  Patent Document 12 describes that the surface of a compound semiconductor containing GaAs as a main component is treated with a plasma containing fluorine element, and an electrode is formed on the surface of the compound semiconductor by vacuum deposition.

  Further, in Patent Document 13, as a method of forming an electrode of a compound semiconductor, an insulating film is formed on the main surface of the semiconductor, an opening for electrode formation is formed in the insulating film, and the semiconductor exposed from the opening is formed using the insulating film as a mask. It is possible to remove a part by etching, form a recess for electrode formation, deposit an electrode material on the entire upper surface of the semiconductor, remove the insulating film by etching, and remove the electrode material on the insulating film by lift-off Are listed.

JP 2001-85740 A JP-A-2005-340767 JP-A-1-238996 Japanese Patent Laid-Open No. 2-14584 JP-A-2-263668 JP 2003-249681 A JP 2005-297422 A JP 2007-250853 A JP 2007-250961 A JP 2008-105221 A JP 2008-284819 A JP-A-5-36622 JP 2000-58481 A

  By the way, when the wiring is formed by wet etching, the amount of etching in the width direction of the wiring varies, so that the variation in the line width increases. On the other hand, in a semiconductor element, there is a demand for suppressing variations in the line width of wiring from the viewpoint of suppressing variations in characteristics. For example, in a light emitting element, there is a demand for suppressing variation in the line width of wiring arranged on the light extraction side from the viewpoint of suppressing variation in light amount.

  An object of the present invention is to provide a semiconductor element in which variations in line width of wiring formed by wet etching are suppressed and a method for manufacturing the same.

  The invention according to claim 1 has an electrode provided on the semiconductor layer, a wiring connection hole provided on the semiconductor layer, reaching the electrode, and a recess is formed around the wiring connection hole. A semiconductor element comprising: an interlayer insulating film; and a wiring formed on the interlayer insulating film by wet etching and connected to the electrode through the wiring connection hole.

  According to a second aspect of the present invention, there is provided an interlayer in which an electrode is formed on a semiconductor layer, a wiring connection hole reaching the electrode is formed on the semiconductor layer, and a recess is formed around the wiring connection hole A step of forming an insulating film; a step of depositing a wiring material on the interlayer insulating film, the step of forming a recess in the wiring material corresponding to the recess of the interlayer insulating film; Forming a resist film for forming a wiring to be connected to the electrode through the wiring connection hole so as to cover a recess formed in the wiring material; and wet etching using the resist film as a mask. And the step of selectively removing the wiring material to form the wiring.

  Invention of Claim 3 is a manufacturing method of the semiconductor element of Claim 2, Comprising: The process of forming the said electrode has an opening in the position in which the said electrode is formed on the said semiconductor layer Forming a resist film for forming; performing wet etching using the resist film for electrode formation as a mask to dig up the semiconductor layer; and depositing an electrode material from the resist film for electrode formation; Removing the resist film for forming the electrode, leaving the electrode material deposited on the semiconductor layer out of the electrode material to be the electrode, wherein the electrode is formed by the region where the semiconductor layer is dug down. Forming a recess around the electrode, and in the step of forming the interlayer insulating film, the recess of the interlayer insulating film is formed corresponding to the recess formed around the electrode. And wherein the door.

  Invention of Claim 4 is a manufacturing method of the semiconductor element of Claim 2, Comprising: The process of forming the said electrode is an electrode which has an opening in the position in which the said electrode is formed on the said semiconductor layer Forming a resist film for forming; depositing an electrode material on the electrode forming resist film; and performing wet etching using the electrode material as a mask, around the electrode material deposited on the semiconductor layer Forming a recess in the substrate, and removing the electrode-forming resist film to leave the electrode material deposited on the semiconductor layer out of the electrode material, thereby forming the electrode. In the step of forming a film, a recess of the interlayer insulating film is formed corresponding to the recess formed around the electrode.

  According to the first aspect of the present invention, it is possible to provide a semiconductor element in which variation in line width of wiring formed by wet etching is suppressed.

  According to the second aspect of the present invention, it is possible to provide a method for manufacturing a semiconductor element in which variation in line width of wiring formed by wet etching is suppressed.

  According to invention of Claim 3, a recessed part can be formed using the resist film for electrode formation.

  According to invention of Claim 4, a recessed part can be formed using the deposited electrode material as a mask.

It is sectional drawing which shows an example of the semiconductor element which concerns on embodiment. It is process drawing which shows the 1st example of the manufacturing method of the semiconductor element which concerns on embodiment. It is a graph which shows an example of the relationship between etching time and the line | wire width of wiring. It is process drawing which shows the 2nd example of the manufacturing method of the semiconductor element which concerns on embodiment. It is sectional drawing which shows an example of a light emitting element. It is an equivalent circuit diagram which shows an example of a light emitting element array. It is a top view which shows an example of a light emitting element array. It is A-A 'sectional drawing of FIG. It is B-B 'sectional drawing of FIG. It is the schematic which shows an example of a structure of a light irradiation apparatus. 1 is a schematic diagram illustrating an example of a configuration of an image forming apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Semiconductor element]
FIG. 1 is a cross-sectional view showing an example of a semiconductor element according to the present embodiment. In FIG. 1, the semiconductor element 10 includes an electrode 11, an interlayer insulating film 12, and a wiring 13.

  The electrode 11 is provided on the semiconductor layer 14 on the substrate 15 constituting the semiconductor element 10. Specifically, the electrode 11 is made of metal, for example, Au or a material containing Au as a main component. However, the electrode 11 may be formed of other materials. Other electrode materials may be simple metals, alloys, or combinations of any of Ag, Pt, Pd, W, Ti, Ni, and Cr. The electrode 11 constitutes an ohmic electrode, for example.

The interlayer insulating film 12 is provided on the semiconductor layer 14 and has a wiring connection hole (contact hole) 12 a reaching the electrode 11. The interlayer insulating film 12 is, for example, a SiO ₂ film.

  In the present embodiment, the interlayer insulating film 12 has a recess (also referred to as a stepped portion) 12b around the contact hole 12a. In one embodiment, as shown in FIG. 1, a recess 14 a is formed around the electrode 11 of the semiconductor layer 14, and a recess 12 b of the interlayer insulating film 12 is formed corresponding to the recess 14 a of the semiconductor layer 14. .

  The wiring 13 is provided on the interlayer insulating film 12 and is formed by wet etching. The wiring 13 is connected to the electrode 11 through the contact hole 12a. The wiring 13 is specifically a metal, and is formed of, for example, Al or a material mainly containing Al. However, the wiring 13 may be formed of other materials. The other material may be a simple substance, alloy, or a combination of any of Ag, Au, Pt, Pd, W, Ti, Ni, and Cr.

  FIG. 2 is a process diagram showing a first example of a method for manufacturing a semiconductor device according to the present embodiment. Hereinafter, a first example of a method for manufacturing the semiconductor element 10 will be described with reference to FIG.

  First, as shown in FIGS. 2A to 2C, the electrode 11 is formed on the semiconductor layer 14.

  That is, as shown in FIG. 2A, an electrode-forming resist film 16 having an opening 16a at a position where the electrode 11 is formed is formed on the semiconductor layer. Specifically, a resist film 16 for forming an electrode having an opening 16a is formed by patterning on a semiconductor layer 14 made of an epitaxial layer formed on a substrate (for example, a GaAs substrate) 15 by a photolithography process. Then, wet etching is performed using the resist film 16 as a mask, and the semiconductor layer 14 is dug down to form a dug-down portion 14b. Here, as the etching solution, for example, a mixed solution of sulfuric acid, hydrogen peroxide, and water is used. The depth of etching is, for example, about 0.2 μm or less.

  Next, as shown in FIG. 2B, an electrode material 17 is deposited on the resist film 16. Specifically, an Au electrode material is formed by vapor deposition. As a result, the electrode material 17 is deposited in a region corresponding to the opening 16 a in the resist film 16 and the semiconductor layer 14.

  Next, as shown in FIG. 2C, the resist film 16 is removed to leave the electrode material deposited on the semiconductor layer 14 in the electrode material 17, thereby forming the electrode 11. Specifically, the electrode 11 is formed by performing lift-off with a tape peeling or resist peeling liquid. Around the electrode 11, a recessed portion 14a is formed by a dug down portion 14b which is a dug down region.

  After the electrode 11 is formed as described above, as shown in FIG. 2D, the semiconductor layer 14 has a contact hole 12a reaching the electrode 11, and a recess 12b is formed around the contact hole 12a. The formed interlayer insulating film 12 is formed. Specifically, an interlayer insulating film 12 is formed on the entire surface of the substrate by a chemical vapor deposition method (CVD method) to a thickness of about 0.5 μm, and a resist film having an opening at a position where the contact hole 12a is formed is formed as a photo resist. The contact hole 12a is formed by lithography and reactive ion etching (RIE). In this step, the recess 12b of the interlayer insulating film 12 is formed corresponding to the recess 14a formed around the electrode 11.

  Next, as shown in FIG. 2E, a wiring material 18 is deposited on the interlayer insulating film 12. At this time, a recess 18 a is formed in the wiring material 18 corresponding to the recess 12 b of the interlayer insulating film 12. Then, a resist film 19 for forming the wiring 13 connected to the electrode 11 through the contact hole 12 a is formed on the wiring material 18 so as to cover the recess 18 a formed in the wiring material 18. Specifically, an Al wiring material is formed to a thickness of about 1.0 μm by sputtering, and then a resist film 19 for wiring formation is formed by patterning by photolithography. In this step, the resist film 19 is provided with a convex portion 19 a that protrudes toward the wiring material 18 corresponding to the concave portion 18 a of the wiring material 18.

  Next, as shown in FIG. 2F, wet etching is performed using the resist film 19 as a mask, and the wiring material 18 is selectively removed to form the wiring 13. For this etching, for example, an etchant containing phosphoric acid as a main component is used. After the etching, the resist film 19 is removed.

  During the above wet etching, the protrusion 19a formed on the resist film 19 prevents the progress of etching in the width direction (lateral direction, the direction parallel to the surface of the semiconductor layer 14), and the etching rate in the width direction is increased. Become slow. That is, in the portion where the convex portion 19a (or the concave portion 18a) is provided, the change in the line width of the wiring with respect to the etching time is reduced. Thereby, controllability of the line width of the wiring is improved, and variations in the line width are suppressed.

  FIG. 3 is a graph showing an example of the relationship between the etching time and the line width of the wiring. This graph is obtained by experiment, the horizontal axis indicates the etching time, and the vertical axis indicates the line width. The value on the vertical axis indicates the difference between the actual line width and the target value, and is positive when the actual line width is thicker than the target. FIG. 3 shows that the change in the line width at the convex portion 19a (or the concave portion 18a) is small with respect to the etching time. For example, a stable line width can be obtained by setting a line width target in an area A (area indicated by a broken line in FIG. 3) A in which the change in the line width is small. However, the line width target may be set outside the region A.

  FIG. 4 is a process diagram showing a second example of the method for manufacturing a semiconductor device according to the present embodiment. Hereinafter, a second example of the method for manufacturing the semiconductor element 10 will be described with reference to FIG.

  First, as shown in FIGS. 4A to 4D, the electrode 11 is formed on the semiconductor layer 14.

  That is, as shown in FIG. 4A, a resist film 16 for forming an electrode having an opening 16a is formed on the semiconductor layer 14 at a position where the electrode 11 is formed. Specifically, a resist film 16 for forming an electrode having an opening 16a is formed by patterning on a semiconductor layer 14 made of an epitaxial layer formed on a substrate (for example, a GaAs substrate) 15 by a photolithography process.

  Next, as shown in FIG. 4B, an electrode material 17 is deposited on the resist film 16. Specifically, an Au electrode material is formed by vapor deposition. As a result, the electrode material 17 is deposited in a region corresponding to the opening 16 a in the resist film 16 and the semiconductor layer 14.

  Next, as shown in FIG. 4C, wet etching is performed using the electrode material 17 as a mask to form a recess 14 a around the electrode material 17 deposited on the semiconductor layer 14. Here, as the etching solution, for example, a mixed solution of sulfuric acid, hydrogen peroxide, and water is used. The depth of etching is, for example, about 0.2 μm or less.

  Next, as shown in FIG. 4D, the resist film 16 is removed to leave the electrode material deposited on the semiconductor layer 14 in the electrode material 17 to form the electrode 11. Specifically, the electrode 11 is formed by performing lift-off with a tape peeling or resist peeling liquid.

  After the electrode 11 is formed as described above, although not shown in FIG. 4, the interlayer insulating film 12 and the wiring 13 are formed as in the first example. That is, as shown in FIGS. 2D to 2F, an interlayer insulating film 12 is formed, a wiring material 18 is deposited thereon, a resist film 19 for forming a wiring is formed, and wiring is formed by wet etching. 13 is formed and the resist film 19 is removed.

  In the first and second examples, the recess 14a is formed in the semiconductor layer 14, and the recess 12b of the interlayer insulating film 12 is formed by the recess 14a. However, the recess 14a of the semiconductor layer 14 is omitted. Also good. In this case, for example, the recess 12b of the interlayer insulating film 12 may be formed by cutting after the interlayer insulating film 12 is formed.

[Light emitting element]
In one aspect, the semiconductor element according to this embodiment is a light emitting element, and the wiring 13 is disposed on the light extraction side of the light emitting element. In this aspect, variation in the light amount of the light emitting element can be suppressed by suppressing variation in the line width of the wiring 13.

  FIG. 5 is a cross-sectional view illustrating an example of a light-emitting element. In FIG. 5, the light emitting element 20 includes a semiconductor substrate 21, a semiconductor stacked body 22 in which a plurality of semiconductor layers including a light emitting layer are stacked, and a wiring structure 23 according to the present embodiment. In the example of FIG. 5, the light emitting element 20 is a light emitting thyristor having a pnpn structure.

  The semiconductor substrate 21 is a p-type semiconductor substrate, for example, a p-type GaAs substrate. An anode electrode 24 which is an ohmic electrode is provided on the back surface of the semiconductor substrate 21.

  The semiconductor stacked body 22 includes a p-type semiconductor layer (anode layer) 22a, an n-type semiconductor layer (n-type gate layer) 22b, a p-type semiconductor layer (p-type gate layer) 22c, which are sequentially stacked on the semiconductor substrate 21. And an n-type semiconductor layer (cathode layer) 22d. These semiconductor layers are, for example, AlGaAs layers. In the semiconductor stacked body 22, the cathode layer 22d is patterned and partially removed.

  The wiring structure 23 includes electrodes 11c and 11g, an interlayer insulating film 12, and wirings 13c and 13g.

  The electrode 11c is provided on the cathode layer 22d, which is a semiconductor layer on the light extraction side, and constitutes a cathode electrode. The electrode 11g is provided on the p-type gate layer 22c and constitutes a gate electrode.

  The interlayer insulating film 12 is provided on the semiconductor stacked body 22 and has a contact hole 12a reaching the electrodes 11c and 11g. A recess is formed around each contact hole 12a as in FIG.

  The wirings 13c and 13g are formed on the interlayer insulating film 12 by wet etching, and are connected to the electrodes 11c and 11g through the contact holes 12a, respectively.

  In the light emitting element 20 having the above-described configuration, for example, after the semiconductor stacked body 22 is formed on the semiconductor substrate 21, the electrodes 11c and 11g are formed on the semiconductor stacked body 22 in the same manner as described in the section [Semiconductor element]. The interlayer insulating film 12 and the wirings 13c and 13g are formed in order.

  In the above description, a light emitting thyristor having a pnpn structure is exemplified as the light emitting element, but other types of light emitting elements such as a light emitting thyristor having an npnp structure may be used.

[Light emitting element array]
In one embodiment, a light emitting element array having a plurality of the light emitting elements is configured. In this aspect, by suppressing the variation in the line width of the wiring 13, the variation in the amount of light between the light emitting elements of the light emitting element array can be suppressed. In a specific embodiment, the light emitting element array is a self-scanning light emitting element array (SLED) having a structure in which a plurality of light emitting thyristors are arranged one-dimensionally and having a function of sequentially self-scanning light emitting points. The SLED may be a type in which the same light emitting thyristor performs both the light emitting function and the light emitting point scanning function (called a non-separable type), or the light emitting thyristor that performs the light emitting function and the light emitting point scanning function. A type in which the light emitting thyristor is provided separately (referred to as a separate type) may be used.

  FIG. 6 is an equivalent circuit diagram showing an example of the light emitting element array. FIG. 7 is a plan view showing an example of the light emitting element array. FIG. 8 is a cross-sectional view taken along line A-A ′ of FIG. 7. FIG. 9 is a cross-sectional view taken along the line B-B ′ of FIG. 7. Hereinafter, an example of the light emitting element array will be described with reference to FIGS. Here, the light emitting element array is a separation type SLED.

  As shown in FIGS. 6 and 7, the light emitting element array 30 includes a shift unit 31 for scanning a light emitting point, and a light emitting unit 32 in which the light emitting point is scanned by the shift unit 31. The shift unit 31 includes a plurality of switch elements (specifically light emitting thyristors) T1, T2,..., And the light emitting unit 32 includes a plurality of light emitting elements (specifically light emitting thyristors) L1, L2, and so on. ···including.

  The gates of the switch elements T1, T2,... Are coupled by a coupling diode D. Further, the gates of the switch elements T1, T2,... Are respectively connected to the power supply wiring (VGA line) 33 via the gate load resistance Rg. A power supply voltage VGA is supplied to the power supply wiring 33.

  .. Are connected to the cathodes of the switch elements T1, T2,..., And a signal wiring to which a transfer signal for sequentially turning on the plurality of light emitting elements L1, L2,. In the example of FIG. 6, signal wiring 34 is connected to odd-numbered switch elements T1, T3,..., And signal wiring 35 is connected to even-numbered switch elements T2, T4,. Yes. A clock signal φ1 is supplied to the signal line 34 via the resistor R1, and a clock signal φ2 is supplied to the signal line 35 via the resistor R2.

  The gate of the first switch element T1 is connected to the signal line 35 via the diode DS. In FIG. 7, the diode DS and the resistors R1 and R2 are not shown.

  The gates of the light emitting elements L1, L2,... Are connected to the gates of the corresponding switch elements T1, T2,.

  The cathodes of the light emitting elements L1, L2,... The signal wiring 36 is supplied with a lighting signal φI for lighting the light emitting element or controlling the light amount of the light emitting element.

  As shown in FIG. 7, the light emitting element array 30 includes a cathode electrode 41 of switching elements T1, T2,..., A cathode electrode 42 of light emitting elements L1, L2,. A gate electrode 44 common to the switch element and the light emitting element, and electrodes 45 and 46 of the gate load resistance Rg are provided. The cathode electrode 41 is connected to the signal wiring 34 or 35, the cathode electrode 42 is connected to the signal wiring 36, and the electrode 46 is connected to the power supply wiring 33. The cathode electrode 43, the gate electrode 44, and the electrode 45 are connected to the connection wiring 37.

  In FIG. 7, for the sake of clarity, the wiring is represented by lines, and the joint between the wiring and the electrodes is represented by black circles for convenience. However, the wiring actually has a width, and the signal wiring 36 partially blocks the light of the light emitting unit 32.

  8 and 9, the light emitting element array 30 includes a semiconductor substrate 51 and a semiconductor stacked body 52 provided on the substrate.

  Here, the semiconductor substrate 51 is a p-type semiconductor substrate, for example, a p-type GaAs substrate. An anode electrode 53 that is an ohmic electrode is provided on the back surface of the semiconductor substrate 51.

  The semiconductor stacked body 52 includes a p-type semiconductor layer (anode layer) 52a, an n-type semiconductor layer (n-type gate layer) 52b, a p-type semiconductor layer (p-type gate layer) 52c, which are sequentially stacked on the semiconductor substrate 51. And an n-type semiconductor layer (cathode layer) 52d. These semiconductor layers are, for example, AlGaAs layers. By patterning these semiconductor layers, switch elements T1, T2,..., Coupling diode D, gate load resistor Rg, resistors R1, R2, diode DS, and light emitting elements L1, L2,. Is done.

  On the cathode layer 52d, a cathode electrode 41 of a switching element, a cathode electrode 42 of a light emitting element, and a cathode electrode 43 of a coupling diode are provided. A gate electrode 44 and gate load resistance electrodes 45 and 46 are provided on the p-type gate layer 52c.

  An interlayer insulating film 55 is provided so as to cover these electrodes 41 to 46, and a power supply wiring 33, signal wirings 34 to 36, and connection wiring 37 are provided on the interlayer insulating film 55. These wirings 33 to 37 are respectively connected to corresponding electrodes 41 to 46 through contact holes formed in the interlayer insulating film 55. In the interlayer insulating film 55, recesses are formed around each contact hole, but the illustration is omitted in FIGS.

  As shown in FIG. 9, the light emitting elements are separated by mesa etching, and a relatively large step portion 60 (for example, exceeding 1 μm) is formed between the light emitting elements.

  Hereinafter, the operation of the light emitting element array 30 will be briefly described. For example, in FIG. 6, it is assumed that the clock signal φ2 is at a low level, the clock signal φ1 is at a high level (0 V), and the switch element T2 is in an on state. At this time, the gate voltage of the switch element T2 is V0 (about 0 V). Since the gate voltages of the switch elements T3, T4, T5,... On the rear stage side of the switch element T2 drop in order by the ON voltage VD of the coupling diode D, respectively, V0-VD, V0-2VD, V0-3VD. , ... On the other hand, the gate voltage of the switch element T1 on the upstream side of the switch element T2 is substantially the same as the power supply voltage VGA (for example, −5 V).

  Next, when the clock signal φ2 becomes high level and the clock signal φ1 becomes low level, the switch element T2 is turned off and the next switch element T3 is turned on. At this time, the low level voltage of the clock signal φ1 is set in a range in which only the switch element T3 is turned on and the other switch elements remain in the off state. For example, the low level voltage of the clock signal φ1 is set to be equal to or lower than the voltage (V0−VD−Vd) required to turn on the switch element T3 and equal to or higher than the voltage required to turn on the switch element T5 (V0−3VD−Vd). Is done. Vd is the diffusion potential of the pn junction between the gate and cathode of the light emitting thyristor.

  When the switch element T3 is turned on, the gate voltage of the switch element T3 becomes V0 (about 0 V). Similarly to the above, the gate voltages of the switch elements T4, T5, T6,... On the rear stage side of the switch element T3 are V0-VD, V0-2VD, V0-3VD,. The gate voltage of the switch elements T2 and T1 on the front stage side of T3 is substantially the same as the power supply voltage VGA (for example, −5 V).

  In this way, the clock signals φ1, φ2 are alternately and alternately switched between the low level and the high level, so that the switch elements T1, T2, T3,.

  In the first stage of scanning, the clock signal φ1 is set to a low level and the clock signal φ2 is set to a high level, whereby the first switch element T1 is turned on. Thereafter, as described above, the switch elements T2, T3,... Are sequentially turned on by alternately switching between the low level and the high level of the clock signals φ1, φ2.

  By the way, the gates of the switch elements T1, T2,... Are connected to the gates of the corresponding light emitting elements L1, L2,. It becomes the same as the gate voltage of the switch elements T1, T2,. Therefore, for example, when the switch element T2 is in the ON state, the gate voltage of the light emitting element L2 is V0 (about 0 V), and the gate voltages of the light emitting elements L3, L4,. 2VD,..., And the gate voltage of the light emitting element L1 on the front stage is the power supply voltage VGA.

  In this way, the switch elements in the on state move sequentially, and when the switch element Tn (n = 1, 2,...) Is in the on state, the light emitting element Ln corresponding to the switch element Tn is lit. Controlled by signal φI. Specifically, the light emitting element Ln is turned on when the lighting signal φI is at a low level, and the light emitting element Ln is turned off when the lighting signal φI is at a high level. At this time, the low level voltage of the lighting signal φI is set to a range in which only the light emitting element Ln is turned on and the other light emitting elements are kept in the off state. For example, the low level voltage of the lighting signal φI is set to be equal to or lower than the voltage (V0−Vd) required to turn on the light emitting element Ln and equal to or higher than the voltage required to turn on the light emitting element Ln + 1 (V0−VD−Vd). .

  In this example, the configuration having two-phase signal wirings (clock lines) is illustrated, but a configuration having three or more phases of clock lines may be used.

  Hereinafter, an example of a method for manufacturing the light emitting element array 30 will be described with reference to FIGS.

  First, on a semiconductor substrate 51, a p-type semiconductor layer (anode layer) 52a, an n-type semiconductor layer (n-type gate layer) 52b, a p-type semiconductor layer (p-type gate layer) 52c, and an n-type semiconductor layer (cathode layer). ) 52d is deposited by metal organic chemical vapor deposition (MOCVD). Then, element separation is performed by mesa etching. Due to this element separation, a stepped portion 60 is formed between the elements. In addition to element isolation, etching also forms the cathode island of the switch element, the cathode island of the light emitting element, and the island of the light emitting part and the shift part and the island of the gate load resistor.

  Next, as described in the “Semiconductor element” column, the electrodes 41 to 46, the interlayer insulating film 55, and the wirings 33 to 37 are formed in this order.

  Specifically, after forming electrodes 41 to 46 mainly composed of Au, an interlayer insulating film 55 is formed on the entire surface of the substrate, and contact holes reaching the electrodes 41 to 46 are formed in the interlayer insulating film 55.

  After the interlayer insulating film 55 is formed, a wiring material is deposited on the entire surface of the substrate. Here, in one embodiment, the wiring material is a material mainly composed of Al. This is because Al is a material that can be easily processed and can be stably connected even with a large level difference.

  Next, a resist film for wiring formation is formed on the wiring material, wet etching is performed using this resist film as a mask, wiring is formed, and the resist film is removed.

  In the wet etching, overetching is performed so that no residue of the wiring material (Al) remains in the stepped portion 60 of the mesa. Although this over-etching can be a factor that increases the variation in the line width of the wiring, in this embodiment, the progress of the etching in the width direction of the wiring is suppressed by the convex portion of the resist film for wiring formation. Variation in line width is suppressed.

[Light irradiation device]
The light emitting element array is used in, for example, a light irradiation device. The light irradiation device includes, for example, the light emitting element array and a drive unit that drives the light emitting element array. The drive unit supplies power and control signals for driving the light emitting element array to the light emitting element array. Such a light irradiation apparatus is used as, for example, an exposure apparatus, an image writing head, or a print head that forms an image by irradiating light to an image carrier such as a photoconductor. However, the light irradiation device may be used for other purposes such as a light source of an image reading device.

  FIG. 10 is a schematic diagram illustrating an example of the configuration of the light irradiation apparatus. In FIG. 10, the light irradiation apparatus 100 includes a substrate 110, a light emitting element array 120 provided on the substrate 110, and a driving unit 130 provided on the substrate 110.

  The light emitting element array 120 is, for example, an SLED, and has a configuration shown in FIGS.

  The drive unit 130 drives the light emitting element array 120 and is, for example, a drive circuit. For example, the drive unit 130 supplies the power supply voltage VGA to the power supply wiring of the light emitting element array 120, supplies the transfer signals φ1 and φ2 to the signal wiring for the transfer signal, and supplies the lighting signal φI to the signal wiring for the lighting signal To do.

  The light irradiation device 100 further supports a lens (for example, a rod lens array) for imaging the light emitted from the light emitting element array 120 on the surface of an image holding body, a housing for supporting the substrate 110, and a lens. A holder for shielding the light emitting element array 120 from the outside, a leaf spring for pressing the housing in the lens direction, and the like may be included.

  Further, the light irradiation apparatus 100 may include a plurality of light emitting element arrays 120. For example, a plurality of light emitting element arrays 120 may be linearly arranged on the substrate 110, and the plurality of light emitting element arrays 120 may be driven by the driving unit 130 on the substrate 110.

[Image forming apparatus]
The light irradiation device is used in an image forming apparatus, for example. The image forming apparatus includes, for example, the light irradiation device and an image holding body on which an image is formed by light from the light emitting element array of the light irradiation device. The drive unit of the light irradiation device drives the light emitting element array based on the image data, thereby forming an image corresponding to the image data on the image holding body.

  FIG. 11 is a schematic diagram illustrating an example of the configuration of the image forming apparatus. Here, the image forming apparatus 200 is an electrophotographic apparatus, for example, a printer, a copier, a facsimile machine, or the like.

  In FIG. 11, an image forming apparatus 200 includes a photoconductor 210 as an image carrier, a charging device 220 that uniformly charges the surface of the photoconductor 210, and a surface of the charged photoconductor 210 based on image data. A light irradiation device (exposure device) 230 that forms an electrostatic latent image by exposure, a developing device 240 that develops the electrostatic latent image into a toner image, and a transfer that transfers the toner image to a printing medium P such as paper. And a fixing device 260 that fixes the transferred toner image on the print medium P.

  In the present embodiment described above, the following effects can also be obtained.

  In one embodiment of this embodiment, a surface on which an electrode is formed is shaved by wet etching. Thereby, the adhesiveness with respect to the semiconductor layer of an electrode improves.

  In one embodiment of the present embodiment, the surface on which the electrode material is deposited is cut away. For this reason, the lift-off electrode material is easily separated.

  In addition, this invention is not limited to the said embodiment, It can change variously within the range which does not deviate from the summary of this invention.

  DESCRIPTION OF SYMBOLS 10 Semiconductor element, 11 Electrode, 12 Interlayer insulation film, 12a Wiring connection hole (contact hole), 12b Recessed part (step part), 13 Wiring, 14 Semiconductor layer, 14a Recessed part, 15 Substrate, 16 Resist film, 17 Electrode material, 18 Wiring material, 18a concave portion, 19 resist film, 19a convex portion.

Claims (4)

An electrode provided on the semiconductor layer;
An interlayer insulating film provided on the semiconductor layer, having a wiring connection hole reaching the electrode, and having a recess formed around the wiring connection hole;
A wiring formed on the interlayer insulating film by wet etching and connected to the electrode via the wiring connection hole;
A semiconductor device comprising: Forming an electrode on the semiconductor layer;
Forming an interlayer insulating film having a wiring connection hole reaching the electrode on the semiconductor layer and having a recess formed around the wiring connection hole;
A step of depositing a wiring material on the interlayer insulating film, the step of forming a recess in the wiring material corresponding to the recess of the interlayer insulating film;
Forming a resist film on the wiring material to form a wiring connected to the electrode through the wiring connection hole so as to cover a recess formed in the wiring material;
Performing wet etching using the resist film as a mask, and selectively removing the wiring material to form the wiring;
The manufacturing method of the semiconductor element characterized by the above-mentioned. A method of manufacturing a semiconductor device according to claim 2,
The step of forming the electrode includes:
Forming a resist film for forming an electrode having an opening at a position where the electrode is formed on the semiconductor layer;
Performing wet etching using the resist film for electrode formation as a mask and digging down the semiconductor layer; and
Depositing an electrode material from the resist film for electrode formation;
The step of removing the resist film for electrode formation and leaving the electrode material deposited on the semiconductor layer out of the electrode material to form the electrode, the region of the electrode being A step of forming a recess around,
Including
In the step of forming the interlayer insulating film, a recess of the interlayer insulating film is formed corresponding to the recess formed around the electrode.
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 2,
The step of forming the electrode includes:
Forming a resist film for forming an electrode having an opening at a position where the electrode is formed on the semiconductor layer;
Depositing an electrode material from the resist film for electrode formation;
Performing wet etching using the electrode material as a mask and forming a recess around the electrode material deposited on the semiconductor layer;
Removing the resist film for electrode formation, leaving the electrode material deposited on the semiconductor layer among the electrode materials to be the electrode;
Including
In the step of forming the interlayer insulating film, a recess of the interlayer insulating film is formed corresponding to the recess formed around the electrode.
A method for manufacturing a semiconductor device, comprising:

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