JP5857569B2 - Light emitting element, light emitting element array, optical writing head, and image forming apparatus - Google Patents

Description

  The present invention relates to a light emitting element, a light emitting element array, an optical writing head, and an image forming apparatus.

  A surface light emitting element array is used for a writing head such as a contact image sensor or a printer. A typical surface light emitting element array is formed by integrating a plurality of light emitting elements arranged linearly on one substrate. As a typical surface light emitting device, a light emitting diode (LED), a light emitting thyristor, and a laser diode are known. In a light emitting diode, light emission in the active region is isotropic, only a portion of the emitted light is emitted from the top layer, and the light emitted to the substrate side is absorbed by the substrate. Therefore, there is a type in which a DBR mirror is formed on a substrate, absorption by the substrate is reduced, and light emission efficiency of the light emitting diode is improved (Patent Document 1).

  In addition, the light emitting thyristor forms a PNPN structure by stacking compound semiconductor layers (GaAs, AlGaAs, etc.), and applies a gate voltage and / or a gate current to the gate electrode, thereby injecting electrons injected from the anode electrode and the cathode electrode. -Emits light by bonding holes. There is one in which a short-circuit electrode is provided on a substrate so that the path of carriers injected from the upper electrode of the light emitting thyristor is shifted laterally from the upper electrode, and the series resistance of the element is reduced (Patent Document 2). . A self-scanning light-emitting element array in which a light-emitting thyristor array having such a PNPN structure is provided with a self-scanning function and each light-emitting thyristor is sequentially turned on has been put into practical use.

JP-A-5-275739 JP 2007-250961 A

  An object of the present invention is to provide a light emitting element and a light emitting element array with improved luminous efficiency.

According to a first aspect of the present invention, there is provided a substrate, a first semiconductor layer of a first conductivity type formed on the substrate, and a second second of a second conductivity type different from the first conductivity type formed on the first semiconductor layer. A semiconductor layer of the first conductivity type, a third semiconductor layer of the first conductivity type formed on the second semiconductor layer, a fourth semiconductor layer of the second conductivity type formed on the third semiconductor layer, A quantum well structure formed between the first to fourth semiconductor layers at a position where a forward bias is applied; a carrier barrier adjustment layer formed adjacent to the quantum well structure; and a first semiconductor layer A first electrode electrically connected, a second electrode electrically connected to the fourth semiconductor layer, and a gate electrode electrically connected to the second semiconductor layer or the third semiconductor layer When the and a current confinement portion formed in the semiconductor layer adjacent to the quantum well structure, the quantum well structure, the Located between the Yaria barrier regulation layer and the current confinement portion, the current confinement portion increases the density of one of the carrier, by injecting the one of the carriers in the quantum well structure, the band of the carrier barrier adjustment layer gap energy level for the one of the carrier the greater than the energy level of the barrier layer of quantum well structure, and the energy levels for the other carrier is adjusted to be equal to the energy level of the barrier layer, the light emitting element.
2. The light emitting device according to claim 1, wherein the energy level of the one carrier is adjusted to a size that allows the light emitting device to operate by allowing a certain leakage of the carrier.
According to a third aspect of the present invention, the current generated by the carriers leaked from the carrier barrier adjustment layer to the semiconductor layer is equal to or higher than a holding current at which the light-emitting thyristor can operate.
According to a fourth aspect of the present invention, the band gap of the carrier barrier adjusting layer is adjusted so that the energy level of the valence band for holes is higher than the energy level of the barrier layer of the quantum well structure. The light emitting element as described in any one.
5. The band gap of the carrier barrier adjusting layer is adjusted so that an energy level of a conduction band with respect to electrons is higher than an energy level of the barrier layer of the quantum well structure. The light emitting element as described in one.
6. The light emitting device according to any one of claims 1 to 5, wherein the quantum well structure is formed between an anode layer and a gate layer of a light emitting thyristor.
The light emitting device according to claim 1, wherein the quantum well structure is formed between a cathode layer and a gate layer of a light emitting thyristor.
Claim 8, wherein the current confinement portion is formed on the p-type semiconductor layer, the light emitting device according to claim 1.
Claim 9, columnar structure formed on said substrate, said current confinement portion includes a conductive region adjacent to the oxidized region and the oxidized region which is oxidized at least one side surface of the columnar structure, according to claim 1 Or the light emitting element of 8 .
A tenth aspect of the present invention is a light emitting element array in which a plurality of the light emitting elements according to any one of the first to ninth aspects are formed in an array on the semiconductor substrate.
11. The light emitting element array according to claim 10 , wherein the light emitting element array is a self-scanning light emitting element array.
A twelfth aspect is an optical writing head using the light emitting element array according to the tenth or eleventh aspect .
A thirteenth aspect of the present invention is an image forming apparatus comprising the optical writing head according to the twelfth aspect .

According to the first aspect, the amount of light emitted from the light emitting element can be increased.
According to the second, third, fourth, and fifth aspects, the operating characteristics of the light emitting element can be maintained.
According to claims 6 and 7, recombination of holes and electrons can be promoted.
According to the first aspect , the density of carriers injected into the quantum well structure can be increased.
According to the eighth aspect , it is possible to increase the density of hole carriers having a low mobility.
According to the ninth aspect , the current confinement portion can be formed by oxidation.
According to the tenth and eleventh aspects , the amount of light emitted from the light emitting element array can be increased.

1 is a schematic cross-sectional view of a light emitting thyristor according to a first embodiment of the present invention. It is the quantum well structure and carrier block adjustment layer energy band figure of the light emitting thyristor concerning the 1st example of the present invention. It is a figure which shows the other structural example of the light emitting thyristor which concerns on the 1st Example of this invention. It is a schematic sectional drawing of the light emitting thyristor which concerns on the 2nd Example of this invention. It is a quantum well structure and carrier block adjustment layer energy band figure of the light emitting thyristor concerning the 2nd example of the present invention. It is a schematic sectional drawing of the light emitting thyristor which concerns on the 3rd Example of this invention. It is a schematic sectional drawing of the light emitting thyristor which concerns on the 4th Example of this invention. It is a schematic plan view of the light emitting element array which has the light emitting thyristor based on the Example of this invention. FIG. 3 is an equivalent circuit diagram of a self-scanning light emitting thyristor array according to an embodiment of the present invention. It is an example which shows the structure of the optical writing head which applied the self-scanning light emitting element array of a present Example. This is an example in which the optical writing head using the self-scanning light emitting element array of this embodiment is applied to an optical printer.

  Next, embodiments of the present invention will be described with reference to the drawings. In this embodiment, a light emitting thyristor and a light emitting thyristor array are exemplified as the surface light emitting element. It should be noted that the scale of the drawings is emphasized for easy understanding of the features of the invention and is not necessarily the same as the scale of an actual device.

  FIG. 1 is a cross-sectional view showing the configuration of a light-emitting thyristor according to the first embodiment of the present invention, and FIG. 2 shows the energy of the quantum well layer and the carrier block adjustment layer of the light-emitting thyristor according to the first embodiment of the present invention. It is a band diagram.

  The light-emitting thyristor 10 of this example includes a p-type buffer layer 14, a p-type first semiconductor layer 16, a quantum well structure 20, an n-type second semiconductor layer 22, on a p-type semiconductor substrate 12. The p-type third semiconductor layer 26 and the n-type fourth semiconductor layer 28 are sequentially grown by epitaxial growth. The semiconductor substrate 12 and the semiconductor layer laminated thereon are preferably made of a III-V group compound semiconductor. Here, the semiconductor substrate 12 and the semiconductor layer laminated thereon are made of GaAs, AlGaAs or AlAs series. Consists of

  A back electrode 30 is formed as an anode side electrode on the back surface of the semiconductor substrate 12, and an upper electrode 32 is formed as a cathode side electrode on the fourth semiconductor layer 28. A gate electrode 34 is formed on the third semiconductor layer 26, and a drive signal is applied to the gate electrode 34 when the light emitting thyristor 10 is self-scanned.

In a preferred example of this embodiment, a p-type GaAs buffer layer 14 is formed on a p-type GaAs substrate 12, and a first semiconductor layer 16 as an anode layer is formed on the buffer layer 14. . The first semiconductor layer 16 is composed of p-type AlGaAs, and AlAs having a relatively high Al composition ratio or AlGaAs having a very high Al composition ratio (for example, an Al composition having a composition of 98% or more). A current confinement portion 18 made of Al _0.98 Ga _0.22 As) is formed. The current confinement portion 18 includes an oxidized region 18A that is selectively oxidized, and a conductive region 18B that is adjacent to or surrounded by the oxidized region 18A.

  In a preferred example, when the light emitting thyristor 10 is manufactured, the mesa M1 is formed so that at least one side surface of the first semiconductor layer 16 is exposed, and the current confinement portion 18 is selectively oxidized from the side surface of the mesa M1. Is done. The remaining first semiconductor layer 16 excluding the current confinement portion 18 has an Al composition much smaller than that of the current confinement portion 18. Therefore, unlike the current confinement portion 18, oxidation does not proceed from the side surface of the mesa M <b> 1.

  When the mesa M1 is formed in a rectangular shape or a cylindrical shape, an oxidized region 18A reflecting the outer shape of the mesa M1 is formed. In the example shown in FIG. 1, a conductive region 18B surrounded by the oxidized region 18A is formed. The oxidized region 18A is a high resistance region, and carriers (holes) injected from the anode side pass through the conductive region 18B having a limited area, and the carrier density is increased. In the above example, the current confinement portion 18 is sandwiched by AlGaAs having a low Al composition. However, the current confinement portion 18 is adjacent to the quantum well structure 20 so as to be adjacent to the quantum well structure 20. It may be formed as an upper layer. Further, although the current confinement portion 18 is formed by selective oxidation, the high resistance region 18A may be formed by ion implantation instead.

A quantum well structure 20 is formed between the first semiconductor layer 16 and the second semiconductor layer 22, that is, at a position that becomes a forward bias in the light emitting thyristor 10. The quantum well structure 20 may be a single quantum well structure (SQW) or a multiple quantum well structure (MQW). The quantum well structure 20 includes, for example, an undoped Al _0.11 Ga _0.89 As quantum well layer and an undoped Al _0.3 Ga _0.7 As barrier layer.

On the quantum well structure 20, a second semiconductor layer 22 made of n-type AlGaAs as a gate layer is formed with a predetermined film thickness and a predetermined dopant concentration. Part of the second semiconductor layer 22 is formed with a carrier block adjustment layer 24 that substantially has no energy barrier against electrons and functions to have an energy barrier against holes during the operation of the light-emitting thyristor 10. . Preferably, the carrier block adjustment layer 24 is made of n-type Al _x Ga _1-x As (0 <X <1) having a constant film thickness and is formed adjacent to the quantum well structure 20. The carrier block adjustment layer 24 forms an energy barrier that adjusts the amount of carriers (holes) from the quantum well structure 20 toward the reverse-biased junction while confining holes in the quantum well structure 20, and increases the energy barrier. The thickness can be determined by the Al composition ratio (X). The reason why the carrier block adjusting layer 24 causes the holes to overflow or leak is to maintain the characteristics of the light emitting thyristor, as will be described later.

  A third semiconductor layer 26 made of p-type AlGaAs as a gate layer is formed on the second semiconductor layer 22 with a predetermined film thickness and a predetermined dopant concentration. Further, on the third semiconductor layer 26, A fourth semiconductor layer 28 made of n-type AlGaAs as a cathode layer is formed with a predetermined film thickness and a predetermined dopant concentration. Preferably, a part of the fourth semiconductor layer 28 and the third semiconductor layer 26 is etched to form, for example, a rectangular mesa M2 on the mesa M1. A gate electrode 34 is formed on the third semiconductor layer 26 whose surface is exposed by the mesa M2.

  On the fourth semiconductor layer 28, an upper electrode 32 as a cathode electrode is formed. An n-type GaAs contact layer 28A having a high impurity concentration may be formed on the uppermost layer of the fourth semiconductor layer 28, and the contact layer 28A can be ohmically connected to the upper electrode 34. The upper electrode 32 is preferably formed substantially at the center of the mesa M2, and it is desirable that a part or all of the upper electrode 32 overlap with the conductive region 18B of the mesa M2. The back electrode 30, the upper electrode 32, and the gate electrode 34 are formed by a single layer or a stack of metal materials such as Au, AuGe, Ni, Ti, and Mo, for example, by lift-off. Thus, the light emitting thyristor 10 having a three-terminal structure is formed.

  Next, the energy band structure of the quantum well structure 20 and the carrier block adjustment layer 24 will be described. FIG. 2 is a diagram for explaining the band gap of the carrier block adjusting layer 24 when the light-emitting thyristor 10 is operated, that is, when a forward bias is applied between the anode and the cathode. The quantum well structure 20 includes a quantum well layer 20A having a small band gap and a barrier layer (barrier layer) 20B having a large band gap formed on both sides of the quantum well layer 20A so as to sandwich the quantum well layer 20A. Is done. However, the barrier layer 20B on the both sides may be referred to as a spacer layer. The band gap of the carrier block adjusting layer 24 is such that the energy level of the conduction band Ec for electrons is substantially equal to the energy level of the barrier layer 20B of the quantum well structure 20, and the energy level of the valence band Ev for holes is that of the quantum well structure 20. It is adjusted to be higher than the energy level of the barrier layer 20B by the barrier ΔEv. That is, during the operation of the light emitting thyristor 10, the conduction band Ec between the second semiconductor layer 22 and the barrier layer 20B is continuous, the barrier between them is substantially zero, and the electrons are contained in the quantum well layer 20A. Injected efficiently. Further, there is a barrier ΔEc between the barrier layer 20B and the p-type first semiconductor layer 16, and leakage or overflow of electrons from the barrier layer 20B to the first semiconductor layer 16 is suppressed by the barrier ΔEc. The

On the other hand, during the operation of the light emitting thyristor 10, the valence band Ev between the p-type first semiconductor layer 16 and the barrier layer 20B is continuous, the barrier between them is substantially zero, and the holes are The first semiconductor layer 16 is efficiently injected into the quantum well layer 20A. Further, the carrier blocking layer 24 forms a barrier ΔEv in the valence band Ev between the barrier layer 20B and the size of the barrier ΔEv is such that a part of the holes overflows the barrier ΔEv, It is set so as to be leaked to the second semiconductor layer 22. ΔEv can be adjusted by appropriately selecting the material constituting the carrier block adjustment layer 24. In this example, the Al composition ratio of Al _x Ga _1-x As constituting the carrier block adjustment layer 24 ( Adjust X). That is, if the Al composition ratio is increased, the barrier ΔEv can be increased accordingly, and the amount of carriers in which holes overflow the barrier ΔEv can be reduced. Preferably, the magnitude of the barrier ΔEv is adjusted so that the anode current due to the overflowed hole becomes equal to or larger than the holding current necessary for turning on (igniting) the light emitting thyristor 10.

  Next, the operation of the light emitting thyristor 10 will be described. When a forward bias drive signal that is equal to or higher than the diffusion potential of the pn junction is applied to the gate electrode 34 in a state where the forward bias is applied to the back electrode 30 and the upper electrode 32, a gate current flows, which triggers Thus, current flows between the anode and the cathode, and the light emitting thyristor 10 is turned on (ignited). Carriers (holes) injected from the first semiconductor layer 16 are increased in carrier density by the current confinement part 18, and carriers (holes) having a high density are injected into the quantum well layer 20A. Most of the holes are confined in the quantum well layer 20A, but a part of the holes overflowing the quantum well layer 20A overflows or leaks to the second semiconductor layer 22 over the barrier ΔEv. Thus, a holding current necessary for the light emitting thyristor 10 is generated.

  On the other hand, the electrons injected from the second semiconductor layer 22 are injected into the quantum well layer 20A, but the electrons are prevented from overflowing to the first semiconductor layer 16 by the barrier ΔEc, and the quantum well layer 20A. Trapped inside. In this way, in the quantum well layer 20A, the combination of electrons and holes is promoted, the light emission efficiency is improved, and light with an increased amount of emitted light can be obtained from the uppermost layer.

  In a typical light-emitting thyristor having no quantum well structure, light is emitted by combining electrons and holes in the second semiconductor layer 22 as an n-gate layer and the third semiconductor layer 26 as a p-gate layer. However, the total thickness of the n gate and the p gate is about 1 μm, and the space in which carriers are present becomes relatively large. Therefore, the carrier concentration is reduced, and the probability of coupling between holes and electrons is reduced. Furthermore, when the carrier concentration is low, light absorption is likely to occur. On the other hand, in the present embodiment, by using the quantum well structure 20, the carrier density of holes and electrons can be increased, and the coupling probability of both can be increased. Further, by providing the current confinement portion 18 in the semiconductor layer 16 adjacent to the quantum well structure 20, the carrier density of holes having low mobility with respect to electrons is increased, and a large amount of holes are injected into the quantum well structure 20. can do.

  As a problem specific to the light emitting thyristor, in order to turn on the light emitting thyristor, a certain holding current must flow between the anode and the cathode. In other words, some of the holes injected from the first semiconductor layer 16 into the quantum well structure 20 are used for light emission, and the rest are injected into the second semiconductor layer 22 without being used for light emission. Must be used for thyristor holding current. In this embodiment, the carrier block adjustment layer 24 sets a barrier ΔEv such that a part of holes leaks to the second semiconductor layer 16.

  The leakage current due to holes overflowing from the barrier ΔEv is preferably equal to or higher than the holding current of the light emitting thyristor. In general, the magnitude of the holding current is about 3% of the drive current of the thyristor. Since the leakage current varies depending on the use conditions (drive current and operating temperature) of the light emitting thyristor, the barrier ΔEv takes into consideration the range of use conditions, for example, the maximum and minimum drive current and operating temperature allowed for the light emitting thyristor. Determined.

  FIG. 3 is a diagram showing another modification of the light-emitting thyristor 10 of the first embodiment. In the light emitting thyristor 10, the upper electrode 32 is formed in a link shape or an annular shape, and light is extracted from the opening of the upper electrode 32. Preferably, the light generated efficiently in the central portion of the mesa M1 can be extracted from the uppermost layer by overlapping the opening of the upper electrode 32 with part or all of the conductive region 18B of the current confinement portion 18. Further, the current confinement portion 18 has an oxidized region 18A oxidized from one side surface of the mesa M1.

  In the above embodiment, the current confinement portion 18 is formed in the first semiconductor layer 16. However, the present invention is not limited to this, and the current confinement portion is formed in the second to fourth semiconductor layers. In this case, the number of current confinement portions is not limited to one and may be plural.

  Next, a second embodiment of the present invention will be described. FIG. 4 shows a cross section of the light emitting thyristor 10A according to the second embodiment. The difference from the first embodiment is that, in the second embodiment, the quantum well structure 20 is formed between the third semiconductor layer 26 and the fourth semiconductor layer 28, that is, at a position that is forward-biased. Is done. In this case, the current confinement portion 18 and the carrier block adjustment layer 24 are formed in the p-type third semiconductor layer 26, and the carrier block adjustment layer 24 is formed adjacent to the quantum well structure 20. The current confinement portion 18 includes an oxidized region 18A selectively oxidized from one side surface or a plurality of side surfaces of the mesa M2, and a conductive region 18B adjacent to or surrounded by the oxidized region 18A. . In the illustrated example, the current confinement portion 18 includes an oxidized region 18A that is oxidized from one side surface of the mesa M2.

  FIG. 5 is a diagram for explaining the energy band structure of the carrier block adjustment layer 24 when the light-emitting thyristor 10A according to the second embodiment is operated. In the second embodiment, unlike the first embodiment, the band gap of the carrier block adjustment layer 24 is such that the energy level of the conduction band Ec with respect to carriers (electrons) is higher by the barrier ΔEc than the barrier layer 20B. The energy level of the valence band Ev with respect to the holes is adjusted to be substantially equal to the energy level of the barrier layer 20B.

  That is, when a forward bias is applied by the gate electrode 34, the valence band Ec between the p-type third semiconductor layer 26 and the barrier layer 20B is continuous, and the barrier therebetween is substantially zero. In addition, the holes are efficiently injected into the quantum well layer 20A without substantially exceeding the barrier. Further, there is a barrier ΔEv between the barrier layer 20B and the fourth semiconductor layer 28, and this barrier ΔEv prevents leakage or overflow of holes from the quantum well layer 20A to the fourth semiconductor layer 16. .

  On the other hand, electrons injected from the fourth semiconductor layer 28 are efficiently injected into the quantum well layer 20A and confined. The carrier blocking layer 24 forms a barrier ΔEc with the barrier layer 20B, and the magnitude of the barrier ΔEc is adjusted so that a part of the electrons overflows beyond the barrier ΔEc. The barrier ΔEc of the carrier block adjustment layer 24 is performed by adjusting the Al composition ratio (X), as in the first embodiment, and preferably the electron current is set to be equal to or higher than the holding current of the light emitting thyristor. Overflow or leakage current is adjusted.

  Next, a third embodiment of the present invention will be described. FIG. 6 shows a schematic cross section of a light emitting thyristor 10B of the third embodiment. The light-emitting thyristor 10B according to the third embodiment uses an n-type GaAs semiconductor substrate, and is obtained by inverting the anode and the cathode in the first embodiment. A light-emitting thyristor 10B according to the third embodiment includes an n-type GaAs buffer layer 14, an n-type AlGaAs first semiconductor layer 16 serving as a cathode layer, an n-type GaAs semiconductor substrate 12, and a first semiconductor layer 16; Quantum well structure 20 on semiconductor layer 16, second semiconductor layer 22 made of p-type AlGaAs, third semiconductor layer 26 made of n-type AlGaAs, and fourth semiconductor made of p-type AlGaAs as an anode layer It has a layer 28. The quantum well structure 20 is formed at a position where the second semiconductor layer 22 and the first semiconductor layer 16 are forward biased, and the carrier block adjustment layer 24 in the second semiconductor layer 22 is adjacent to the quantum well structure 20. To do. Further, in the second semiconductor layer 22, a current confinement portion 18 having an oxidized region 18A selectively oxidized from one side surface of the mesa M1 and a conductive region 18B adjacent thereto is formed. As in the second embodiment (see FIG. 4), the energy level of the conduction band Ec with respect to carriers (electrons) is higher by the barrier ΔEc than the barrier layer 20B. The energy level of the valence band Ev with respect to the holes is adjusted to be substantially equal to the energy level of the barrier layer of the barrier layer 20B.

  Next, a fourth embodiment of the present invention will be described. FIG. 7 shows a schematic cross section of a light emitting thyristor 10C of the fourth embodiment. In the fourth embodiment, the quantum well structure 20 is formed at a forward bias position between the fourth semiconductor layer 28 and the third semiconductor layer 26. In this case, the current confinement portion 18 including the oxidized region 18A oxidized from the side surface of the mesa M2 is formed in the fourth semiconductor layer 28. A carrier block adjustment layer 24 is formed on the third semiconductor layer 26 so as to be adjacent to the quantum well structure 20. As in the first embodiment (see FIG. 2), the band gap of the carrier block adjusting layer 24 is higher by the barrier ΔEc than the barrier layer 20B because the energy level of the valence band for holes is higher than that of the barrier layer 20B. The energy level of the conduction band is adjusted to be substantially equal to that of the barrier layer 20B.

  Note that when the current confinement portion 18 is formed in the mesa M2, the mesa M1 is not necessarily required. In the above embodiment, the mesa M1 and M2 as the columnar structures are processed into a rectangular shape. However, the mesa M1 and M2 may have other shapes, for example, a columnar shape. Further, the sizes of the mesas M1 and M2 can be appropriately selected according to the size of the upper electrode 32, the size of the conductive region 18B of the current confinement portion 18, and the like.

  FIG. 8 is a schematic plan view of a self-scanning light emitting element array using the light emitting thyristor of the present embodiment. As shown in the figure, on a single semiconductor substrate, a plurality of light emitting thyristors 10-1, 10-2... 10-n and a shift unit 60 that scans each light emitting thyristor are formed. The plurality of light emitting thyristors 10-1 to 10-n are linearly arranged, and the upper electrodes (cathode electrodes) 32-1 to 32-n of each light emitting thyristor extend in parallel to the arrangement direction of the light emitting thyristors. Connected to layer 38. .., 34-n are supplied with drive signals 62-1, 62-2,... 62-n from the shift unit 60, respectively. The light emitting thyristor is sequentially scanned by applying a driving signal to the gate electrode.

FIG. 9 is an equivalent circuit diagram of the self-scanning light emitting element array. Here, four light emitting thyristors L1 to L4 are illustrated. Shift unit 60 is configured to include a transfer thyristor T1-T4, a diode D1 to D3, and a resistor _{R G.} The transfer control signal Φ1 is connected to the cathodes of the odd transfer thyristors T1 and T3, the transfer control signal Φ2 is connected to the cathodes of the even transfer thyristors T2 and T4, and the two transfer control signals Φ1 and Φ2 are alternately , Pulled down to the cathode potential. The light emission signal Φ for supplying a potential corresponding to the data “0” and “1” is commonly connected to the cathodes of the light emitting thyristors L1 to L4. The gates of the light emitting thyristors L1 to L4 and the transfer thyristors T1 to T4 are common, and each gate is connected to a resistor _RG . Further, diodes D1 to D3 are connected between adjacent gates, respectively.

Here, it is assumed that the transfer thyristor T2 is in the ON state. At this time, the transfer control signal Φ2 is a cathode potential, and the transfer control signal Φ1 is a ground potential. A trigger potential Vs larger than the gate / cathode bias voltage is applied to the gate of the transfer thyristor T2. Since the trigger potential Vs is also applied to the light emitting thyristor L2, the light emitting thyristor L2 is fired or extinguished according to the data “1” and “0” of the light emission signal Φ. A potential V2 that is lower than the trigger potential Vs by the diffusion potential of the diodes D2 and D3 is applied to the gate of the transfer thyristor T4 that commonly connects the transfer control signal Φ2, and this potential V2 Thus, the transfer thyristor T4 and the light emitting thyristor L4 are extinguished. A potential V1 (V1> V2) that is lower than the trigger potential Vs by the diffusion potential of the diode D2 is applied to the gate of the adjacent transfer thyristor T3, and this potential V1 is a bias voltage between the gate and the cathode. Bigger than. Therefore, the transfer thyristor T3 is fired next time when the transfer control signal Φ1 is lowered to the cathode potential. Further, the trigger potential Vs is not applied by the diode D1 to the gate of the transfer thyristor T1, and the power supply _VGA is supplied. Since this potential is smaller than the bias voltage between the gate and the cathode, the next transfer control signal Φ1 Even if is lowered to the cathode potential, the transfer thyristor T1 is not ignited. Thus, by alternately driving the transfer control signals Φ1 and Φ2 to the cathode potential, the transfer thyristors are sequentially self-scanned, and the light emitting thyristors are fired or extinguished. The detailed configuration and operation of the shift unit are described in, for example, Japanese Patent Laid-Open No. 1-238962. In the above example, an example of an array in which light emitting thyristors are arranged in a one-dimensional direction is shown, but the light emitting thyristor array may be one in which light emitting thyristors are arranged in two dimensions.

  The self-scanning light emitting element array as described above is used, for example, in an optical writing head of an optical printer. FIG. 10 shows an example of an optical writing head using a self-scanning light emitting element array. A plurality of light emitting element array chips 71 in which light emitting thyristors are arranged in a row on a chip mounting substrate 70 are mounted in the main scanning direction, and on the optical path of light emitted by the light emitting elements of the light emitting element array chip 71, An erecting equal-magnification rod lens array 72 that is long in the main scanning direction is fixed by a resin housing 73. A photosensitive drum 74 is provided on the optical axis of the rod lens array 72. Further, a heat sink 75 for releasing heat of the light emitting element array chip 71 is provided on the base of the chip mounting substrate 70, and the housing 73 and the heat sink 75 are fixed by a fastener 76 with the chip mounting substrate 70 interposed therebetween. ing.

  An optical printer using the optical writing head shown in FIG. 10 is shown in FIG. An optical writing head 100 is installed in the optical printer. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 102. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged by the charger 104. Then, the optical writing head 100 irradiates the photosensitive member with the light of the dot image to be printed, neutralizes the charge where the light hits, and forms a latent image. Subsequently, the developing device 106 applies toner to the photoconductor according to the charged state on the photoconductor. The transfer device 108 transfers the toner onto the paper 112 sent from the cassette 110. The sheet is heated and fixed by the fixing device 114 and sent to the stacker 116. On the other hand, the drum that has been transferred is neutralized by the erasing lamp 118 over the entire surface, and the remaining toner is removed by the cleaner 120. Such an optical writing head can be used not only in a printer but also in an image forming apparatus such as a facsimile machine and a copying machine.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims. Deformation / change is possible.

10, 10A, 10B, 10C: Light-emitting thyristor 12: Semiconductor substrate 14: Buffer layer 16: First semiconductor layer 18: Current constriction 18A: Oxidized region 18B: Conductive region 20: Quantum well structure 20A: Quantum well layer 20B: Barrier layer 22: second semiconductor layer 24: carrier block adjustment layer 26: third semiconductor layer 28: fourth semiconductor layer 28A: contact layer 30: back electrode 32: upper electrode 34: gate electrodes M1, M2: mesa

Claims (13)

A substrate,
A first semiconductor layer of a first conductivity type formed on the substrate;
A second semiconductor layer of a second conductivity type different from the first conductivity type formed on the first semiconductor layer;
A third semiconductor layer of the first conductivity type formed on the second semiconductor layer;
A fourth semiconductor layer of the second conductivity type formed on the third semiconductor layer;
A quantum well structure formed between the first to fourth semiconductor layers at a position to be forward biased;
A carrier barrier adjustment layer formed adjacent to the quantum well structure;
A first electrode electrically connected to the first semiconductor layer;
A second electrode electrically connected to the fourth semiconductor layer;
A gate electrode electrically connected to the second semiconductor layer or the third semiconductor layer;
A current confinement portion formed in the semiconductor layer adjacent to the quantum well structure ;
The quantum well structure is located between the carrier barrier adjustment layer and the current confinement portion, the current confinement portion increases the density of one carrier, injects the one carrier into the quantum well structure,
A band gap of the carrier barrier adjustment layer, the energy level is larger than the energy level of the barrier layer of the quantum well structure for said one carrier, and the energy levels for the other carriers equal to the energy level of the barrier layer The light emitting element is adjusted as follows. The light emitting device according to claim 1, wherein the energy level of the one carrier is adjusted to a size that allows the light emitting device to operate by allowing a certain leakage of the carrier. 3. The light emitting device according to claim 1, wherein a current generated by carriers leaked from the carrier barrier adjustment layer to the semiconductor layer is equal to or higher than a holding current at which the light emitting thyristor can operate. 4. The band gap of the carrier barrier adjustment layer is adjusted so that an energy level of a valence band with respect to holes is higher than an energy level of the barrier layer of the quantum well structure. The light emitting element of description. 4. The band gap of the carrier barrier adjustment layer is adjusted so that an energy level of a conduction band with respect to electrons is higher than an energy level of the barrier layer of the quantum well structure. Light emitting element. The light emitting device according to claim 1, wherein the quantum well structure is formed between an anode layer and a gate layer of a light emitting thyristor. The light emitting device according to claim 1, wherein the quantum well structure is formed between a cathode layer and a gate layer of a light emitting thyristor. The light emitting device according to claim 1 , wherein the current confinement portion is formed in a p-type semiconductor layer. Columnar structure is formed on the substrate, wherein the current confinement portion includes a conductive region adjacent to the at least one oxidation area and the oxidized region which is oxidized from the side surface of the columnar structure of claim 1 or 8 Light emitting element. The light emitting device according to 9 any one claims 1 is formed in a plurality of numbers in an array on the semiconductor substrate, the light-emitting element array. The light emitting element array according to claim 10, wherein the light emitting element array is a self-scanning light emitting element array. An optical writing head using the light emitting element array according to claim 10 . An image forming apparatus comprising the optical writing head according to claim 12 .

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