JP2013021229A - 電子部品とその製造方法 - Google Patents
電子部品とその製造方法 Download PDFInfo
- Publication number
- JP2013021229A JP2013021229A JP2011154928A JP2011154928A JP2013021229A JP 2013021229 A JP2013021229 A JP 2013021229A JP 2011154928 A JP2011154928 A JP 2011154928A JP 2011154928 A JP2011154928 A JP 2011154928A JP 2013021229 A JP2013021229 A JP 2013021229A
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- JP
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- Prior art keywords
- semiconductor chip
- spring
- resin
- electronic component
- heat spreader
- Prior art date
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】パッケージ基板8と、パッケージ基板8上に配置された半導体チップ9と、バネ23を介して半導体チップ9と接続されたヒートスプレッダ15とを有する電子部品による。
【選択図】図5
Description
前記パッケージ基板上に配置された半導体チップと、
バネを介して前記半導体チップと接続されたヒートスプレッダと、
を有することを特徴とする電子部品。
前記バネは前記樹脂に埋設されていることを特徴とする付記1に記載の電子部品。
前記バネの他方の端部は前記ヒートスプレッダと接続されていることを特徴とする付記1〜3のいずれかに記載の電子部品。
前記パッケージ基板と対向して設けられ、前記LGAコネクタを介して前記パッケージ基板と電気的に接続された配線基板とを更に有することを特徴とする付記1〜5のいずれかに記載の電子部品。
複数の前記バネの上に、パッケージ基板上に配置された半導体チップを載せる工程と、
前記型枠の中に液状の樹脂を注入する工程と、
前記樹脂を硬化させる工程と、
硬化した前記樹脂から前記型枠を除去することにより、前記底に接していた部分の前記樹脂の表面を露出させる工程と、
前記樹脂の前記表面にヒートスプレッダを押圧することにより、前記バネと前記半導体チップとを熱的に接続する工程と、
を有することを特徴とする電子部品の製造方法。
Claims (5)
- パッケージ基板と、
前記パッケージ基板上に配置された半導体チップと、
バネを介して前記半導体チップと接続されたヒートスプレッダと、
を有することを特徴とする電子部品。 - 樹脂を更に有し、
前記バネは前記樹脂に埋設されていることを特徴とする請求項1に記載の電子部品。 - 前記バネの一方の端部は前記半導体チップと接続され、
前記バネの他方の端部は前記ヒートスプレッダと接続されていることを特徴とする請求項1又は請求項2に記載の電子部品。 - 前記バネの材料は超弾性合金であることを特徴とする請求項1乃至請求項3のいずれか1項に記載の電子部品。
- 型枠の底に複数のバネを立てる工程と、
複数の前記バネの上に、パッケージ基板上に配置された半導体チップを載せる工程と、
前記型枠の中に液状の樹脂を注入する工程と、
前記樹脂を硬化させる工程と、
硬化した前記樹脂から前記型枠を除去することにより、前記底に接していた部分の前記樹脂の表面を露出させる工程と、
前記樹脂の前記表面にヒートスプレッダを押圧することにより、前記バネと前記半導体チップとを熱的に接続する工程と、
を有することを特徴とする電子部品の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011154928A JP2013021229A (ja) | 2011-07-13 | 2011-07-13 | 電子部品とその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011154928A JP2013021229A (ja) | 2011-07-13 | 2011-07-13 | 電子部品とその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2013021229A true JP2013021229A (ja) | 2013-01-31 |
Family
ID=47692353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011154928A Pending JP2013021229A (ja) | 2011-07-13 | 2011-07-13 | 電子部品とその製造方法 |
Country Status (1)
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JP (1) | JP2013021229A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015115413A (ja) * | 2013-12-10 | 2015-06-22 | キヤノン株式会社 | インプリント装置及び物品の製造方法 |
JP2017194799A (ja) * | 2016-04-19 | 2017-10-26 | 富士通株式会社 | 液冷サーバ |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02132955U (ja) * | 1989-04-07 | 1990-11-05 | ||
JPH1050904A (ja) * | 1996-08-06 | 1998-02-20 | Advantest Corp | 伝熱素子 |
JP2004193387A (ja) * | 2002-12-12 | 2004-07-08 | Mitsumi Electric Co Ltd | 電子部品の放熱装置 |
US20060087015A1 (en) * | 2004-10-27 | 2006-04-27 | Freescale Semiconductor Inc. | Thermally enhanced molded package for semiconductors |
JP2007073744A (ja) * | 2005-09-07 | 2007-03-22 | Nec Personal Products Co Ltd | 放熱構造体、電子機器 |
US20070108587A1 (en) * | 2005-04-22 | 2007-05-17 | Stats Chippac Ltd. | Integrated circuit package system with a heat sink |
-
2011
- 2011-07-13 JP JP2011154928A patent/JP2013021229A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02132955U (ja) * | 1989-04-07 | 1990-11-05 | ||
JPH1050904A (ja) * | 1996-08-06 | 1998-02-20 | Advantest Corp | 伝熱素子 |
JP2004193387A (ja) * | 2002-12-12 | 2004-07-08 | Mitsumi Electric Co Ltd | 電子部品の放熱装置 |
US20060087015A1 (en) * | 2004-10-27 | 2006-04-27 | Freescale Semiconductor Inc. | Thermally enhanced molded package for semiconductors |
US20070108587A1 (en) * | 2005-04-22 | 2007-05-17 | Stats Chippac Ltd. | Integrated circuit package system with a heat sink |
JP2007073744A (ja) * | 2005-09-07 | 2007-03-22 | Nec Personal Products Co Ltd | 放熱構造体、電子機器 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015115413A (ja) * | 2013-12-10 | 2015-06-22 | キヤノン株式会社 | インプリント装置及び物品の製造方法 |
JP2017194799A (ja) * | 2016-04-19 | 2017-10-26 | 富士通株式会社 | 液冷サーバ |
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