TWM593647U - 具有熱管理之堆疊矽封裝組件 - Google Patents
具有熱管理之堆疊矽封裝組件 Download PDFInfo
- Publication number
- TWM593647U TWM593647U TW108211759U TW108211759U TWM593647U TW M593647 U TWM593647 U TW M593647U TW 108211759 U TW108211759 U TW 108211759U TW 108211759 U TW108211759 U TW 108211759U TW M593647 U TWM593647 U TW M593647U
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- substrate
- chip package
- cover
- disposed
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 2
- 229910052710 silicon Inorganic materials 0.000 title description 2
- 239000010703 silicon Substances 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000000945 filler Substances 0.000 claims description 53
- 239000004020 conductor Substances 0.000 claims description 43
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000002787 reinforcement Effects 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000000843 powder Substances 0.000 claims description 4
- 239000000835 fiber Substances 0.000 claims description 2
- 239000002923 metal particle Substances 0.000 claims description 2
- 210000002268 wool Anatomy 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 31
- 239000000463 material Substances 0.000 description 24
- 239000010949 copper Substances 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000012782 phase change material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000007641 inkjet printing Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 101710149792 Triosephosphate isomerase, chloroplastic Proteins 0.000 description 1
- 101710195516 Triosephosphate isomerase, glycosomal Proteins 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003856 thermoforming Methods 0.000 description 1
- 238000007514 turning Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/1631—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/1632—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/164—Material
- H01L2924/165—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
提供一種晶片封裝組件及其製造方法,其利用複數個附加晶粒熱傳遞柱以用於改良熱管理。在一個實例中,提供一種晶片封裝組件,其包括:一第一積體電路(IC)晶粒,其安裝至一基板;一罩蓋,其安置於該第一IC晶粒上方;及複數個附加晶粒傳導柱,其安置於該罩蓋與基板之間。該等附加晶粒傳導柱在該罩蓋與基板之間提供在該第一IC晶粒外部橫向延伸之一熱傳遞路徑。
Description
本新型之具體實例大體上關於一種晶片封裝組件,且詳言之,關於一種包含至少安置在封裝基板或內插件上之積體電路(integrated circuit;IC)晶粒及複數個附加晶粒熱傳遞柱的晶片封裝組件。
諸如平板電腦、電腦、影印機、數位攝影機、智慧型電話、控制系統及自動化櫃員機等之電子裝置經常採用充分利用晶片封裝組件之能力的電子組件,以用於提高的功能性及較高的組件密度。習知的晶片封裝方案經常利用封裝基板,經常結合矽穿孔(through-silicon-via;TSV)內插件,以使得複數個積體電路(IC)晶粒能夠安裝至單一封裝基板。IC晶粒可包含記憶體、邏輯或其他IC裝置。
在許多晶片封裝組件中,提供充足熱管理變得越來越具有挑戰性。未能提供充足冷卻經常使得使用壽命減少並且甚至引起裝置故障。熱管理尤其在高頻寬記憶體(high band-width memory;HBM)及諸如場可程式化閘陣列(field programmable gate array;FPGA)之邏輯晶粒整合於單一封裝組件中之應用中是成問題的。在此類應用中,記憶體及邏輯晶粒可在極接近熱接面溫度限制之溫度下操作。因此,諸如因空調機故障產生之環境溫度的小波動可能會快速地導致超過熱接面溫度限制,從而引起裝置故障或系統停機。
因此,需要一種具有經改良的熱管理之晶片封裝組件。
本文中記載一種晶片封裝組件及其製造方法,其利用複數個附加晶粒熱傳遞柱以用於改良熱管理。在一個實例中,提供一種晶片封裝組件,其包括:一第一積體電路(IC)晶粒,其安裝至一基板;一罩蓋,其安置於該第一IC晶粒上方;及複數個附加晶粒傳導柱,其安置於該罩蓋與基板之間。該等附加晶粒傳導柱在該罩蓋與基板之間提供在該第一IC晶粒外部橫向延伸之熱傳遞路徑。
在另一實例中,提供一種晶片封裝組件,其包括一基板、安裝至該基板之至少一第一記憶體晶粒、安裝並通信耦接至該基板之至少一第一邏輯晶粒、安置於該第一記憶體晶粒及該第一邏輯晶粒上方之一罩蓋、安置於該第一記憶體晶粒及該第一邏輯晶粒周圍之一介電材料,及一第一傳導柱。該介電材料安置於該基板與該罩蓋之間。該第一傳導柱安置於穿過該介電材料形成之一孔中,並且在該罩蓋與基板之間提供一熱傳遞路徑。
在又另一實例中,提供一種用於製造一晶片封裝組件之方法。該方法包括將一第一積體電路(IC)晶粒安裝至一基板、在該基板上之該第一IC晶粒外部形成附加晶粒導熱柱,及在該第一IC晶粒及該等附加晶粒傳導柱上方安裝一罩蓋。
在另一實例中,該用於製造一晶片封裝組件之方法亦可包括在安置於該第一IC晶粒周圍之一介電材料中形成一孔,及當形成該等附加晶粒導熱柱時用一塊狀導熱層填充該孔。
在另一實例中,該用於製造一晶片封裝組件之方法亦可包括將該等附加晶粒傳導柱沈積在該基板上,及當形成該等附加晶粒導熱柱時在該等附加晶粒傳導柱及該第一IC晶粒周圍沈積一塊狀導熱層。
提供一種晶片封裝組件及其製造方法,其利用安置於積體電路(IC)晶粒周圍之複數個附加晶粒熱傳遞柱。本文中所描述之晶片封裝組件包括安置在基板上之至少一個積體電路(IC)晶粒及罩蓋。該基板可為封裝基板或內插件。形容詞「附加晶粒」描述該等柱不延伸通過IC晶粒並且在IC晶粒外部橫向延伸。附加晶粒熱傳遞柱在罩蓋與基板之間提供穩健的熱傳遞路徑。儘管本文中提供之實例說明安置於罩蓋與呈內插件形式之基板之間的附加晶粒熱傳遞柱,但附加晶粒熱傳遞柱可在不利用內插件之具體實例中替代地安置於罩蓋與呈封裝基板形式之基板之間。有利地,至晶片封裝組件之罩蓋的增強的熱傳遞會改良可靠性及效能。此外,附加晶粒熱傳遞柱可經配置以例如藉由在一個區上使用比在另一區上還多之柱來增強橫越整個晶片封裝組件之熱傳遞,從而縮減可能誘發翹曲或提供IC晶粒之不充分溫度控制的熱點。另外,附加晶粒熱傳遞柱自內插件移除熱量之能力顯著地縮減晶片封裝組件內之熱耦合及溫度上升,從而有利地提高電遷移(electromigration;EM)壽命。
現在轉而參看圖1,示意性地說明具有安置於積體電路(IC)晶粒106周圍之複數個附加晶粒熱傳遞柱110的晶片封裝組件100之示意性截面視圖。晶片封裝組件100亦包括罩蓋102、內插件104及封裝基板108。
儘管圖1中展示兩個IC晶粒106,但IC晶粒之總數目可介於兩個至可裝配在晶片封裝組件100內之數量的範圍內。可用於晶片封裝組件100中之IC晶粒106之實例包括但不限於諸如場可程式化閘陣列(FPGA)之可程式化邏輯裝置、諸如高頻寬記憶體(HBM)之記憶體裝置、光學裝置、處理器或其他IC邏輯結構。IC晶粒106中之一或多者可視情況包括光學裝置,諸如光電偵測器、雷射器、光源等。
每一晶粒106包括底部表面140及頂部表面142。晶粒106之底部表面140藉由焊料連接118或其他適合的電氣連接以耦接至內插件104之頂部表面138。晶粒106之頂部表面142面朝罩蓋102之底部表面144。熱界面材料(thermal interface material;TIM)114安置於晶粒106之頂部表面142與罩蓋102之底部表面144之間以增強其間的熱傳遞。在一個實例中,TIM 114可為熱凝膠或熱環氧樹脂,諸如封裝組件連接黏著劑,其可購自位於新澤西普林斯頓樞紐(Princeton Junction, New Jersey)的AI Technology, Inc.。
在一些實施方式中,罩蓋102由硬質材料製成。在其他實施方式中,尤其在需要利用罩蓋102以自IC晶粒106及柱110接收熱量之實施方式中,罩蓋102由諸如不鏽鋼、銅、鍍鎳銅或鋁之導熱材料以及其他適合的材料製成。未展示之散熱片可視情況安裝至罩蓋102之頂部表面146。
罩蓋102可在結構上耦接至封裝基板108以增加晶片封裝組件100之硬度。視情況,加強件120可用以在結構上將罩蓋102耦接至封裝基板108。當使用時,加強件120可由陶瓷、金屬或其他各種無機材料製成,諸如氧化鋁(Al
2O
3)、氮化鋁(AlN)、氮化矽(SiN)、矽(Si)、銅(Cu)、鋁(AL)及不鏽鋼以及其他材料。加強件120亦可由有機材料製成,諸如覆銅層合物。
如上文所論述,IC晶粒106藉由焊料連接118以連接至內插件104之電路。內插件104之電路類似地連接至封裝基板108之電路。在圖1中所描繪之實例中,內插件104之底部表面136藉由焊料連接118或其他適合連接以電氣方式且機械地耦接至封裝基板108之頂部表面134。
晶片封裝組件100可安裝至印刷電路板(printed circuit board;PCB)116以形成電子裝置150。以此方式,封裝基板108之電路經由焊球122或其他適合連接以耦接至封裝基板108之電路。在圖1中所描繪之實例中,封裝基板108之底部表面132藉由焊球122以電氣方式且機械地耦接至PCB之頂部表面130。
介電質填充物112安置在晶粒106之間的內插件104上。介電質填充物112向封裝組件100提供額外硬度,同時亦保護焊料連接118。介電質填充物112可為基於環氧樹脂之材料或其他適合的材料。介電質填充物112可另外包括填充物,例如無機填充物,諸如二氧化矽(SiO
2)。在一個實例中,介電質填充物112可具有在約20至約40 ppm/攝氏度之間的CTE、在約5至約20帕斯卡-秒之間的黏度,及在約6至約15帕斯卡(Pa)之間的楊氏模數。
在一個實例中,介電質填充物112在固化之前具有適合於流入並填充在晶粒106之底部表面140與內插件104之頂部表面138之間的圍繞焊料連接118之填隙空間的黏度。替代地,單獨的底填充材料可用於填充在晶粒106之底部表面140與內插件104之頂部表面138之間的圍繞焊料連接118之填隙空間,而介電質填充物112安置於底填充料上方並填充鄰近晶粒106之間的填隙空間。
附加晶粒熱傳遞柱110延伸通過介電質填充物112,並在內插件104之頂部表面138與罩蓋102之底部表面144之間提供穩健的傳導熱傳遞路徑。可在柱110與罩蓋102之間利用TIM以在柱110與罩蓋102之底部表面144之間提供穩健的熱傳遞界面。柱110通常由導熱材料形成,該導熱材料經選擇以在罩蓋102與內插件104之間提供良好的熱傳遞。柱110可具有任何合適的截面輪廓,且通常具有大約與晶粒106之高度相同的長度。在一個實例中,柱110之截面輪廓為圓形的。柱110之數量、大小、密度及位置可經選擇以在罩蓋102與內插件104之間提供所要的熱傳遞輪廓,例如用以對一個晶粒106比另一晶粒106產生更多熱量進行補償。
圖2為圖1之具有罩蓋102之晶片封裝組件100的示意性俯視圖,該罩蓋經移除以顯露安置於IC晶粒106周圍之附加晶粒熱傳遞柱110之例示性幾何配置。在圖2中所描繪之實例中,晶片封裝組件100經組態為高頻寬記憶體(high band-width memory;HBM)裝置,其中IC晶粒106
A經組態為場可程式化閘陣列(field programmable gate array;FPGA)且IC晶粒106
B經組態為HBM晶粒。預期包含晶片封裝組件100之IC晶粒可為相同或不同類型,其包括HBM及FPGA晶粒之外的類型。
在圖2中所描繪之實例中,附加晶粒熱傳遞柱110包括安置於鄰近晶粒106
A之間、安置於鄰近晶粒106
B之間及安置於鄰近晶粒106
A與106
B之間的柱202。另外,附加晶粒熱傳遞柱110包括安置於晶粒106
A、106
B與內插件104之邊緣208之間的柱204。換言之,柱204安置在晶粒106
A、106
B外部,且安置在加強件120之邊緣210內部。柱202、204之位置、大小及密度可經選擇以增強所要位置中之熱傳遞,並控制晶片封裝組件100之翹曲。下文進一步所描述之圖3至圖5中提供之例示用非限制性實例中所提供柱110之額外細節。
圖3為安置於內插件104之頂部表面138與罩蓋102之底部表面144之間的附加晶粒熱傳遞柱110之一個實例的示意性截面視圖。柱110安置於延伸通過介電質填充物112之孔302中。可在將柱110沈積在介電質填充物112中之前形成孔302。舉例而言,孔302可藉由蝕刻、雷射鑽孔、壓印、熱成形、機械鑽孔或其他適合方法來形成。可在柱110安置在內插件104上之後替代地形成孔302。舉例而言,介電質填充物112可圍繞先前形成的柱110來形成,諸如藉由在先前形成的柱110周圍模製填充物112或藉由其他適合技術。
在圖3中所描繪之具體實例中,柱110包括在內插件104與罩蓋102之間延伸的塊狀導體306。塊狀導體306可為填充或鍍覆在孔302內的金屬。在一個實例中,塊狀導體306為無電極鍍製銅或電鍍銅。塊狀導體306可形成在內插件104之頂部表面138的正上方。視情況,晶種層304可形成在內插件104之頂部表面138上,且塊狀導體306藉由鍍製以在晶種層304上形成。對於在孔302內之塊狀導體306的無電極鍍製不需要使用晶種層304。儘管未展示,但晶種層304可另外沿著孔302之側壁來形成。一旦塊狀導體306形成於孔302中,則TIM 114安置在塊狀導體306上以在柱110與罩蓋102之間提供良好的熱傳遞界面,以有利地改良晶片封裝組件100之熱傳遞效能。
圖4為安置於內插件104之頂部表面138與罩蓋102之底部表面144之間的附加晶粒熱傳遞柱400之另一實例的示意性截面視圖。附加晶粒柱400可用以替換用於晶片封裝組件100中之附加晶粒柱110中之任一個或全部。
類似於上文所描述的附加晶粒柱110,附加晶粒柱400安置於延伸通過介電質填充物112之孔302中。附加晶粒柱400可直接在內插件104之頂部表面138上安置於孔302中。視情況,TIM 114或其他導熱黏著劑或糊狀物可安置於柱400與內插件104之頂部表面138之間。
在圖4中所描繪之實例中,附加晶粒柱400呈經組態以在物件端部之間提供高熱傳遞速率的物件之形式。高熱傳遞速率的物件利用超導熱性質以在物件端部之間轉移熱量。高熱傳遞速率的物件可包括(1)振動並接觸物件內之顆粒以傳遞熱量,諸如工業金剛石,或(2)藉由提供兩個被動流動功能性(諸如熱管)來移動物件內之顆粒,或(3)藉由物件內之引入的流體循環而引起的強制流移動來移動顆粒,該引入的流體循環將自外部物件(即,封裝外部的泵)泵吸。在圖4中所描繪之實例中,高熱傳遞速率物件展示為熱管402。熱管402包括密封管404,其具有第一端部410及第二端部412。密封管404包括其中安置相變材料406的密封空腔408。在操作中,與導熱固體表面(亦即密封管404之第一端部410)接觸之液相的相變材料406藉由自內插件104吸收熱量而轉變成蒸汽。蒸汽接著在密封管404之密封空腔408內部之第一端部410與冷界面(亦即密封管404之第二端部412)之間行進,並且冷凝回液體—藉由TIM 114以將潛熱釋放至罩蓋102中。呈液體形式之相變材料406接著藉由毛細管作用及/或重力以返回至密封管404之第一端部410處之熱界面,且該循環重複進行。由於用於沸騰及冷凝之熱傳遞係數極高,因此附加晶粒柱400在內插件104之頂部表面138與罩蓋102之底部表面144之間有效且高效地傳導熱量,以有利地改良晶片封裝組件100之熱傳遞效能。
圖5為安置於內插件104之頂部表面138與罩蓋102之底部表面144之間的附加晶粒熱傳遞柱500之另一實例的示意性截面視圖。附加晶粒柱500可用以替換用於晶片封裝組件100中之附加晶粒柱110中之任一個或全部。
類似於上文所描述的附加晶粒柱110,附加晶粒柱500安置於延伸通過介電質填充物112之孔302中。附加晶粒柱500可直接在內插件104之頂部表面138上安置於孔302中。視情況,TIM或其他導熱黏著劑或糊狀物可安置於柱500與內插件104之頂部表面138之間。
在圖5中所描繪之實例中,附加晶粒柱500包括安置於孔302中之塊狀導體502。塊狀導體502包括導熱材料。導熱材料可為單一實心塊狀物,或包含多個元件,諸如粉末、金屬棉或離散形狀以及其他形式。導熱材料可為焊錫膏、金屬纖維、金屬粉末、金屬顆粒、金屬球、導熱黏著劑或其他適合的導熱材料。在一個實例中,塊狀導體502包含填充孔302之複數個銅球。在銅球(或填充孔302之其他傳導材料)之間的填隙空間可填充TIM或其他熱傳遞材料。
圖6為用於製造具有附加晶粒熱傳遞柱之晶片封裝組件(諸如上文參看圖1至圖5所描述的晶片封裝組件100等)之方法600的流程圖。圖7A至圖7J為晶片封裝組件在圖6之方法600的不同階段之示意性截面視圖。
方法600藉由將內插件104附接至載體700以在操作602處開始,如圖7A中所說明。僅在最初的製造操作期間利用載體700,並且因而,該載體以可移除方式被附接至內插件104之底部表面136。在一個實例中,使用可釋放壓敏黏著劑以將內插件104附接至載體700。
在操作604處,晶粒106附接至內插件104之頂部表面138,如圖7B中所說明。在晶粒附接操作期間,焊料連接118經回焊以將晶粒106之電路機械地並以電氣方式附接至內插件104之電路。
在操作606處,介電質填充物112安置於晶粒106及內插件104之頂部表面138上方,如圖7C中所說明。介電質填充物112可藉由另一合適方法進行旋塗、施配、包覆模製或沈積。在操作606處,介電質填充物112填充在鄰近晶粒106之間所限定的空間。介電質填充物112亦填充在安置於晶粒106與內插件104之間的焊料連接118之間所限定的填隙空間。介電質填充物112通常安置成大於晶粒106之頂部表面142的高度,使得晶粒106基本上完全嵌入填充物112內。
在操作608處,介電質填充物112經圖案化以創建穿過填充物112之孔302,該等孔暴露內插件104之頂部表面138之部分704,如圖7D中所說明。可藉由蝕刻介電質填充物112、壓印介電質填充物112、對介電質填充物112鑽孔或機械加工、對介電質填充物112雷射鑽孔或藉由使用另一合適技術來創建孔302。在圖7D中所描繪之實例中,使用雷射器以將孔302形成於晶粒106之間及形成於晶粒106與內插件104之邊緣208之間。
在操作610處,晶種層304沈積於內插件104之頂部表面138之藉由填充物112所暴露的部分704上,如圖7E中所說明。晶種層304可使用化學氣相沈積、物理氣相沈積、噴墨印刷或其他適合技術來沈積。晶種層304為隨後沈積在孔302中之金屬材料提供黏著層。晶種層304可視情況沈積於孔302之側壁上。在圖7E中所描繪之實例中,晶種層304由銅製成。
在操作612處,塊狀導體306沈積於晶種層304上,如圖7F中所說明。塊狀導體306可使用無電極鍍製、電鍍、化學氣相沈積、物理氣相沈積或其他適合技術以沈積於晶種層304上。塊狀導體306將孔302完全填充至介電質填充物112之頂部表面706。在圖7F中所描繪之實例中,塊狀導體306為直接鍍製在晶種層304上之銅。
在操作614處,移除塊狀導體306及介電質填充物112之一部分,如圖7G中所說明。塊狀導體306及介電質填充物112之經移除部分可藉由蝕刻、研磨、機械加工或其他適合技術來移除。在圖7G中所描繪之實例中,塊狀導體306及介電質填充物112經研磨使得介電質填充物112(及塊狀導體306)之頂部表面706與晶粒106之頂部表面142基本上共面,使得塊狀導體306及晶種層304形成傳導柱110。移除操作614可視情況移除晶粒106之頂部表面142之一部分以縮減晶粒106的高度。
替代地,可省去晶種層沈積的操作610,且諸如上文所描述的材料502之導熱材料可用以填充孔302並形成傳導柱500。在另一替代實例中,可省去操作610及612,且熱管402可安置於孔302中以形成傳導柱400。
繼續進行到操作616,載體700與內插件104分離,如圖7H中所說明。在操作618處,封裝基板108連接至內插件104之底部表面136,如圖7I中所說明。在封裝基板至內插件附接操作期間,焊料連接118經回焊以將封裝基板108之電路機械地並以電氣方式附接至內插件104之電路。
在操作620處,完成晶片封裝組件100之組裝,如圖7J中所說明。在操作620處完成晶片封裝組件100包括經由晶粒106以將罩蓋102附接至封裝基板108。操作620亦包括在附加晶粒柱110與罩蓋102之間安置TIM 114以確保在柱110與罩蓋102之間的穩健的熱界面,且因此確保在內插件104與罩蓋102之間的穩健的傳導熱傳遞路徑。TIM 114可另外沈積在罩蓋102與晶粒106之頂部表面142之間。
圖8為用於製造具有附加晶粒熱傳遞柱之晶片封裝組件(諸如上文參看圖1至圖5所描述的晶片封裝組件100等)之方法800的流程圖。圖7A至圖7J為晶片封裝組件在圖8之方法800的不同階段之示意性截面視圖。
方法800藉由將內插件104附接至載體700而在操作802處開始,如圖9A中所說明。僅在最初的製造操作期間利用載體700,並且因而,該載體以可移除方式附接至內插件104之底部表面136。在一個實例中,使用可釋放壓敏黏著劑以將內插件104附接至載體700。
在操作804處,晶種層304沈積於內插件104之頂部表面138上,如圖9B中所說明。晶種層304可使用化學氣相沈積、物理氣相沈積、噴墨印刷或其他適合的技術來沈積。晶種層304為隨後經沈積以形成附加晶粒柱110之金屬材料提供黏著層,如下文進一步描述。在圖9B中所描繪之實例中,晶種層304由銅製成。
在操作806處,遮罩材料900沈積於晶種層304上方,如圖9C中所說明。遮罩材料900可為光阻材料或適於晶種層304之圖案化及後續圖案化的其他材料。遮罩材料900可使用旋塗、可流動沈積、化學氣相沈積、噴墨印刷或其他適合技術來沈積。在圖9B中所描繪之實例中,遮罩材料900為聚合光阻材料。
在操作808處,遮罩材料900經圖案化並用於劃分並創建晶種層304之離散部分904,如圖9D中所說明。晶種層將為內插件晶圓上之覆蓋膜。光阻遮罩將經圖案化在此膜上,隨後為進行鍍製。904個突起部應與遮罩材料一樣較高,且區902經限定在遮罩突起部與非晶種層突起部之間。區902經限定在晶種層304之離散部分904之間,其中稍後附接晶粒106。遮罩材料900及晶種層304可使用合適微影及蝕刻技術來圖案化。替代地,可視情況省去操作806,且可剝蝕晶種層304以直接在內插件104之頂部表面138上形成離散部分904。在實例中,晶種層304之離散部分904可藉由雷射剝蝕來形成,以移除駐留在區902中之晶種層304的部分。
在操作810處,塊狀導體306沈積於晶種層304之離散部分904上,如圖9E中所說明。塊狀導體306可使用無電極鍍製、電鍍、化學氣相沈積、物理氣相沈積或其他適合的技術來沈積於晶種層304上。塊狀導體306形成為超過晶粒106之高度的高度,該等晶粒將稍後附接至區902中之內插件104。在圖9E中所描繪之實例中,塊狀導體306為銅且選擇性地直接鍍製在晶種層304上,使得基本上無銅膜沈積在區902中,且所形成的銅柱變為傳導柱110之主要部分。
在操作812處,晶粒106附接至在塊狀導體306之間所限定的在區902中之內插件104的頂部表面138,如圖9F中所說明。在晶粒附接操作期間,焊料連接118經回焊以將晶粒106之電路機械地並以電氣方式附接至內插件104之電路。
在操作814處,介電質填充物112安置於晶粒106及內插件104之頂部表面138上方,如圖9G中所說明。介電質填充物112圍繞塊狀導體306及晶種層304來形成,從而在介電質填充物112中形成其中駐留有塊狀導體306的孔302。介電質填充物112可藉由另一合適的方法旋塗、施配、包覆模製或沈積。在操作814處,介電質填充物112填充在鄰近晶粒106之間所限定的空間。介電質填充物112亦填充在安置於晶粒106與內插件104之間的焊料連接118之間所限定的填隙空間。介電質填充物112通常安置成大於晶粒106之頂部表面142的高度,使得晶粒106基本上完全嵌入填充物112內。
在操作816處,移除塊狀導體306及介電質填充物112之一部分,如圖9H中所說明。塊狀導體306及介電質填充物112之經移除部分可藉由蝕刻、研磨、機械加工或其他適合的技術來移除。在圖9H中所描繪之實例中,塊狀導體306及介電質填充物112經研磨使得介電質填充物112(及塊狀導體306)之頂部表面706與晶粒106之頂部表面142基本上共面,使得塊狀導體306及晶種層304形成傳導柱110。如上文所論述,移除的操作816可視情況移除晶粒106之頂部表面142的一部分以縮減晶粒106之高度。
在操作818處,載體700與內插件104分離,如圖9I中所說明。在操作820處,封裝基板108連接至內插件104之底部表面136,如圖9J中所說明。在封裝基板至內插件附接操作期間,焊料連接118經回焊以將封裝基板108之電路機械地並以電氣方式附接至內插件104之電路。
在操作822處,完成晶片封裝組件100之組裝,如圖9K中所說明。操作822類似於上文所描述的操作620。在操作822處完成晶片封裝組件100包括經由晶粒106以將罩蓋102附接至封裝基板108。操作822亦包括在附加晶粒柱110與罩蓋102之間安置TIM 114,以確保在柱110與罩蓋102之間的穩健的熱界面,且因此確保在內插件104與罩蓋102之間的穩健的熱傳遞路徑。TIM 114可另外沈積在罩蓋102與晶粒106之頂部表面142之間。
因此,已經提供晶片封裝組件及其製造方法,其利用安置於積體電路(IC)晶粒周圍之複數個附加晶粒熱傳遞柱以改良晶片封裝組件內之豎直熱傳遞。附加晶粒熱傳遞柱在罩蓋與基板(諸如內插件或封裝基板)之間有利地提供穩健的傳導熱傳遞路徑。附加晶粒熱傳遞柱亦可選擇性地定位以改良橫越封裝組件之熱傳遞輪廓。至晶片封裝組件之罩蓋的增強的熱傳遞顯著地改良可靠性及效能,同時亦縮減可能誘發翹曲或提供IC晶粒之不充分溫度控制的熱點。另外,附加晶粒熱傳遞柱自內插件移除熱量之能力顯著地縮減在晶片封裝組件內之熱耦合及溫度上升,從而有利地提高電遷移(EM)壽命。
雖然前述內容係針對本新型的具體實例,但在不脫離本新型的基本範疇之情況下,可設計出本新型之其他及另外具體實例,且由以下申請專利範圍判定本新型之範圍。
100:晶片封裝組件
102:罩蓋
104:內插件
106、106A、106B:積體電路(IC)晶粒
108:封裝基板
110:附加晶粒熱傳遞柱/附加晶粒柱/傳導柱/柱
112:介電質填充物
114:熱界面材料(TIM)
116:印刷電路板(PCB)
118:焊料連接
120:加強件
122:焊球
130、134、138、142、146:頂部表面
132、136、140、144:底部表面
150:電子裝置
202、204:柱
208、210:邊緣
302:孔
304:晶種層
306:塊狀導體
400:附加晶粒柱/附加晶粒熱傳遞柱/柱
402:熱管
404:密封管
406:相變材料
408:密封空腔
410:第一端部
412:第二端部
500:附加晶粒熱傳遞柱/附加晶粒柱/柱
502:塊狀導體/材料
600:方法
602、604、606、608、610、614、616、618、620:操作
700:載體
704:部分
706:頂部表面
800:方法
802、804、806、808、810、812、814、816、818、820、822:操作
900:遮罩材料
902:區
904:離散部分
因此,可參考具體實例獲得可詳細地理解本新型之以上列舉特徵之方式、上文簡要概述之本新型之更特定描述,其中一些說明於隨附圖式中。然而,應注意到,隨附圖式僅說明本新型之典型具體實例且因此不應將其視為限制本新型之範圍,因為本新型可准許其他同等有效之具體實例。
圖1為具有安置於積體電路(IC)晶粒周圍之複數個附加晶粒熱傳遞柱之晶片封裝組件的示意性截面視圖。
圖2為圖1之具有罩蓋之晶片封裝組件的示意性俯視圖,該罩蓋經移除以顯露安置於IC晶粒周圍之附加晶粒熱傳遞柱之例示性幾何配置。
圖3為圖2之附加晶粒熱傳遞柱中之一個例示性附加晶粒熱傳遞柱的示意性截面視圖。
圖4至圖5為附加晶粒熱傳遞柱之各種替代性具體實例的示意性截面視圖。
圖6為用於製造具有附加晶粒熱傳遞柱之晶片封裝組件之方法的流程圖。
圖7A至圖7J為晶片封裝組件在圖6之方法的不同階段之示意性截面視圖。
圖8為用於製造具有附加晶粒熱傳遞柱之晶片封裝組件之方法的流程圖。
圖9A至圖9K為晶片封裝組件在圖8之方法的不同階段之示意性截面視圖。
為了促進理解,已使用相同元件符號在可能的情況下表示圖式中共有的相同元件。預期一個具體實例之元件可有益地併入於其他具體實例中。
100:晶片封裝組件
102:罩蓋
104:內插件
106:積體電路(IC)晶粒
108:封裝基板
110:附加晶粒熱傳遞柱/附加晶粒柱/傳導柱/柱
112:介電質填充物
114:熱界面材料(TIM)
116:印刷電路板(PCB)
118:焊料連接
120:加強件
122:焊球
130、134、138、142、146:頂部表面
132、136、140、144:底部表面
150:電子裝置
Claims (12)
- 一種晶片封裝組件,其包含: 基板; 第一積體電路(IC)晶粒,其安裝至該基板; 罩蓋,其安置於該第一IC晶粒上方;及 複數個附加晶粒傳導柱,其安置於該罩蓋與基板之間,該複數個附加晶粒傳導柱在該罩蓋與該基板之間提供在該第一IC晶粒外部橫向延伸之熱傳遞路徑。
- 如請求項1所述之晶片封裝組件,其進一步包含: 介電質填充物,其安置於該基板與安置於該晶粒上方之該罩蓋之間,該介電質填充物具有其中安置有該複數個附加晶粒傳導柱之複數個孔。
- 如請求項2所述之晶片封裝組件,其中該複數個附加晶粒傳導柱中之第一傳導柱進一步包含: 熱管,其具有藉由該複數個孔中之第一孔暴露且與該罩蓋進行導熱接觸之第一端部,該熱管具有藉由該第一孔暴露且與該基板進行導熱接觸之第二端部。
- 如請求項1所述之晶片封裝組件,其中該複數個附加晶粒傳導柱各自進一步包含: 晶種層,其安置在該基板上;及 塊狀導熱層,其安置在該晶種層上。
- 如請求項1所述之晶片封裝組件,其進一步包含: 第二IC晶粒,其安裝至該基板,該第二IC晶粒經組態為記憶體晶粒,且該第一IC晶粒經組態為邏輯晶粒。
- 如請求項5所述之晶片封裝組件,其進一步包含: 加強件,其結合至該基板並且包圍該第一IC晶粒及該第二IC晶粒。
- 如請求項6所述之晶片封裝組件,其中該複數個附加晶粒傳導柱中之至少一第一傳導柱安置於該第一IC晶粒及該第二IC晶粒中之一者與該加強件之間。
- 如請求項7所述之晶片封裝組件,其中該複數個附加晶粒傳導柱中之至少一第二傳導柱安置於該第一IC晶粒與該第二IC晶粒之間。
- 如請求項1所述之晶片封裝組件,其中該複數個附加晶粒傳導柱中之第一傳導柱包含選自由以下組成之群組之導熱材料:粉末、金屬棉、離散形狀、焊錫膏、金屬纖維、金屬粉末、金屬顆粒、金屬球,及導熱黏著劑。
- 一種高頻寬記憶體晶片封裝組件,其包含: 基板; 至少一第一記憶體晶粒,其安裝至該基板; 至少一第一邏輯晶粒,其安裝至並且通信耦接至該基板; 罩蓋,其安置於該第一記憶體晶粒及該第一邏輯晶粒上方; 介電質填充物,其安置於該第一記憶體晶粒及該第一邏輯晶粒周圍,該介電質填充物安置於該基板與該罩蓋之間,該介電質填充物具有至少一個孔;及 第一傳導柱,其安置於該介電質填充物中之該孔中,並且在該罩蓋與該基板之間提供熱傳遞路徑。
- 如請求項10所述之高頻寬記憶體晶片封裝組件,其中該第一傳導柱進一步包含: 晶種層,其安置在該基板上;及 塊狀導熱層,其安置在該晶種層上。
- 如請求項10所述之高頻寬記憶體晶片封裝組件,其進一步包含: 加強件,其結合至該基板並且包圍該第一記憶體晶粒及該第一邏輯晶粒。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/147,286 | 2018-09-28 | ||
US16/147,286 US11355412B2 (en) | 2018-09-28 | 2018-09-28 | Stacked silicon package assembly having thermal management |
Publications (1)
Publication Number | Publication Date |
---|---|
TWM593647U true TWM593647U (zh) | 2020-04-11 |
Family
ID=69946107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108211759U TWM593647U (zh) | 2018-09-28 | 2019-09-04 | 具有熱管理之堆疊矽封裝組件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11355412B2 (zh) |
CN (1) | CN212342623U (zh) |
TW (1) | TWM593647U (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI764779B (zh) * | 2015-04-14 | 2022-05-11 | 美商安芬諾股份有限公司 | 電連接器 |
EP3547360A1 (de) * | 2018-03-29 | 2019-10-02 | Siemens Aktiengesellschaft | Halbleiterbaugruppe und verfahren zur herstellung der halbleiterbaugruppe |
US11355412B2 (en) * | 2018-09-28 | 2022-06-07 | Xilinx, Inc. | Stacked silicon package assembly having thermal management |
KR102677834B1 (ko) * | 2019-03-26 | 2024-06-21 | 삼성전자주식회사 | 반도체 패키지 |
US11488887B1 (en) | 2020-03-05 | 2022-11-01 | Xilinx, Inc. | Thermal enablement of dies with impurity gettering |
US11282775B1 (en) | 2020-07-30 | 2022-03-22 | Xilinx, Inc. | Chip package assembly with stress decoupled interconnect layer |
US11246211B1 (en) | 2021-03-01 | 2022-02-08 | Xilinx, Inc. | Micro device with through PCB cooling |
US11817436B2 (en) * | 2021-06-28 | 2023-11-14 | Advanced Micro Devices, Inc. | Common cooling solution for multiple packages |
US11830785B2 (en) * | 2021-10-06 | 2023-11-28 | STATS ChipPAC Pte. Ltd. | Package with windowed heat spreader |
CN116504646B (zh) * | 2023-06-21 | 2023-12-15 | 青岛泰睿思微电子有限公司 | 多芯片排列封装结构及方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5886408A (en) * | 1994-09-08 | 1999-03-23 | Fujitsu Limited | Multi-chip semiconductor device |
US5777847A (en) * | 1995-09-27 | 1998-07-07 | Nec Corporation | Multichip module having a cover wtih support pillar |
US5990418A (en) * | 1997-07-29 | 1999-11-23 | International Business Machines Corporation | Hermetic CBGA/CCGA structure with thermal paste cooling |
US6703560B2 (en) * | 1998-09-15 | 2004-03-09 | International Business Machines Corporation | Stress resistant land grid array (LGA) module and method of forming the same |
US7061103B2 (en) * | 2003-04-22 | 2006-06-13 | Industrial Technology Research Institute | Chip package structure |
US7038316B2 (en) * | 2004-03-25 | 2006-05-02 | Intel Corporation | Bumpless die and heat spreader lid module bonded to bumped die carrier |
US7126217B2 (en) * | 2004-08-07 | 2006-10-24 | Texas Instruments Incorporated | Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression support |
JP2013115083A (ja) * | 2011-11-25 | 2013-06-10 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
US9252054B2 (en) * | 2013-09-13 | 2016-02-02 | Industrial Technology Research Institute | Thinned integrated circuit device and manufacturing process for the same |
US9653443B2 (en) * | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US10177130B2 (en) * | 2015-04-01 | 2019-01-08 | Bridge Semiconductor Corporation | Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener |
US9478504B1 (en) * | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
KR102037763B1 (ko) * | 2015-08-17 | 2019-10-30 | 한국전자통신연구원 | 송수신 패키지 |
US10236229B2 (en) * | 2016-06-24 | 2019-03-19 | Xilinx, Inc. | Stacked silicon package assembly having conformal lid |
US11398414B2 (en) * | 2018-09-26 | 2022-07-26 | Intel Corporation | Sloped metal features for cooling hotspots in stacked-die packages |
US11355412B2 (en) * | 2018-09-28 | 2022-06-07 | Xilinx, Inc. | Stacked silicon package assembly having thermal management |
-
2018
- 2018-09-28 US US16/147,286 patent/US11355412B2/en active Active
-
2019
- 2019-09-04 TW TW108211759U patent/TWM593647U/zh unknown
- 2019-09-27 CN CN201921625811.5U patent/CN212342623U/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20200105642A1 (en) | 2020-04-02 |
US11355412B2 (en) | 2022-06-07 |
CN212342623U (zh) | 2021-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11355412B2 (en) | Stacked silicon package assembly having thermal management | |
US11133237B2 (en) | Package with embedded heat dissipation features | |
CN104600064B (zh) | 封装件上芯片结构和方法 | |
US7671466B2 (en) | Semiconductor package having heat dissipating device with cooling fluid | |
US9922902B2 (en) | Semiconductor device and semiconductor package | |
TWI749212B (zh) | 半導體元件封裝及半導體裝置 | |
US20170345708A1 (en) | Semiconductor Packaging Structure and Process | |
US11488936B2 (en) | Stacked silicon package assembly having vertical thermal management | |
US20070290310A1 (en) | Semiconductor Device and Method for Manufacturing the Same | |
US9240394B1 (en) | Stacked chips attached to heat sink having bonding pads | |
US20060043576A1 (en) | Structures and methods for heat dissipation of semiconductor integrated circuits | |
CN104716109A (zh) | 具有降低热串扰的热管理部件的封装件及其形成方法 | |
CN215299234U (zh) | 芯片封装组件 | |
JP2016063178A (ja) | 半導体装置及びその製造方法 | |
TWI655714B (zh) | 封裝基板、封裝半導體裝置與其之封裝方法 | |
US11640930B2 (en) | Semiconductor package having liquid-cooling lid | |
US11450597B2 (en) | Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same | |
TWI721898B (zh) | 半導體封裝結構 | |
JP2008243966A (ja) | 電子部品が実装されたプリント基板及びその製造方法 | |
CN220324452U (zh) | 一种半导体封装装置 |