JP2012504903A5 - - Google Patents

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Publication number
JP2012504903A5
JP2012504903A5 JP2011530058A JP2011530058A JP2012504903A5 JP 2012504903 A5 JP2012504903 A5 JP 2012504903A5 JP 2011530058 A JP2011530058 A JP 2011530058A JP 2011530058 A JP2011530058 A JP 2011530058A JP 2012504903 A5 JP2012504903 A5 JP 2012504903A5
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JP
Japan
Prior art keywords
snr
steps
bit interleaver
bit
determining
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JP2011530058A
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Japanese (ja)
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JP2012504903A (ja
JP5584219B2 (ja
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Priority claimed from PCT/US2009/005437 external-priority patent/WO2010039257A1/en
Publication of JP2012504903A publication Critical patent/JP2012504903A/ja
Publication of JP2012504903A5 publication Critical patent/JP2012504903A5/ja
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Publication of JP5584219B2 publication Critical patent/JP5584219B2/ja
Expired - Fee Related legal-status Critical Current
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JP2011530058A 2008-10-03 2009-10-02 2元消失サロゲート・チャネルを用いたawgnチャネル条件下でビット・インタリーバをldpc符号および変調に適合させる方法および装置 Expired - Fee Related JP5584219B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10251708P 2008-10-03 2008-10-03
US61/102,517 2008-10-03
US19688908P 2008-10-21 2008-10-21
US61/196,889 2008-10-21
PCT/US2009/005437 WO2010039257A1 (en) 2008-10-03 2009-10-02 Method and apparatus for adapting a bit interleaver to ldpc codes and modulations under awgn channel conditions using binary erasure surrogate channels

Publications (3)

Publication Number Publication Date
JP2012504903A JP2012504903A (ja) 2012-02-23
JP2012504903A5 true JP2012504903A5 (enExample) 2013-12-12
JP5584219B2 JP5584219B2 (ja) 2014-09-03

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JP2011530058A Expired - Fee Related JP5584219B2 (ja) 2008-10-03 2009-10-02 2元消失サロゲート・チャネルを用いたawgnチャネル条件下でビット・インタリーバをldpc符号および変調に適合させる方法および装置

Country Status (7)

Country Link
US (1) US8677219B2 (enExample)
EP (1) EP2329602B1 (enExample)
JP (1) JP5584219B2 (enExample)
KR (1) KR101630442B1 (enExample)
CN (1) CN102292917B (enExample)
BR (1) BRPI0919542A2 (enExample)
WO (1) WO2010039257A1 (enExample)

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