WO2010039257A1 - Method and apparatus for adapting a bit interleaver to ldpc codes and modulations under awgn channel conditions using binary erasure surrogate channels - Google Patents
Method and apparatus for adapting a bit interleaver to ldpc codes and modulations under awgn channel conditions using binary erasure surrogate channels Download PDFInfo
- Publication number
- WO2010039257A1 WO2010039257A1 PCT/US2009/005437 US2009005437W WO2010039257A1 WO 2010039257 A1 WO2010039257 A1 WO 2010039257A1 US 2009005437 W US2009005437 W US 2009005437W WO 2010039257 A1 WO2010039257 A1 WO 2010039257A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bit interleaver
- snr
- erasure
- decoding threshold
- determining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2757—Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
Definitions
- processor or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (“DSP”) hardware, read-only memory (“ROM”) for storing software, random access memory (“RAM”), and non-volatile storage.
- DSP digital signal processor
- ROM read-only memory
- RAM random access memory
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP09741488.2A EP2329602B1 (en) | 2008-10-03 | 2009-10-02 | Method and apparatus for adapting a bit interleaver to ldpc codes and modulations under awgn channel conditions using binary erasure surrogate channels |
| US12/998,270 US8677219B2 (en) | 2008-10-03 | 2009-10-02 | Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels |
| CN200980139687.4A CN102292917B (zh) | 2008-10-03 | 2009-10-02 | 利用二元删除替代信道在awgn信道条件下将比特交织器适配于ldpc码和调制的方法和装置 |
| JP2011530058A JP5584219B2 (ja) | 2008-10-03 | 2009-10-02 | 2元消失サロゲート・チャネルを用いたawgnチャネル条件下でビット・インタリーバをldpc符号および変調に適合させる方法および装置 |
| BRPI0919542A BRPI0919542A2 (pt) | 2008-10-03 | 2009-10-02 | método e aparelho para adaptação de um intercalador de bits em códigos ldpc e modulações sob condições de canal awgn usando canais substitutos de emenda binária |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10251708P | 2008-10-03 | 2008-10-03 | |
| US61/102,517 | 2008-10-03 | ||
| US19688908P | 2008-10-21 | 2008-10-21 | |
| US61/196,889 | 2008-10-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2010039257A1 true WO2010039257A1 (en) | 2010-04-08 |
Family
ID=41354107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2009/005437 Ceased WO2010039257A1 (en) | 2008-10-03 | 2009-10-02 | Method and apparatus for adapting a bit interleaver to ldpc codes and modulations under awgn channel conditions using binary erasure surrogate channels |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8677219B2 (enExample) |
| EP (1) | EP2329602B1 (enExample) |
| JP (1) | JP5584219B2 (enExample) |
| KR (1) | KR101630442B1 (enExample) |
| CN (1) | CN102292917B (enExample) |
| BR (1) | BRPI0919542A2 (enExample) |
| WO (1) | WO2010039257A1 (enExample) |
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| CN103023618A (zh) * | 2013-01-11 | 2013-04-03 | 北京邮电大学 | 一种任意码长的极化编码方法 |
| EP2690790A1 (en) * | 2012-07-27 | 2014-01-29 | Panasonic Corporation | Bit interleaving for rotated constellations with quasi-cyclic LDPC codes |
| EP2879295A4 (en) * | 2012-07-27 | 2015-07-08 | Panasonic Corp | TRANSMISSION PROCEDURES, RECEIVING METHODS, TRANSMITTERS AND RECEIVERS |
| JP2016123106A (ja) * | 2011-05-18 | 2016-07-07 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP2016136753A (ja) * | 2011-05-18 | 2016-07-28 | パナソニック株式会社 | 並列ビットインターリーバ |
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| US12289192B2 (en) | 2008-12-30 | 2025-04-29 | Constellation Designs, LLC | Systems and methods for receiving data transmitted using non-uniform QAM 256 constellations |
| US12425885B2 (en) | 2010-07-08 | 2025-09-23 | Constellation Designs, LLC | Systems and methods for receiving data transmitted using non-uniform QAM 256 constellations via fading channels |
| EP2525495A1 (en) | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
| US9654316B2 (en) * | 2012-07-27 | 2017-05-16 | Sun Patent Trust | Transmission method, transmitter, reception method, and receiver |
| KR102002559B1 (ko) | 2013-07-05 | 2019-07-22 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| US9735809B2 (en) | 2013-09-26 | 2017-08-15 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
| KR102264848B1 (ko) * | 2013-09-26 | 2021-06-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| US10135460B2 (en) * | 2013-10-01 | 2018-11-20 | Texas Instruments Incorporated | Apparatus and method for multilevel coding (MLC) with binary alphabet polar codes |
| WO2015076629A1 (en) * | 2013-11-25 | 2015-05-28 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
| US9859925B2 (en) * | 2013-12-13 | 2018-01-02 | Empire Technology Development Llc | Low-complexity flash memory data-encoding techniques using simplified belief propagation |
| KR101776275B1 (ko) * | 2014-02-19 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
| US9602137B2 (en) * | 2014-02-19 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US10425110B2 (en) * | 2014-02-19 | 2019-09-24 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| EP3985879A1 (en) * | 2014-02-20 | 2022-04-20 | Shanghai National Engineering Research Center of Digital Television Co., Ltd. | Multi-stage interleaving for ldpc codes |
| BR112016021595B1 (pt) * | 2014-03-19 | 2022-09-20 | Samsung Electronics Co., Ltd | Aparelho transmissor, e método de intercalação de um aparelho transmissor |
| KR101776272B1 (ko) | 2014-03-19 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
| KR101775704B1 (ko) | 2014-05-21 | 2017-09-19 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
| KR101775703B1 (ko) | 2014-05-21 | 2017-09-06 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
| US9800269B2 (en) | 2014-05-21 | 2017-10-24 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9602245B2 (en) * | 2014-05-21 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US10361720B2 (en) * | 2014-05-22 | 2019-07-23 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same |
| US9923970B2 (en) | 2014-08-22 | 2018-03-20 | Nexenta Systems, Inc. | Multicast collaborative erasure encoding and distributed parity protection |
| US10110676B2 (en) | 2014-08-22 | 2018-10-23 | Nexenta Systems, Inc. | Parallel transparent restructuring of immutable content in a distributed object storage system |
| US10447428B2 (en) | 2015-05-19 | 2019-10-15 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9634692B2 (en) | 2015-05-19 | 2017-04-25 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9729174B2 (en) | 2015-05-19 | 2017-08-08 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9692453B2 (en) | 2015-05-19 | 2017-06-27 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US10340954B2 (en) | 2015-05-19 | 2019-07-02 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9595978B2 (en) | 2015-05-19 | 2017-03-14 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9680505B2 (en) * | 2015-05-19 | 2017-06-13 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
| US9916878B2 (en) * | 2016-03-15 | 2018-03-13 | Maxlinear, Inc. | Methods and systems for parallel column twist interleaving |
| US11475310B1 (en) * | 2016-11-29 | 2022-10-18 | Perceive Corporation | Training network to minimize worst-case error |
| US10291318B2 (en) * | 2017-04-27 | 2019-05-14 | Nec Corporation | Physical layer security in optical communications using Bessel modes |
| KR102186741B1 (ko) * | 2020-04-01 | 2020-12-04 | 한국과학기술원 | 정규 저밀도 패리티 검사부호의 비트 반전 복호 알고리즘의 밀도 진화 방법 및 그 장치 |
| CN115133936A (zh) * | 2021-03-27 | 2022-09-30 | 华为技术有限公司 | 编码方法、译码方法以及通信装置 |
| CN114142872B (zh) * | 2021-12-06 | 2023-03-10 | 上海垣信卫星科技有限公司 | Ldpc解码装置及其方法,低轨道卫星接收设备 |
| KR20230126777A (ko) * | 2022-02-23 | 2023-08-31 | 삼성디스플레이 주식회사 | 디코더 및 그것을 포함하는 데이터 처리 장치 |
| US12387092B1 (en) | 2022-07-11 | 2025-08-12 | Amazon Technologies, Inc. | Neural network loss function that incorporates incorrect category probabilities |
| US12289163B2 (en) * | 2022-12-27 | 2025-04-29 | Qualcomm Incorporated | Low density parity check graph adaptation |
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| CN1294706C (zh) * | 2003-11-07 | 2007-01-10 | 中国人民解放军理工大学通信工程学院 | 对于具有输出外信息的编码调制系统的迭代解调解码方法及装置 |
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2009
- 2009-10-02 US US12/998,270 patent/US8677219B2/en not_active Expired - Fee Related
- 2009-10-02 BR BRPI0919542A patent/BRPI0919542A2/pt not_active IP Right Cessation
- 2009-10-02 KR KR1020117010084A patent/KR101630442B1/ko not_active Expired - Fee Related
- 2009-10-02 EP EP09741488.2A patent/EP2329602B1/en not_active Not-in-force
- 2009-10-02 WO PCT/US2009/005437 patent/WO2010039257A1/en not_active Ceased
- 2009-10-02 JP JP2011530058A patent/JP5584219B2/ja not_active Expired - Fee Related
- 2009-10-02 CN CN200980139687.4A patent/CN102292917B/zh not_active Expired - Fee Related
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| FRANK KIENLE ET AL: "Macro interleaver design for bit interleaved coded modulation with low-density parity-check codes", PROC., IEEE VEHICULAR TECHNOLOGY CONFERENCE, VTC SPRING 2008, 11 May 2008 (2008-05-11), pages 763 - 766, XP031255631, ISBN: 978-1-4244-1644-8 * |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016123106A (ja) * | 2011-05-18 | 2016-07-07 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP2016136753A (ja) * | 2011-05-18 | 2016-07-28 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP2017085629A (ja) * | 2011-05-18 | 2017-05-18 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP2017085626A (ja) * | 2011-05-18 | 2017-05-18 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP2021048602A (ja) * | 2011-05-18 | 2021-03-25 | パナソニック株式会社 | 並列ビットインターリーバ |
| JP6999010B2 (ja) | 2011-05-18 | 2022-01-18 | パナソニック株式会社 | 並列ビットインターリーバ |
| EP2690790A1 (en) * | 2012-07-27 | 2014-01-29 | Panasonic Corporation | Bit interleaving for rotated constellations with quasi-cyclic LDPC codes |
| EP2879295A4 (en) * | 2012-07-27 | 2015-07-08 | Panasonic Corp | TRANSMISSION PROCEDURES, RECEIVING METHODS, TRANSMITTERS AND RECEIVERS |
| CN103023618A (zh) * | 2013-01-11 | 2013-04-03 | 北京邮电大学 | 一种任意码长的极化编码方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101630442B1 (ko) | 2016-06-24 |
| EP2329602B1 (en) | 2015-03-11 |
| CN102292917A (zh) | 2011-12-21 |
| US8677219B2 (en) | 2014-03-18 |
| JP2012504903A (ja) | 2012-02-23 |
| EP2329602A1 (en) | 2011-06-08 |
| KR20110082032A (ko) | 2011-07-15 |
| US20110182345A1 (en) | 2011-07-28 |
| BRPI0919542A2 (pt) | 2015-12-08 |
| CN102292917B (zh) | 2015-08-26 |
| JP5584219B2 (ja) | 2014-09-03 |
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