JP2012504344A - 削設構造の垂直側壁に金属をパターニングする方法、当該方法を用いた埋め込みmimキャパシタを形成する方法、及び当該方法により製造された埋め込みメモリデバイス - Google Patents
削設構造の垂直側壁に金属をパターニングする方法、当該方法を用いた埋め込みmimキャパシタを形成する方法、及び当該方法により製造された埋め込みメモリデバイス Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 77
- 239000002184 metal Substances 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 238000000059 patterning Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 62
- 239000011521 glass Substances 0.000 claims abstract description 56
- 238000005520 cutting process Methods 0.000 claims abstract description 43
- 239000000126 substance Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000002679 ablation Methods 0.000 claims abstract description 3
- 230000006870 function Effects 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- -1 polymethylsiloxane Polymers 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 86
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/012—Form of non-self-supporting electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【選択図】図1
Description
Claims (20)
- 第1導電層と
前記第1導電層上に設けられる第1絶縁層と、
前記第1絶縁層中に設けられ、前記第1導電層まで延びる削設構造と、
前記第1導電層と隣接して電気的に接続された第2導電層、前記第2導電層の内側に設けられた第2絶縁層、及び前記第2絶縁層の内側に設けられた第3導電層を有し、前記削設構造に設けられるMIMキャパシタと
を備え、
前記第1導電層は、前記削設構造の床として機能し、
前記削設構造は、前記床から離れる方向に延びる側壁をさらに含み、
前記第2導電層は、前記床及び前記側壁の第1部分を覆い、
前記第2絶縁層は、前記第2導電層及び前記側壁の第2部分を覆う埋め込みメモリデバイス。 - 前記第1導電層は、銅線である請求項1に記載の埋め込みメモリデバイス。
- 前記第3導電層は、銅プラグである請求項2に記載の埋め込みメモリデバイス。
- 前記第2絶縁層は、共形誘電体膜である請求項3に記載の埋め込みメモリデバイス。
- 前記共形誘電体膜は、高誘電率材料を含む請求項4に記載の埋め込みメモリデバイス。
- 削設構造の垂直側壁に金属をパターニングする方法であって、
前記金属の一部分が、前記削設構造内においてスピンオングラス材料の上方で露出するように、前記スピンオングラス材料を前記削設構造内に配置する段階と、
第1のウェット化学エッチングを使用して前記金属の前記一部分をエッチングし、前記垂直側壁から取り除く段階と、
第2のウェット化学エッチングを使用してエッチングすることにより、前記削設構造から前記スピンオングラス材料を取り除く段階と
を備える方法。 - 前記スピンオングラス材料を前記削設構造内に配置する段階は、
前記削設構造を前記スピンオングラス材料で満たす段階と、前記金属の前記一部分が露出するように、前記スピンオングラス材料の一部分を取り除く段階と
を有する請求項6に記載の方法。 - 前記スピンオングラス材料は、ポリメチルシロキサン膜を含む請求項7に記載の方法。
- 前記スピンオングラス材料の一部分を取り除く段階は、プラズマエッチングを使用して、前記スピンオングラス材料の前記一部分を取り除く段階を含む請求項7に記載の方法。
- 前記第1のウェット化学エッチングは、酸性ベースの水溶性化学作用を含む請求項6に記載の方法。
- 前記第2のウェット化学エッチングは、アルカリ性の水溶性化学作用を含む請求項10に記載の方法。
- 前記スピンオングラス材料を前記削設構造内に配置する段階は、スピンコーティング技術を使用して前記スピンオングラス材料を堆積する段階を有する請求項6に記載の方法。
- 埋め込みMIMキャパシタを形成する方法であって、
金属線がビアの底部に露出するように、誘電体材料中に前記ビアを形成する工程と、
前記ビアに、前記埋め込みMIMキャパシタの下部電極として機能する共形金属膜を堆積する工程と、
前記ビアをスピンオングラス材料で満たす工程と、
前記スピンオングラス材料の第1部分を取り除いて、前記ビア内に残存する前記スピンオングラス材料の第2部分の上方に、前記共形金属膜の一部分を前記ビア内で露出させる工程と、
第1のウェット化学エッチングを使用して、前記共形金属膜の前記一部分をエッチングして取り除く工程と、
第2のウェット化学エッチングを使用してエッチングすることにより、前記スピンオングラス材料の前記第2部分を前記ビアから取り除く工程と、
前記ビアに、前記埋め込みMIMキャパシタの絶縁層として機能する共形誘電体層を堆積する工程と、
前記ビアを、前記埋め込みMIMキャパシタの上部電極として機能する金属プラグで埋める工程と
を備える方法。 - 前記金属線は、銅を含む請求項13に記載の方法。
- 前記金属プラグは、銅を含む請求項14に記載の方法。
- 前記ビアを前記金属プラグで埋める工程は、電気めっき技術を使用して、前記銅を堆積させることを含む請求項15に記載の方法。
- 前記共形誘電体層は、高誘電率材料を含む請求項15に記載の方法。
- 前記第1のウェット化学エッチングは、酸性ベースの水溶性化学作用を含む請求項13に記載の方法。
- 前記第2のウェット化学エッチングは、アルカリ性の水溶性化学作用を含む請求項18に記載の方法。
- 前記ビアを前記スピンオングラス材料で満たす工程は、スピンコーティング技術を使用して前記スピンオングラス材料を堆積することを含む請求項13に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/286,338 | 2008-09-30 | ||
US12/286,338 US7927959B2 (en) | 2008-09-30 | 2008-09-30 | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby |
PCT/US2009/058540 WO2010039629A2 (en) | 2008-09-30 | 2009-09-28 | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded mim capacitor using same, and embedded memory device produced thereby |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012504344A true JP2012504344A (ja) | 2012-02-16 |
JP5358848B2 JP5358848B2 (ja) | 2013-12-04 |
Family
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JP2011529301A Expired - Fee Related JP5358848B2 (ja) | 2008-09-30 | 2009-09-28 | 削設構造の側壁に金属をパターニングする方法、及びメモリデバイスの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7927959B2 (ja) |
EP (1) | EP2329524A4 (ja) |
JP (1) | JP5358848B2 (ja) |
KR (1) | KR101345926B1 (ja) |
CN (1) | CN102165580A (ja) |
WO (1) | WO2010039629A2 (ja) |
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JP4823954B2 (ja) * | 2007-03-30 | 2011-11-24 | 本田技研工業株式会社 | 自動二輪車用可動ステップ |
US7927959B2 (en) | 2008-09-30 | 2011-04-19 | Intel Corporation | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby |
US8441097B2 (en) | 2009-12-23 | 2013-05-14 | Intel Corporation | Methods to form memory devices having a capacitor with a recessed electrode |
US8502293B2 (en) | 2010-12-22 | 2013-08-06 | Intel Corporation | Capacitor with recessed plate portion for dynamic random access memory (DRAM) and method to form the same |
US20120161215A1 (en) * | 2010-12-22 | 2012-06-28 | Nick Lindert | Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same |
US20120223413A1 (en) | 2011-03-04 | 2012-09-06 | Nick Lindert | Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer |
SG192574A1 (en) | 2011-03-11 | 2013-09-30 | Fujifilm Electronic Materials | Novel etching composition |
US8519510B2 (en) * | 2011-06-21 | 2013-08-27 | Intel Corporation | Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same |
TWI577834B (zh) | 2011-10-21 | 2017-04-11 | 富士軟片電子材料美國股份有限公司 | 新穎的鈍化組成物及方法 |
CN102709270A (zh) * | 2012-05-23 | 2012-10-03 | 上海宏力半导体制造有限公司 | Mim电容器及其形成方法 |
US8709277B2 (en) * | 2012-09-10 | 2014-04-29 | Fujifilm Corporation | Etching composition |
US9741817B2 (en) * | 2016-01-21 | 2017-08-22 | Tower Semiconductor Ltd. | Method for manufacturing a trench metal insulator metal capacitor |
CN109509836B (zh) | 2017-09-14 | 2022-11-01 | 联华电子股份有限公司 | 形成存储器电容的方法 |
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US11088154B1 (en) * | 2020-02-11 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ferroelectric device and methods of fabrication thereof |
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2008
- 2008-09-30 US US12/286,338 patent/US7927959B2/en not_active Expired - Fee Related
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2009
- 2009-09-28 CN CN2009801376851A patent/CN102165580A/zh active Pending
- 2009-09-28 KR KR1020117007256A patent/KR101345926B1/ko active IP Right Grant
- 2009-09-28 WO PCT/US2009/058540 patent/WO2010039629A2/en active Application Filing
- 2009-09-28 EP EP09818322.1A patent/EP2329524A4/en not_active Withdrawn
- 2009-09-28 JP JP2011529301A patent/JP5358848B2/ja not_active Expired - Fee Related
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- 2011-02-16 US US13/028,400 patent/US8441057B2/en not_active Expired - Fee Related
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JP2002270798A (ja) * | 2001-03-08 | 2002-09-20 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US6436787B1 (en) * | 2001-07-26 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming crown-type MIM capacitor integrated with the CU damascene process |
US6670237B1 (en) * | 2002-08-01 | 2003-12-30 | Chartered Semiconductor Manufacturing Ltd. | Method for an advanced MIM capacitor |
JP2005032800A (ja) * | 2003-07-08 | 2005-02-03 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2005150159A (ja) * | 2003-11-11 | 2005-06-09 | Toshiba Corp | 半導体装置、及び、半導体装置の製造方法 |
US20050106809A1 (en) * | 2003-11-14 | 2005-05-19 | Shea Kevin R. | Reduced cell-to-cell shorting for memory arrays |
Also Published As
Publication number | Publication date |
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WO2010039629A2 (en) | 2010-04-08 |
KR20110063795A (ko) | 2011-06-14 |
CN102165580A (zh) | 2011-08-24 |
EP2329524A2 (en) | 2011-06-08 |
US8441057B2 (en) | 2013-05-14 |
JP5358848B2 (ja) | 2013-12-04 |
KR101345926B1 (ko) | 2013-12-27 |
US20130234290A1 (en) | 2013-09-12 |
US20100079924A1 (en) | 2010-04-01 |
EP2329524A4 (en) | 2013-05-15 |
WO2010039629A3 (en) | 2010-07-01 |
US7927959B2 (en) | 2011-04-19 |
US9224794B2 (en) | 2015-12-29 |
US20110134583A1 (en) | 2011-06-09 |
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