JP2012059921A - Semiconductor light-emitting device and manufacturing method of the same - Google Patents

Semiconductor light-emitting device and manufacturing method of the same Download PDF

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JP2012059921A
JP2012059921A JP2010201786A JP2010201786A JP2012059921A JP 2012059921 A JP2012059921 A JP 2012059921A JP 2010201786 A JP2010201786 A JP 2010201786A JP 2010201786 A JP2010201786 A JP 2010201786A JP 2012059921 A JP2012059921 A JP 2012059921A
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white
resist layer
semiconductor light
light emitting
layer
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JP5710915B2 (en
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Ryo Tamura
量 田村
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Citizen Holdings Co Ltd
Citizen Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To solve the problems that a void and a crack are generated when white ceramic mixing reflective fine particles into an inorganic binder for ensuring high reflectance is thickly applied on a circuit substrate, and that white ceramic ink is easy to peel off from the circuit substrate because it is hard, even if the white ceramic ink is made to be two layers so as to avoid generating the void and the crack.SOLUTION: An LED device 10 has an electrode 17 on an upper surface of a circuit substrate 22, and comprises at least a white resist layer 16 for covering a part of the electrode 17, and a white ceramic ink layer 15 for covering the white resist layer 16. Consequently, a reflection member made by a laminated body of the white resist layer 16 and the white ceramic ink layer 15 has high reflectance and light resistance, and a soft white resist layer 16 becomes a buffer to make the reflection member hard to peel off from the circuit substrate.

Description

回路基板上に反射部材と半導体発光素子を備えた半導体発光装置及びその製造方法に関する。   The present invention relates to a semiconductor light emitting device including a reflective member and a semiconductor light emitting element on a circuit board, and a method for manufacturing the same.

半導体発光素子(以後とくに断らない限りLED素子と呼ぶ)を回路基板に実装しパッケージ化した半導体発光装置(以後とくに断らない限りLED装置と呼ぶ)のなかで、発光効率を改善するため回路基板表面に白色の反射部材を備えたLED装置が知られている。   In a semiconductor light emitting device (hereinafter referred to as an LED device unless otherwise specified) in which a semiconductor light emitting element (hereinafter referred to as an LED device) is packaged and packaged on a circuit board, the surface of the circuit board is improved in order to improve luminous efficiency. An LED device having a white reflecting member is known.

例えば特許文献1の図1には白色レジスト層6(反射部材)を備えた光源装置10(LED装置)が示されている。光源装置10は基板1(回路基板)上に一対の電極2,3が形成され、これらの電極2,3と接続された発光ダイオードのチップ4(LED素子)はドーム状の透明樹脂7に封止されている。発光ダイオードのチップ4は一方の電極2上に配置され、この電極2と電気的に接続している。また、チップ4と他方の電極3とはワイヤ5によって電気的に接続している。この基板1上に形成された白色レジスト層6は、発光ダイオードのチップ4や、ワイヤ5と接続された電極3の端子付近が開口部となっており、開口部以外の部分では電極2,3を覆っている。開口部は矩形状となっており、開口部の壁面6Aはチップ4や電極3の端子に近い箇所にある。   For example, FIG. 1 of Patent Document 1 shows a light source device 10 (LED device) including a white resist layer 6 (reflecting member). The light source device 10 has a pair of electrodes 2 and 3 formed on a substrate 1 (circuit board), and a light emitting diode chip 4 (LED element) connected to the electrodes 2 and 3 is sealed in a dome-shaped transparent resin 7. It has been stopped. The light emitting diode chip 4 is disposed on one electrode 2 and is electrically connected to the electrode 2. The chip 4 and the other electrode 3 are electrically connected by a wire 5. The white resist layer 6 formed on the substrate 1 has an opening in the vicinity of the terminal of the electrode 3 connected to the chip 4 of the light emitting diode 4 or the wire 5, and the electrodes 2, 3 in the portion other than the opening. Covering. The opening has a rectangular shape, and the wall surface 6 </ b> A of the opening is in a location near the terminals of the chip 4 and the electrode 3.

レジスト層6の反射率を向上させるためにはレジスト層6を厚くする必要がある。このようにすると、例えばレジスト層下部まで露光光が届きにくくなりレジスト層が硬化しにくくなるような様々な問題が生じる。そこで特許文献1の図3には2層のレジスト層61,62を備えた光源装置12が示されている。段落0054には光源装置12において、2層のレジスト層61,62の積層により厚い白色レジスト層6が得られると共に、各レジスト層61,62を早く硬化させることができた、と記載されている。   In order to improve the reflectance of the resist layer 6, it is necessary to increase the thickness of the resist layer 6. In this case, for example, various problems occur such that the exposure light does not easily reach the lower part of the resist layer and the resist layer is hard to be cured. Therefore, FIG. 3 of Patent Document 1 shows a light source device 12 including two resist layers 61 and 62. Paragraph 0054 describes that, in the light source device 12, the thick white resist layer 6 was obtained by laminating the two resist layers 61 and 62, and the resist layers 61 and 62 could be cured quickly. .

特開2007−243226号公報 (図1、図3、段落0054)JP 2007-243226 A (FIG. 1, FIG. 3, paragraph 0054)

LED素子の発光により樹脂が劣化するため、反射部材として白色レジストの代わりに耐光性が高く硬化するとガラス質になる白色セラミックインクが使われるようになってきた。この白色セラミックインクは様々な課題があり、例えば充分な反射率を確保するためには白色レジストと同様に厚くしなければならないが、このときボイド(気泡)やクラックが生じる。これらを回避するため特許文献1を参考にして白色セラミックインクを2層化しても、白色セラミックインクが硬質であるため回路基板から剥がれやすいという課題が残る。   Since the resin deteriorates due to the light emitted from the LED element, a white ceramic ink that becomes glassy when cured with high light resistance is used instead of a white resist as a reflecting member. This white ceramic ink has various problems. For example, in order to ensure sufficient reflectivity, the white ceramic ink has to be thick like the white resist, but at this time, voids (bubbles) and cracks are generated. In order to avoid these problems, even if the white ceramic ink is formed in two layers with reference to Patent Document 1, the problem remains that the white ceramic ink is hard and easily peels off from the circuit board.

そこで本発明は、この課題に鑑みてなされたものであり、回路基板上に反射部材と半導体発光素子を備えた半導体発光装置及びその製造方法において、反射部材が充分な反射率と耐光性を備えながら回路基板と良好に密着する半導体発光装置及びその製造方法を提供することを目的とする。   Accordingly, the present invention has been made in view of this problem, and in a semiconductor light-emitting device including a reflective member and a semiconductor light-emitting element on a circuit board and a manufacturing method thereof, the reflective member has sufficient reflectance and light resistance. An object of the present invention is to provide a semiconductor light-emitting device that adheres well to a circuit board and a method for manufacturing the same.

本発明の半導体発光装置は、回路基板上に反射部材と半導体発光素子を備えた半導体発光装置において、
前記回路基板の上面に電極を有し、
少なくとも該電極の一部を覆う白色レジスト層と、
該白色レジスト層を覆う白色セラミックインク層とを備え、
該白色セラミックインク層が樹脂層で覆われている
ことを特徴とする。
The semiconductor light emitting device of the present invention is a semiconductor light emitting device comprising a reflective member and a semiconductor light emitting element on a circuit board.
Having an electrode on the upper surface of the circuit board;
A white resist layer covering at least a part of the electrode;
A white ceramic ink layer covering the white resist layer,
The white ceramic ink layer is covered with a resin layer.

前記電極がポストを備え、該ポストに前記半導体発光素子がフリップチップ実装されると良い。   The electrode may include a post, and the semiconductor light emitting element may be flip-chip mounted on the post.

前記ポストの上面と前記白色レジスト層の上面の高さが略一致していても良い。   The height of the upper surface of the post and the upper surface of the white resist layer may be substantially the same.

前記ポストに前記白色レジスト層又は前記白色セラミックインク層が接触していることが好ましい。   It is preferable that the white resist layer or the white ceramic ink layer is in contact with the post.

本発明の半導体発光装置の製造方法は、回路基板上に反射部材と半導体発光素子を備えた半導体発光装置の製造方法において、
前記回路基板が連結した集合基板を準備する工程と、
白色レジスト層を形成する工程と、
該白色レジスト層に開口部を形成する工程と、
該白色レジスト層に白色セラミックインク層を積層する工程と、
前記半導体発光素子を実装する工程と、
該半導体発光素子を封止する工程と、
前記集合基板から前記半導体発光装置を個片化する工程と
を備えることを特徴とする。
A method for manufacturing a semiconductor light emitting device of the present invention is a method for manufacturing a semiconductor light emitting device including a reflective member and a semiconductor light emitting element on a circuit board.
Preparing a collective substrate connected to the circuit board;
Forming a white resist layer;
Forming an opening in the white resist layer;
Laminating a white ceramic ink layer on the white resist layer;
Mounting the semiconductor light emitting element;
Sealing the semiconductor light emitting element;
And singulating the semiconductor light emitting device from the aggregate substrate.

前記白色レジスト層に開口部を形成する工程の後に、
第2レジスト層を形成する工程と、
前記白色レジストの開口部と重なる位置に前記第2レジスト層の開口部を形成する工程と、
該開口部に導電性のポストを形成する工程と、
前記第2レジストを除去する工程と
を備えても良い。
After the step of forming an opening in the white resist layer,
Forming a second resist layer;
Forming an opening of the second resist layer at a position overlapping the opening of the white resist;
Forming a conductive post in the opening;
A step of removing the second resist.

前記ポストを形成する工程を備えるとき、前記白色レジスト層に白色セラミックインク層を積層する工程のあと、該白色セラミックインク層を研磨する工程を備えていても良い。   When the step of forming the post is provided, a step of polishing the white ceramic ink layer may be provided after the step of laminating the white ceramic ink layer on the white resist layer.

本発明の半導体発光装置は、回路基板上に白色レジスト層を形成し、さらに白色レジスト層上に白色セラミックインク層が積層している。この構造により反射部材は充分な厚さで高い反射率を維持する。また白色レジスト層を白色セラミックインク層が覆っているので、白色セラミックインク層が半導体発光素子の発光による白色レジスト層の劣化を防止している。白色レジスト層は白色セラミックインク層より軟質であるため、熱膨張や回路基板の変形にともなって生じる反射部材内の応力を緩和する。同様に白色レジスト層と白色セラミックインク層の界面付近に発生する応力も白色レジスト層が緩和する。以上の結果、本発明の半導体発光装置は、反射部材が充分な反射率と耐光性を備えながら回路基板と良好に密着することができる。   In the semiconductor light emitting device of the present invention, a white resist layer is formed on a circuit board, and a white ceramic ink layer is laminated on the white resist layer. With this structure, the reflecting member maintains a high reflectance with a sufficient thickness. Further, since the white ceramic ink layer covers the white resist layer, the white ceramic ink layer prevents the deterioration of the white resist layer due to light emission of the semiconductor light emitting element. Since the white resist layer is softer than the white ceramic ink layer, the stress in the reflecting member caused by thermal expansion or deformation of the circuit board is relieved. Similarly, the white resist layer also relaxes the stress generated near the interface between the white resist layer and the white ceramic ink layer. As a result of the above, the semiconductor light emitting device of the present invention can be satisfactorily adhered to the circuit board while the reflecting member has sufficient reflectance and light resistance.

同様に本発明の半導体発光装置の製造方法は、回路基板上に白色レジスト層と白色セラミックインク層を積層させることにより、反射部材が充分な反射率と耐光性を備えながら回路基板と良好に密着する半導体発光装置を製造できる。   Similarly, in the method for manufacturing a semiconductor light emitting device of the present invention, the white resist layer and the white ceramic ink layer are laminated on the circuit board, so that the reflecting member has sufficient reflectivity and light resistance, and adheres well to the circuit board. A semiconductor light emitting device can be manufactured.

本発明の第1実施形態におけるLED装置の断面図。The sectional view of the LED device in a 1st embodiment of the present invention. 図1に示すLED装置の製造方法の説明図。Explanatory drawing of the manufacturing method of the LED apparatus shown in FIG. 本発明の第2実施形態におけるLED装置の断面図。Sectional drawing of the LED apparatus in 2nd Embodiment of this invention. 図3に示すLED装置の製造方法の説明図。Explanatory drawing of the manufacturing method of the LED apparatus shown in FIG. 図3に示すLED装置の製造方法の説明図。Explanatory drawing of the manufacturing method of the LED apparatus shown in FIG.

以下、添付図1〜5を参照しながら本発明の好適な実施形態について詳細に説明する。なお図面の説明において、同一または相当要素には同一の符号を付し、重複する説明は省略する。また説明のため部材の縮尺は適宜変更している。
(第1実施形態)
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted. For the sake of explanation, the scale of the members is changed as appropriate.
(First embodiment)

図1と図2により本発明の第1本実施形態について説明する。図1は本実施形態のLED装置10(半導体発光装置)の構造を説明するための断面図である。回路基板22は、電極17,19、スルーホール18、及び板材20からなる。回路基板22の上面に形成された電極17は、回路基板22の下面に形成された電極19とスルーホール18で接続している。電極17上にはLED素子21(半導体発光素子)がフリップチップ実装されている。LED素子21はサファイア基板12の下面に半導体層13を備え、半導体層13にはアノードとカソードに対応するバンプ14が付着している。LED素子21を含む回路基板22の上部は樹脂層11で封止されている。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view for explaining the structure of an LED device 10 (semiconductor light emitting device) according to this embodiment. The circuit board 22 includes electrodes 17 and 19, a through hole 18, and a plate material 20. The electrode 17 formed on the upper surface of the circuit board 22 is connected to the electrode 19 formed on the lower surface of the circuit board 22 by a through hole 18. An LED element 21 (semiconductor light emitting element) is flip-chip mounted on the electrode 17. The LED element 21 includes a semiconductor layer 13 on the lower surface of the sapphire substrate 12, and bumps 14 corresponding to the anode and the cathode are attached to the semiconductor layer 13. The upper part of the circuit board 22 including the LED elements 21 is sealed with the resin layer 11.

白色レジスト層16は、LED素子21の実装領域が開口するようにして電極17の一部を含む回路基板22の上面全体を覆っている。白色レジスト層16上には白色セラミックインク層15が積層している。白色セラミックインク層15の開口部は白色レジスト層16の開口部よりやや広い。   The white resist layer 16 covers the entire upper surface of the circuit board 22 including a part of the electrode 17 so that the mounting region of the LED element 21 is opened. A white ceramic ink layer 15 is laminated on the white resist layer 16. The opening of the white ceramic ink layer 15 is slightly wider than the opening of the white resist layer 16.

回路基板22の板材20はBTレジン(三菱瓦斯化学の商標名であり、ビスマレイミドトリアジン樹脂等からなる熱硬化性樹脂)等の樹脂であるが、セラミック、金属であっても良い。電極17,19は銅箔上にニッケルと金を積層した金属パターンである。スルーホール18の内部には金属ペーストが充填されている。LED素子21のサファイア基板12は厚さが80〜150μm、半導体層13は発光層を含み厚さが約7μm、バンプ14は金バンプからなり厚さが20〜30μmである。樹脂層11はシリコーン樹脂にYAG等の蛍光体を混錬した蛍光樹脂である。   The plate member 20 of the circuit board 22 is a resin such as BT resin (trade name of Mitsubishi Gas Chemical, a thermosetting resin made of bismaleimide triazine resin or the like), but may be ceramic or metal. The electrodes 17 and 19 are metal patterns in which nickel and gold are laminated on a copper foil. The through hole 18 is filled with a metal paste. The sapphire substrate 12 of the LED element 21 has a thickness of 80 to 150 μm, the semiconductor layer 13 includes a light emitting layer and has a thickness of about 7 μm, and the bumps 14 are gold bumps and have a thickness of 20 to 30 μm. The resin layer 11 is a fluorescent resin obtained by kneading a phosphor such as YAG in a silicone resin.

白色レジスト層16は二酸化チタン等の反射性微粒子を混錬した感光性樹脂を硬化させたものであり、厚さは15μm程度である。白色セラミックインク層15は、オルガノポリシロキサン等のバインダ中に触媒や溶媒とともに二酸化チタン等の反射性粒子を混練した混合物を焼結したものであり、厚さは20μm程度である。焼結後の白色セラミックインク層15はガラス質(無機質)となる。   The white resist layer 16 is obtained by curing a photosensitive resin kneaded with reflective fine particles such as titanium dioxide, and has a thickness of about 15 μm. The white ceramic ink layer 15 is obtained by sintering a mixture obtained by kneading reflective particles such as titanium dioxide together with a catalyst and a solvent in a binder such as organopolysiloxane, and has a thickness of about 20 μm. The white ceramic ink layer 15 after sintering becomes vitreous (inorganic).

図2によりLED装置10の製造方法を説明する。図2はLED装置10の製造方法の説明図である。(a)は、回路基板22(番号は図示せず)が連結した集合基板25を準備する工程である。なお集合基板25には数百から数千個の回路基板領域が配列しているが、図2では簡単のため3個にしている。また図中、板材20上には多数形成された電極17のみ示し、スルーホール18及び電極19は省略した。   A method of manufacturing the LED device 10 will be described with reference to FIG. FIG. 2 is an explanatory diagram of a method for manufacturing the LED device 10. (A) is a step of preparing a collective board 25 to which circuit boards 22 (numbers are not shown) are connected. Note that hundreds to thousands of circuit board regions are arranged on the collective board 25, but in FIG. In the drawing, only a large number of electrodes 17 formed on the plate member 20 are shown, and the through holes 18 and the electrodes 19 are omitted.

(b)は白色レジスト層16を形成する工程である。コーター又はスクリーン印刷により集合基板25の上面に白色レジスト層16を形成する。白色レジスト層16は80℃(約30分間)で仮硬化する。   (B) is a step of forming the white resist layer 16. The white resist layer 16 is formed on the upper surface of the collective substrate 25 by a coater or screen printing. The white resist layer 16 is temporarily cured at 80 ° C. (about 30 minutes).

(c)は白色レジスト層16に開口部26を形成する工程である。フォトマスクを使って開口させる領域(開口部26)以外を露光し、現像して開口部26を形成する。その後、150℃(約1時間)で白色レジスト層16を硬化させる。   (C) is a step of forming the opening 26 in the white resist layer 16. An area other than the area (opening 26) to be opened is exposed using a photomask, and developed to form the opening 26. Thereafter, the white resist layer 16 is cured at 150 ° C. (about 1 hour).

(d)は白色レジスト層16に白色セラミックインク層15を積層する工程である。スクリーン印刷法により白色セラミックインクを白色レジスト層16上に塗布する。印刷の位置精度の関係で白色レジスト層16の開口部26より白色セラミックインク層15の開口部の方が大きくなっている。   (D) is a step of laminating the white ceramic ink layer 15 on the white resist layer 16. White ceramic ink is applied onto the white resist layer 16 by screen printing. Due to the positional accuracy of printing, the opening of the white ceramic ink layer 15 is larger than the opening 26 of the white resist layer 16.

(e)はLED素子21を実装する工程である。集合基板25の電極17のピッチで粘着シート(図示せず)上に配列させた多数のLED素子21を、同時に加圧加熱して集合基板25の電極17に接合する。LED素子21のバンプ14(番号は図示せず)の下面には予め金錫共晶層を形成しておく。金錫共晶接合は融点が約300℃に設定できるため回路基板22をマザー基板(図示せず)に半田リフロー(約260℃)するとき接合部が固体のままであるという特徴がある。   (E) is a process of mounting the LED element 21. A large number of LED elements 21 arranged on an adhesive sheet (not shown) at the pitch of the electrodes 17 of the collective substrate 25 are simultaneously heated under pressure and joined to the electrodes 17 of the collective substrate 25. A gold-tin eutectic layer is formed in advance on the lower surface of the bump 14 (number is not shown) of the LED element 21. Gold-tin eutectic bonding has a feature that the melting point can be set to about 300 ° C., so that when the circuit board 22 is solder-reflowed (about 260 ° C.) to a mother board (not shown), the bonding portion remains solid.

(f)はLED素子21を封止する工程である。集合基板25を金型に装填してから、YAG等の蛍光体を混練したシリコーン樹脂を金型に充填し、シリコーン樹脂を約150℃で加熱硬化させ樹脂層11を形成する。   (F) is a step of sealing the LED element 21. After the assembly substrate 25 is loaded into a mold, a silicone resin kneaded with a phosphor such as YAG is filled into the mold, and the silicone resin is heated and cured at about 150 ° C. to form the resin layer 11.

(g)は集合基板25からLED装置10を個片化する工程である。ダイサー(図示せず)で樹脂層11を備えた集合基板25を切断し、個片化したLED装置10を得る。   (G) is a process of separating the LED device 10 from the collective substrate 25. The collective substrate 25 provided with the resin layer 11 is cut with a dicer (not shown) to obtain the LED device 10 separated into pieces.

本実施形態のLED装置10は樹脂層11の側面からも光が出射するが、LED装置10の外周に反射枠を設け配光を調整しても良い。また本実施形態の製造方法では白色レジスト層16を形成するのに手番の長いフォトリソグラフィ法を適用しているが、集合基板25には多数の回路基板領域が含まれているのでLED装置10当りの工程負荷増は小さい。
(第2実施形態)
The LED device 10 according to the present embodiment emits light also from the side surface of the resin layer 11. However, the light distribution may be adjusted by providing a reflection frame on the outer periphery of the LED device 10. Further, in the manufacturing method of the present embodiment, a long photolithography method is applied to form the white resist layer 16. However, since the collective substrate 25 includes a large number of circuit board regions, the LED device 10. The increase in process load per hit is small.
(Second Embodiment)

図3〜図5により本発明の第2本実施形態について説明する。第1実施形態と同等の部材は同じ番号で示し説明を省略する。図3は本実施形態のLED装置30(半導体発光装置)の構造を説明するための断面図である。電極17上には導電性のポスト31が形成されている。このポスト31は銅からなり上面にニッケルと金がメッキされている。ポスト31を除く回路基板22の上面全体を白色レジスト層36が覆っている。さらに白色レジスト層36上には白色セラミックインク層35が積層している。白色セラミックインク層35の上面とポスト31の上面は略等しい。ポスト31上にはLED素子21がフリップ実装されており、LED素子21を含む回路基板22の上部は樹脂層11で覆われている。   A second embodiment of the present invention will be described with reference to FIGS. The same members as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. FIG. 3 is a cross-sectional view for explaining the structure of the LED device 30 (semiconductor light emitting device) of the present embodiment. A conductive post 31 is formed on the electrode 17. The post 31 is made of copper, and nickel and gold are plated on the upper surface. A white resist layer 36 covers the entire top surface of the circuit board 22 except for the posts 31. Further, a white ceramic ink layer 35 is laminated on the white resist layer 36. The upper surface of the white ceramic ink layer 35 and the upper surface of the post 31 are substantially equal. The LED element 21 is flip-mounted on the post 31, and the upper part of the circuit board 22 including the LED element 21 is covered with the resin layer 11.

図4と図5によりLED装置30の製造方法を説明する。図4と図5はLED装置30の製造方法の説明図である。(a)は回路基板22が連結した集合基板25を準備する工程、(b)は白色レジスト層36を形成する工程であり、それぞれ実施形態1の図2(a),(b)と等しい。   A method for manufacturing the LED device 30 will be described with reference to FIGS. 4 and 5 are explanatory diagrams of the method for manufacturing the LED device 30. FIG. (A) is a step of preparing the collective substrate 25 to which the circuit boards 22 are connected, and (b) is a step of forming the white resist layer 36, which is the same as FIGS. 2 (a) and 2 (b) of the first embodiment.

(c)は白色レジスト層36に開口部41を形成する工程である。白色レジスト層36はポスト31を形成する領域に開口部41がある。この工程も第1実施形態の図2(c)と同様に露光・現像で開口部41を形成し、150℃で白色レジスト層36を硬化させる。 (C) is a step of forming the opening 41 in the white resist layer 36. The white resist layer 36 has an opening 41 in a region where the post 31 is formed. In this process, as in FIG. 2C of the first embodiment, the opening 41 is formed by exposure and development, and the white resist layer 36 is cured at 150 ° C.

(d)は第2レジスト層42を形成する工程である。第2レジスト層42は感光性ドライフィルムであり、白色レジスト層36の上面に貼りつける。   (D) is a step of forming the second resist layer 42. The second resist layer 42 is a photosensitive dry film and is attached to the upper surface of the white resist layer 36.

(e)は白色レジスト層36の開口部41と重なる位置に第2レジスト層42の開口部43を形成する工程である。感光性ドライフィルム(第2レジスト層42)も白色レジスト層36と同様に露光・現像でパターニングする。   (E) is a step of forming the opening 43 of the second resist layer 42 at a position overlapping the opening 41 of the white resist layer 36. The photosensitive dry film (second resist layer 42) is patterned by exposure and development in the same manner as the white resist layer 36.

(f)は開口部43に導電性のポストを形成する工程である。電解メッキ法によりポスト31を成長させる。なお電解メッキに対応できるよう、周知の設計技法により集合基板25の状態では全ての電極17(又は電極19)は電気的に接続させておく。   (F) is a step of forming a conductive post in the opening 43. Posts 31 are grown by electrolytic plating. Note that all the electrodes 17 (or electrodes 19) are electrically connected in the state of the collective substrate 25 by a well-known design technique so as to cope with electrolytic plating.

(g)は第2レジストを除去する工程である。剥離液を用いて感光性ドライフィルム(第2レジスト層42)だけを除去する。この結果、白色レジスト層36からポスト31の先端が突き出る。   (G) is a step of removing the second resist. Only the photosensitive dry film (second resist layer 42) is removed using a stripping solution. As a result, the tip of the post 31 protrudes from the white resist layer 36.

(h)は白色レジスト層36に白色セラミックインク層35を積層する工程である。スクリーン印刷機やコーターを使って白色レジスト層36の上面全体に亘り白色セラミックインク(硬化前)を塗布する。このあと約150℃で白色セラミックインク層35を硬化させる。このとき白色セラミックインク層35が白色ポスト31の上面を僅かに覆うようにする。 (H) is a step of laminating the white ceramic ink layer 35 on the white resist layer 36. A white ceramic ink (before curing) is applied to the entire upper surface of the white resist layer 36 using a screen printer or a coater. Thereafter, the white ceramic ink layer 35 is cured at about 150 ° C. At this time, the white ceramic ink layer 35 slightly covers the upper surface of the white post 31.

(i)は白色セラミックインク層35を研磨する工程である。ポスト31の上面が露出するまで白色セラミックインク層35を研磨する。その後、ポスト31の上面にニッケル層と金層を電解メッキ法で形成する。   (I) is a step of polishing the white ceramic ink layer 35. The white ceramic ink layer 35 is polished until the upper surface of the post 31 is exposed. Thereafter, a nickel layer and a gold layer are formed on the upper surface of the post 31 by electrolytic plating.

(j)はLED素子21を実装する工程である。電極17に代わりにポスト31上に実装すること以外は実施形態1の図2(e)と同様である。(k)はLED素子21を封止する工程、(l)は集合基板25からLED装置30を個片化する工程であり、それぞれ実施形態1の図2(f),(g)と同様である。   (J) is a process of mounting the LED element 21. Except for mounting on the post 31 instead of the electrode 17, it is the same as FIG. 2 (e) of the first embodiment. (K) is a step of sealing the LED element 21, and (l) is a step of separating the LED device 30 from the collective substrate 25, which is the same as in FIGS. 2 (f) and 2 (g) of the first embodiment. is there.

本実施形態では電極17がポスト31を備え、このポスト31にLED素子21がフリップチップ実装されていた。このようすると反射部材を厚くできることに加え、ポスト31を除く回路基板22の表面を隙間なく反射部材が占められるため高い反射率を維持できる。   In this embodiment, the electrode 17 includes a post 31, and the LED element 21 is flip-chip mounted on the post 31. In this way, the reflection member can be made thick, and the reflection member can be occupied without gaps on the surface of the circuit board 22 excluding the post 31, so that a high reflectance can be maintained.

本実施形態ではポスト31に白色レジスト層36及び白色セラミックインク層35が接触していた。工程を節約するため白色レジスト層36又は白色セラミックインク層35を印刷法で形成し手も良い。このとき白色レジスト層36又は白色セラミックインク層35がポスト31に接触しない状態となる。ポスト31と白色レジスト層36又は白色セラミックインク層35との間に隙間があると反射率の低下を招くばかりでなく、板材20が樹脂であると板材20の光劣化を招く。高い反射率と信頼性が必要な場合には、ポスト31に白色レジスト層36及び白色セラミックインク層35が接触していることが必要になる。   In this embodiment, the white resist layer 36 and the white ceramic ink layer 35 are in contact with the post 31. In order to save the process, the white resist layer 36 or the white ceramic ink layer 35 may be formed by a printing method. At this time, the white resist layer 36 or the white ceramic ink layer 35 is not in contact with the post 31. If there is a gap between the post 31 and the white resist layer 36 or the white ceramic ink layer 35, not only will the reflectance be lowered, but if the plate material 20 is a resin, the plate material 20 will be lightly degraded. When high reflectance and reliability are required, it is necessary that the white resist layer 36 and the white ceramic ink layer 35 are in contact with the post 31.

本実施形態ではポスト31の上面と白色セラミックインク層35の上面の高さが略一致していた。これは白色セラミックインク層35を形成後、研磨によりポスト31の上面を
露出させた結果である。これに対し周知の方法で白色セラミックインクの塗布量を正確にし制御することで図5(i)の研磨工程を省くことは可能である。しかしながら本実施形態は、塗布量の高精度な制御の代わりに研磨を採用し製造工程を容易にした。
In the present embodiment, the height of the upper surface of the post 31 and the upper surface of the white ceramic ink layer 35 are substantially the same. This is a result of exposing the upper surface of the post 31 by polishing after the white ceramic ink layer 35 is formed. On the other hand, it is possible to omit the polishing step of FIG. 5 (i) by accurately controlling the application amount of the white ceramic ink by a known method. However, this embodiment employs polishing instead of high-precision control of the coating amount to facilitate the manufacturing process.

第1および第2実施形態では回路基板22にLED素子21をフリップチップ実装していた。しかしながらLED素子21の実装形態はフリップチップ実装に限定されず、LED素子21のサファイア基板12を回路基板22にダイボンディングし、半導体層13を上方に向けた実装(フェイスアップ実装)であっても良い。   In the first and second embodiments, the LED element 21 is flip-chip mounted on the circuit board 22. However, the mounting form of the LED element 21 is not limited to flip-chip mounting. Even if the sapphire substrate 12 of the LED element 21 is die-bonded to the circuit board 22 and the semiconductor layer 13 faces upward (face-up mounting). good.

10,30…LED装置(半導体発光装置)、
11…樹脂層、
12…サファイア基板、
13…半導体層、
14…バンプ、
15,35…白色セラミックインク層、
16,36…白色レジスト層、
17、19…電極、
18…スルーホール、
20…板材、
21…LED素子(半導体発光素子)、
22…回路基板、
25…集合基板、
26,41,43…開口部、
31…ポスト、
42…第2レジスト層。
10, 30 ... LED device (semiconductor light emitting device),
11 ... resin layer,
12 ... sapphire substrate,
13 ... semiconductor layer,
14 ... Bump,
15, 35 ... white ceramic ink layer,
16, 36 ... white resist layer,
17, 19 ... electrodes,
18 ... Through hole,
20 ... plate material,
21 ... LED element (semiconductor light emitting element),
22 ... circuit board,
25. Collective board,
26, 41, 43 ... opening,
31 ... Post,
42 ... Second resist layer.

Claims (7)

回路基板上に反射部材と半導体発光素子を備えた半導体発光装置において、
前記回路基板の上面に電極を有し、
少なくとも該電極の一部を覆う白色レジスト層と、
該白色レジスト層を覆う白色セラミックインク層とを備え、
該白色セラミックインク層が樹脂層で覆われている
ことを特徴とする半導体発光装置。
In a semiconductor light emitting device including a reflective member and a semiconductor light emitting element on a circuit board,
Having an electrode on the upper surface of the circuit board;
A white resist layer covering at least a part of the electrode;
A white ceramic ink layer covering the white resist layer,
A semiconductor light emitting device, wherein the white ceramic ink layer is covered with a resin layer.
前記電極がポストを備え、該ポストに前記半導体発光素子がフリップチップ実装されることを特徴とする請求項1に記載の半導体発光装置。   The semiconductor light emitting device according to claim 1, wherein the electrode includes a post, and the semiconductor light emitting element is flip-chip mounted on the post. 前記ポストの上面と前記白色レジスト層の上面の高さが略一致してることを特徴とする請求項2に記載の半導体発光装置。   The semiconductor light emitting device according to claim 2, wherein a height of an upper surface of the post and an upper surface of the white resist layer substantially coincide with each other. 前記ポストに前記白色レジスト層又は前記白色セラミックインク層が接触していることを特徴とする請求項2又は3に記載の半導体発光装置。   The semiconductor light emitting device according to claim 2, wherein the white resist layer or the white ceramic ink layer is in contact with the post. 回路基板上に反射部材と半導体発光素子を備えた半導体発光装置の製造方法において、
前記回路基板が連結した集合基板を準備する工程と、
白色レジスト層を形成する工程と、
該白色レジスト層に開口部を形成する工程と、
該白色レジスト層に白色セラミックインク層を積層する工程と、
前記半導体発光素子を実装する工程と、
該半導体発光素子を封止する工程と、
前記集合基板から前記半導体発光装置を個片化する工程と
を備えることを特徴とする半導体発光装置の製造方法。
In a method for manufacturing a semiconductor light emitting device including a reflective member and a semiconductor light emitting element on a circuit board,
Preparing a collective substrate connected to the circuit board;
Forming a white resist layer;
Forming an opening in the white resist layer;
Laminating a white ceramic ink layer on the white resist layer;
Mounting the semiconductor light emitting element;
Sealing the semiconductor light emitting element;
And a step of separating the semiconductor light emitting device from the collective substrate.
前記白色レジスト層に開口部を形成する工程の後に、
第2レジスト層を形成する工程と、
前記白色レジストの開口部と重なる位置に前記第2レジスト層の開口部を形成する工程と、
該開口部に導電性のポストを形成する工程と、
前記第2レジストを除去する工程と
を備えることを特徴とする請求項5に記載の半導体発光装置の製造方法。
After the step of forming an opening in the white resist layer,
Forming a second resist layer;
Forming an opening of the second resist layer at a position overlapping the opening of the white resist;
Forming a conductive post in the opening;
The method for manufacturing a semiconductor light emitting device according to claim 5, further comprising a step of removing the second resist.
前記白色レジスト層に白色セラミックインク層を積層する工程のあと、該白色セラミックインク層を研磨する工程を備えることを特徴とする請求項6に記載の半導体発光装置の製造方法。

The method of manufacturing a semiconductor light emitting device according to claim 6, further comprising a step of polishing the white ceramic ink layer after the step of laminating the white ceramic ink layer on the white resist layer.

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