JP2012044003A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】
実施形態の半導体装置は、基板と、前記基板上に設けられた半導体層と、前記半導体層上に設けられ、少なくとも2つの開口を有し、窒化物を含む第1表面パッシベーション膜と、前記第1表面パッシベーション膜の上面及び側面を覆う第2表面パッシベーション膜と、前記第2表面パッシベーション膜上の一部に設けられたゲート電極と、前記2つの開口にそれぞれ設けられたソース電極およびドレイン電極と、を有する。前記第2表面パッシベーション膜は、前記ゲート電極、前記ソース電極、および前記ドレイン電極よりも融点が高い材料で形成される。
【選択図】図1
Description
第1の実施形態に係る半導体装置について図1を使って説明する。図1は、半導体装置であるゲート絶縁膜を有する高電子移動度トランジスタ(High Electron Mobility Transistor)の断面を示す図である。この薄膜トランジスタは、基板1と、基板1上に設けられた半導体層20と、半導体層20上に設けられ、複数の開口(第1の開口、第2の開口、第3の開口)X、Y、Zを有する第1パッシベーション膜6と、第1パッシベーション膜6の上面及び側面、及び第1パッシベーション膜6の開口Yを覆う第2パッシベーション膜8とを有する。さらに、この電界効果トランジスタは、開口Yを覆う第2パッシベーション膜8上に設けられたゲート電極14と、開口X、Z上に設けられたソース電極15、ドレイン電極16と、を有する。半導体層20は、基板1側から順番にバッファ層2、チャネル層3、スペーサ層4、バリア層5が積層されたものである。
第2の実施形態に係る半導体装置について、図12を使って説明する。図12は半導体装置の一断面を示す図である。
第3の実施形態について図12を使って説明する。図13は半導体装置の一断面を示す図である。
第4の実施形態を、図14を使って説明する。図14は半導体装置の一断面を示す図である。
第5の実施形態について図15を使って説明する。この半導体装置は、半導体装置が破壊に至る耐圧を向上する目的で、ゲート電極14とソース電極15との距離よりも、ゲート電極14とドレイン電極16との距離の方を長く設定している。例えば、600Vの耐圧を要する半導体装置では、ゲート電極14とドレイン電極16間の距離は、5〜15ミクロン程度が好ましく、10ミクロンがより好ましい。この時、ゲート電極14とソース電極15との距離は、2ミクロン以下が好ましく、1ミクロンがより好ましい。
第6の実施形態について図16を使って説明する。図16は、半導体装置の一断面を示す図である。ソース電極15、ドレイン電極16の下にある第1表面パッシベーション膜6の開口X、Zに対応するように、バリア層5にも開口がもうけられている。バリア層5の開口は、スペーサ層4まで貫通する開口である。このバリア層5の開口X、Z側面は第2表面パッシベーション膜8で覆われている。また、ゲート電極14の下の第1表面パッシベーション膜6には開口が設けられていない。
第1の実施形態における半導体装置の電極の他の製造方法について、図17〜図22を使って説明する。電極以外の製造方法(図2乃至図11)は、第1の実施形態と同じであるので、同じ部分の詳細な説明は省略する。
2 バッファ層
3 チャネル層
4 スペーサ層
5 バリア層
6 第1表面パッシベーション膜
71、72、73,74、75 フォトレジスト
8 第2表面パッシベーション膜
9 オーミック電極コンタクト面
14 ゲート電極
15 ソース電極
16 ドレイン電極
17 第2表面パッシベーション膜
X、Y、Z 開口
Claims (8)
- 基板と、
前記基板上に設けられた半導体層と、
前記半導体層上に設けられ、少なくとも2つの開口を有し、窒化物を含む第1表面パッシベーション膜と、
前記第1表面パッシベーション膜の上面及び側面を覆う第2表面パッシベーション膜と、
前記第2表面パッシベーション膜上の一部に設けられたゲート電極と、
前記2つの開口にそれぞれ設けられたソース電極およびドレイン電極と、
を有し、
前記第2表面パッシベーション膜は、前記ゲート電極、前記ソース電極、および前記ドレイン電極よりも融点が高い材料で形成された半導体装置。 - 前記第1表面パッシベーション膜は開口を有し、前記開口は前記第2表面パッシベーション膜および前記ゲート電極の一部に覆われている請求項1に記載の半導体装置。
- 前記第1表面パッシベーション膜の側面は、順テーパ状である請求項2に記載の半導体装置。
- 前記第2表面パッシベーション膜は、2以上の膜が積層されて形成されている請求項2に記載の半導体装置。
- 前記開口は前記第2表面パッシベーション膜と前記半導体層が接するように貫通しており、前記開口部分に対応する前記半導体層の上面は凹状になっている請求項2に記載の半導体装置。
- 前記半導体層は、前記ソース電極及び前記ドレイン電極が設けられた位置に開口を有する請求項2に記載の半導体装置。
- 請求項1から5に記載の半導体装置において、前記ゲート電極が、前記ソース電極と前記ドレイン電極と、同一のメタル積層構造から構成されることを特徴とする半導体装置。
- 前記半導体層上に、前記第1表面パッシベーション膜を設ける工程と、
前記第1表面パッシベーション膜に第1の開口、第2の開口、および第3の開口を形成する工程と、
前記第1表面パッシベーション膜、前記開口から露出した前記半導体層、および前記開口の側面を覆う第2表面パッシベーション膜を成膜する工程と、
前記開口の側面を覆う部分を残して、前記第2表面パッシベーション膜の前記第1の開口、第2の開口を覆う部分を開口する工程と、
前記第1の開口の上にソース電極を形成し、前記第2の開口の上にドレイン電極を形成し、前記第3の開口の上にゲート電極を形成する工程と、
前記ソース電極、前記ドレイン電極、前記ゲート電極を熱処理する工程と、
を備え、前記第2パッシベーション膜の材料は前記ゲート電極、前記ソース電極および前記ドレイン電極よりも融点が高い、請求項1から5に記載の半導体装置の製造方法。
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