JP2012033834A - 半導体装置およびその製造方法ならびに不揮発性半導体記憶装置 - Google Patents
半導体装置およびその製造方法ならびに不揮発性半導体記憶装置 Download PDFInfo
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Abstract
【解決手段】MOSFETと、トンネル接合を有するトンネルバイポーラトランジスタを組み合わせることにより、低電圧であっても、ゲート電位変化に対してドレイン電流が急峻な変化(S値が60mV/桁よりも小さい)を示す半導体素子を構成する。
【選択図】図1
Description
<本願発明の回路構成による特徴説明>
従来のMOSFETのドレイン領域(ドレイン拡散層)内にトンネルダイオード素子を形成し、基板電極を用いたトンネルバイポーラトランジスタを形成することにより、上述した目的を達成することができる。トンネルバイポーラトランジスタとは、エミッタ―ベース間にトンネル接合を持ったバイポーラトランジスタのことである。後で製造工程(加工プロセス)をもとに詳しく説明するが、この構造では、集積性の問題は生じることはない。すなわちプレーナ技術においてMOSFETのドレイン領域(ドレイン拡散層)およびソース領域(ソース拡散層)は、ゲート電極に対してイオン打ち込み法を用いることで自己整合的に形成される。そのため、ゲート電極を小さく形成すれば、それに合わせて素子特性を決めるドレイン領域およびソース領域も極めて小さく(近接させて)形成することができる。この結果、素子性能を向上させながら全体を小さくできるので、集積性を高くできる要因になっている。現在、半導体産業において広く用いられているスペーサ技術を用いると、本発明のトンネルダイオードをゲート電極に対して自己整合的に形成することができる。そのため、本発明の構造によれば集積性の問題を生じないことは明らかである。
続いて、本願発明における半導体素子のデバイス構造の観点から、本願発明の特徴について説明する。図4は、本実施の形態1における半導体素子を上部から見た平面図である。図4において、X方向に離間して並ぶようにn型半導体領域NRsとn型半導体領域NRbが形成されている。そして、n型半導体領域NRbの上部にはp型半導体領域PRdが形成されている。このp型半導体領域PRdと電気的に接続するようにプラグPLG1が形成され、n型半導体領域NRsと電気的に接続するようにプラグPLG2が形成されている。さらに、離間されて配置されているn型半導体領域NRsと半導体領域NRbの間をY方向に延在するようにゲート電極Gが形成されている。そして、ゲート電極Gの一端部でゲート電極GはプラグPLG3と電気的に接続されている。
本実施の形態1における半導体装置は上記のように構成されており、以下にその製造方法について図面を参照しながら説明する。
前記実施の形態1では、nチャネル型MOSFETとPNP型トンネルバイポーラトランジスタを組み合わせたnチャネル型半導体素子について説明したが、本願発明の半導体素子では、pチャネル型MOSFETとNPN型トンネルバイポーラトランジスタを組み合わせたpチャネル型半導体素子も形成できる。したがって、本願発明の半導体素子では、nチャネル型半導体素子とpチャネル型半導体素子とを利用して相補型(Complementary)の半導体素子を形成することができる。本実施の形態2では、nチャネル型半導体素子とpチャネル型半導体素子を組み合わせた相補型半導体素子について説明する。特に、本実施の形態2では、相補型半導体素子を利用した回路として、インバータ回路を例に挙げて説明する。
本実施の形態3では、同一の半導体基板上に、本願発明における半導体素子と、単体MOSFETからなる単体トランジスタとを形成する例について説明する。
本実施の形態4では、SOI(Silicon On Insulator)基板上に本願発明の半導体素子を形成する例について説明する。図37は、本実施の形態4における半導体素子を上部から見た平面図である。図37において、X方向に離間して並ぶようにn型半導体領域NRsとn型半導体領域NRbが形成されている。そして、n型半導体領域NRbの上部にはp型半導体領域PRdが形成されている。このp型半導体領域PRdと電気的に接続するようにプラグPLG1が形成されている。また、n型半導体領域NRsの外側領域には、p型半導体領域PRcが形成されており、このp型半導体領域PRcとn型半導体領域NRsの両方と電気的に接続するようにプラグPLG2が形成されている。さらに、離間されて配置されているn型半導体領域NRsと半導体領域NRbの間をY方向に延在するようにゲート電極Gが形成されている。そして、ゲート電極Gの一端部でゲート電極GはプラグPLG3と電気的に接続されている。
本願発明における半導体素子は、MOSFETとトンネルバイポーラトランジスタを組み合わせることにより、60mV/桁以下のS値を実現することができ、この結果、低電圧においても優れたスイッチング特性を有するデバイスである。つまり、本願発明における半導体素子は、低電圧での動作で特に有効であるという第1特徴点を有している。一方、本願発明における半導体素子は上述した第1特徴点とは別の有効な第2特徴点も有している。この第2特徴点について説明する。
本実施の形態6では、本願発明の技術的思想を不揮発性半導体記憶装置に適用する例について説明する。図51は本実施の形態6におけるメモリセルのデバイス構造を示す断面図である。図51に示すように、本実施の形態6におけるメモリセルは、半導体基板1Sに形成された素子分離領域STIで区画されたアクティブ領域に形成されている。具体的に、素子分離領域STIで区画された半導体基板1S内には、例えば、ボロンなどのp型不純物を導入したp型ウェルPWLが形成されており、このp型ウェルPWL内に離間して一対の低濃度n型半導体領域EX1が形成されている。低濃度n型半導体領域EX1は、リンなどのn型不純物を導入した半導体領域であり、一対の低濃度n型半導体領域EX1で挟まれたp型ウェルPWL内の領域がチャネル領域となる。そして、低濃度n型半導体領域EX1の外側にはn型半導体領域NRsとn型半導体領域NRbが形成されている。すなわち、一対の低濃度n型半導体領域EX1のうち左側の低濃度n型半導体領域EX1のさらに左側にn型半導体領域NRsが形成され、一対の低濃度n型半導体領域EX1のうち右側の低濃度n型半導体領域EX1のさらに右側にn型半導体領域NRbが形成されている。このn型半導体領域NRsおよびn型半導体領域NRbは、砒素などのn型不純物が導入された半導体領域である。
A ノード
BD ボディ領域
BOX 埋め込み絶縁層
CIL コンタクト層間絶縁膜
CNT コンタクトホール
CNT1 コンタクトホール
CNT2 コンタクトホール
D ドレイン端子
EB1 第1電位障壁膜
EB2 第2電位障壁膜
EC 電荷蓄積膜
Ec 伝導帯
Ef フェルミ準位
Ev 価電子帯
EX1 低濃度n型半導体領域
EX2 低濃度p型半導体領域
EX3 低濃度n型半導体領域
G ゲート電極
G1 ゲート電極
G2 ゲート電極
GND グランド電位
GOX ゲート絶縁膜
GT ゲート端子
HS 支持基板
HVU 高電圧動作部
IN 入力
IOU I/O回路部
L1 配線
LVU 低電圧動作部
NRb n型半導体領域
NRb2 n型半導体領域
NRd n型半導体領域
NRs n型半導体領域
NRs2 n型半導体領域
NR1 n型給電領域
NTr nチャネル型半導体素子
NTr1 nチャネル型半導体素子
NTr2 単体トランジスタ
NWL n型ウェル
OUT 出力
PCU 電源回路部
PF1 ポリシリコン膜
PLG プラグ
PLG1 プラグ
PLG2 プラグ
PLG3 プラグ
PRb p型半導体領域
PRc p型半導体領域
PRc2 p型半導体領域
PRd p型半導体領域
PRs p型半導体領域
PR1 p型給電領域
PR2 p型給電領域
PTr pチャネル型半導体素子
PTr1 pチャネル型半導体素子
PWL p型ウェル
PWL1 p型ウェル
PWL2 p型ウェル
S ソース端子
SL シリサイド膜
STI 素子分離領域
Sub 基板端子
SW1 サイドウォール
SW2 サイドウォール
VD ドレイン電位
VDD 電源電位
VG ゲート電位
Vs ソース電位
Vsub 基板電位
Claims (25)
- 半導体基板に形成された第1電界効果トランジスタとバイポーラトランジスタから構成される半導体素子を備え、
前記半導体素子を構成する前記第1電界効果トランジスタは、
(a)前記半導体基板内に設けられた第1ソース領域となる第1導電型の第1半導体領域と、
(b)前記半導体基板内で前記第1半導体領域と離間して設けられた第1ドレイン領域となる前記第1導電型の第2半導体領域と、
(c)前記第1半導体領域と前記第2半導体領域の間の前記半導体基板内に形成された前記第1導電型とは逆導電型である第2導電型の第1チャネル領域と、
(d)前記第1チャネル領域上に形成された第1ゲート絶縁膜と、
(e)前記第1ゲート絶縁膜上に形成された第1ゲート電極とを有し、
前記半導体素子を構成する前記バイポーラトランジスタは、
(f)前記第2半導体領域に内包されるように形成されたエミッタ領域となる前記第2導電型の第3半導体領域と、
(g)ベース領域となる前記第1導電型の前記第2半導体領域と、
(h)コレクタ領域となる前記第2導電型の前記半導体基板とを有する半導体装置であって、
前記第2半導体領域と前記第3半導体領域の境界領域にトンネル接合が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記トンネル接合とは、順方向に所定電圧以下の順バイアスを印加した場合にも、電流が流れないのではなく、バンド間トンネリングに起因した電流が流れ、かつ、逆バイアスを印加した時に一定の電流抑制機能を有する接合であることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記第3半導体領域の不純物濃度は前記第2半導体領域の不純物濃度よりも高いことを特徴とする半導体装置。 - 請求項3記載の半導体装置であって、
前記第3半導体領域の不純物濃度は、1020/cm3のオーダーであり、
前記第2半導体領域の不純物濃度は、1019/cm3のオーダーであることを特徴とする半導体装置。 - 支持基板と、前記支持基板上に形成された埋め込み絶縁層と、前記埋め込み絶縁層上に形成された活性層よりなるSOI基板に形成された第1電界効果トランジスタとバイポーラトランジスタから構成される半導体素子を備え、
前記半導体素子を構成する前記電界効果トランジスタは、
(a)前記活性層内に設けられた第1ソース領域となる第1導電型の第1半導体領域と、
(b)前記活性層内で前記第1半導体領域と離間して設けられた第1ドレイン領域となる前記第1導電型の第2半導体領域と、
(c)前記第1半導体領域と前記第2半導体領域の間の前記活性層内に形成された第1チャネル領域となる前記第1導電型とは逆導電型である第2導電型の第1ボディ領域と、
(d)前記第1ボディ領域上に形成された第1ゲート絶縁膜と、
(e)前記第1ゲート絶縁膜上に形成された第1ゲート電極とを有し、
前記半導体素子を構成する前記バイポーラトランジスタは、
(f)前記第2半導体領域に内包されるように形成されたエミッタ領域となる前記第2導電型の第3半導体領域と、
(g)ベース領域となる前記第1導電型の前記第2半導体領域と、
(h)コレクタ領域となる前記第2導電型の前記ボディ領域とを有する半導体装置であって、
前記第2半導体領域と前記第3半導体領域の境界領域にトンネル接合が形成されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記トンネル接合とは、順方向に所定電圧以下の順バイアスを印加した場合にも、電流が流れないのではなく、バンド間トンネリングに起因した電流が流れ、かつ、逆バイアスを印加した時に一定の電流抑制機能を有する接合であることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記第3半導体領域の不純物濃度は前記第2半導体領域の不純物濃度よりも高いことを特徴とする半導体装置。 - 請求項7記載の半導体装置であって、
前記第3半導体領域の不純物濃度は、1020/cm3のオーダーであり、
前記第2半導体領域の不純物濃度は、1019/cm3のオーダーであることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記第1半導体領域は、前記埋め込み絶縁層まで達しておらず、かつ、前記第1半導体領域の前記第2半導体領域側とは反対側に前記埋め込み絶縁層まで達する前記第2導電型の第4半導体領域が形成されており、
前記第4半導体領域と前記第1ボディ領域とは電気的に接続されていることを特徴とする半導体装置。 - 請求項9記載の半導体装置であって、
前記第1半導体領域と前記第4半導体領域の両方に接するように、前記第1半導体領域および前記第4半導体領域上にプラグが形成されており、
前記プラグを介して前記第1半導体領域と前記第1ボディ領域に同じ電位が印加されることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記第1半導体領域は、前記埋め込み絶縁層まで達しておらず、かつ、前記第1半導体領域と前記埋め込み絶縁層の間に前記第2導電型の第5半導体領域が形成されており、
前記第1半導体領域と前記第5半導体領域とはオーミック接触していることを特徴とする半導体装置。 - 請求項11記載の半導体装置であって、
前記オーミック接触とは、整流作用がなく、かつ、電流・電圧特性が抵抗性を示す接触であることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体装置は、複数の前記半導体素子を有し、
複数の前記半導体素子は、第1半導体素子と第2半導体素子を含み、
前記第1半導体素子は、前記第1導電型がN型であり、かつ、前記第2導電型がP型である前記半導体素子であり、
前記第2半導体素子は、前記第1導電型がP型であり、かつ、前記第2導電型がN型である前記半導体素子であることを特徴とする半導体装置。 - 請求項13記載の半導体装置であって、
前記第1半導体素子と前記第2半導体素子がインバータを構成していることを特徴とする半導体装置。 - 請求項14記載の半導体装置であって、
前記インバータは、SRAMのメモリセルに使用されることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体装置は、複数の前記半導体素子を有し、
複数の前記半導体素子の中には、低電圧で動作する低電圧半導体素子と、前記低電圧より高い高電圧で動作する高電圧半導体素子が含まれていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体装置は、前記半導体素子とは別の第2電界効果トランジスタを有し、
前記第2電界効果トランジスタは、
(i)前記半導体基板内に設けられた第2ソース領域と、
(j)前記半導体基板内で前記第2ソース領域と離間して設けられた第2ドレイン領域と、
(k)前記第2ソース領域と前記第2ドレイン領域の間の前記半導体基板内に形成された第2チャネル領域と、
(l)前記第2チャネル領域上に形成された第2ゲート絶縁膜と、
(m)前記第2ゲート絶縁膜上に形成された第2ゲート電極とを有することを特徴とする半導体装置。 - 半導体基板に形成されたメモリトランジスタとバイポーラトランジスタから構成されるメモリセルを備え、
前記メモリセルを構成する前記メモリトランジスタは、
(a)前記半導体基板内に設けられたソース領域となる第1導電型の第1半導体領域と、
(b)前記半導体基板内で前記第1半導体領域と離間して設けられたドレイン領域となる前記第1導電型の第2半導体領域と、
(c)前記第1半導体領域と前記第2半導体領域の間の前記半導体基板内に形成された前記第1導電型とは逆導電型である第2導電型のチャネル領域と、
(d)前記チャネル領域上に形成された第1電位障壁膜と、
(e)前記第1電位障壁膜上に形成された電荷蓄積膜と、
(f)前記電荷蓄積膜上に形成された第2電位障壁膜と、
(g)前記第2電位障壁膜上に形成されたゲート電極とを有し、
前記メモリセルを構成する前記バイポーラトランジスタは、
(h)前記第2半導体領域に内包されるように形成されたエミッタ領域となる前記第2導電型の第3半導体領域と、
(i)ベース領域となる前記第1導電型の前記第2半導体領域と、
(j)コレクタ領域となる前記第2導電型の前記半導体基板とを有する不揮発性半導体記憶装置であって、
前記第2半導体領域と前記第3半導体領域の境界領域にトンネル接合が形成されていることを特徴とする不揮発性半導体記憶装置。 - 請求項18記載の不揮発性半導体記憶装置であって、
前記トンネル接合とは、順方向に所定電圧以下の順バイアスを印加した場合にも、電流が流れないのではなく、バンド間トンネリングに起因した電流が流れ、かつ、逆バイアスを印加した時に一定の電流抑制機能を有する接合であることを特徴とする不揮発性半導体記憶装置。 - 請求項19記載の不揮発性半導体記憶装置であって、
前記第3半導体領域の不純物濃度は前記第2半導体領域の不純物濃度よりも高いことを特徴とする不揮発性半導体記憶装置。 - 請求項20記載の不揮発性半導体記憶装置であって、
前記第3半導体領域の不純物濃度は、1020/cm3のオーダーであり、
前記第2半導体領域の不純物濃度は、1019/cm3のオーダーであることを特徴とする不揮発性半導体記憶装置。 - 請求項18記載の不揮発性半導体記憶装置であって、
前記電荷蓄積膜は、導体膜から形成されていることを特徴とする不揮発性半導体記憶装置。 - 請求項18記載の不揮発性半導体記憶装置であって、
前記電荷蓄積膜は、トラップ準位を有する絶縁膜から形成されていることを特徴とする不揮発性半導体記憶装置。 - (a)前記半導体基板を用意する工程と、
(b)前記半導体基板上にゲート絶縁膜を形成する工程と、
(c)前記ゲート絶縁膜上にゲート電極を形成する工程と、
(d)前記(c)工程後、前記半導体基板内に第1導電型不純物を導入することにより、第1導電型の第1半導体領域および前記第1導電型の第2半導体領域を互いに離間して形成する工程と、
(e)前記(d)工程後、前記半導体基板内に第2導電型不純物を導入することにより、前記第2半導体領域に内包されるように、第1導電型とは逆導電型の第2導電型の第3半導体領域を形成する工程と、
(f)前記(e)工程後、前記第1半導体領域および前記第2半導体領域に導入した前記第1導電型不純物と、前記第3半導体領域に導入した前記第2導電型不純物を活性化するための熱処理を実施する工程とを備え、
前記(d)工程で前記第1半導体領域および前記第2半導体領域に導入する前記第1導電型不純物の濃度、前記(e)工程で前記第3半導体領域に導入する前記第2導電型不純物の濃度、および、前記(f)工程で実施する熱処理を調整することにより、前記第2半導体領域と前記第3半導体領域の境界領域にトンネル接合を形成することを特徴とする半導体装置の製造方法。 - 請求項24記載の半導体装置の製造方法であって、
前記(f)工程で実施する熱処理は、レーザ・スパイク・アニールであることを特徴とする半導体装置の製造方法。
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