JP2011518402A - 負バイアス温度不安定性によるバーンインの発生を低減する方法 - Google Patents
負バイアス温度不安定性によるバーンインの発生を低減する方法 Download PDFInfo
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- JP2011518402A JP2011518402A JP2011504599A JP2011504599A JP2011518402A JP 2011518402 A JP2011518402 A JP 2011518402A JP 2011504599 A JP2011504599 A JP 2011504599A JP 2011504599 A JP2011504599 A JP 2011504599A JP 2011518402 A JP2011518402 A JP 2011518402A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
Abstract
Description
Claims (8)
- 複数の問題とする記憶素子を含むデバイスに関してバーンイン効果を軽減し、かつ始動工程を行うことができるようにする方法であって、応答パターンが記憶素子の物理的特性に依存するので、記憶素子が、始動時に、同定に有用な始動値の応答パターンを生成することができ、方法が、記憶素子の始動後に、前に同じ記憶素子から読み出された応答パターンの反転であるデータパターンを記憶素子に書き込むステップを含む方法。
- 始動工程ごとに、書き込まれるデータパターンが、その個々の始動工程の結果として生成される応答パターンの反転である、請求項1に記載の方法。
- 書き込まれるデータパターンが固定されており、登録フェーズの間に生成される応答パターンの反転である、請求項1に記載の方法。
- 登録フェーズの間に決定される応答が、不揮発性メモリ内に記憶され、不揮発性メモリが、デバイス自体の中に組み込まれることがある、請求項3に記載の方法。
- 前記応答が、保護された形式で記憶される、請求項3に記載の方法。
- 請求項1に記載の方法を実装するように配置される、電子デバイス。
- プロセッサ上にロードされ、プロセッサ上で実行されるときに、請求項1に記載の方法を実装するように配置される、プロセッサ実行可能な命令群を含む、コンピュータプログラム製品。
- 構成可能電子回路にロードされたときに、電子回路を請求項1に記載の方法を実行するように配置されるように構成する、好ましくはビットストリームの形式で構成データを含む、コンピュータプログラム製品。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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EP08154744.0 | 2008-04-17 | ||
EP08154744 | 2008-04-17 | ||
PCT/IB2009/051592 WO2009128044A1 (en) | 2008-04-17 | 2009-04-16 | Method of reducing the occurrence of burn-in due to negative bias temperature instability |
Publications (2)
Publication Number | Publication Date |
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JP2011518402A true JP2011518402A (ja) | 2011-06-23 |
JP5586582B2 JP5586582B2 (ja) | 2014-09-10 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2011504599A Active JP5586582B2 (ja) | 2008-04-17 | 2009-04-16 | 負バイアス温度不安定性によるバーンインの発生を低減する方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US8339875B2 (ja) |
EP (1) | EP2269133B1 (ja) |
JP (1) | JP5586582B2 (ja) |
KR (1) | KR101690196B1 (ja) |
CN (1) | CN101981540B (ja) |
ES (1) | ES2584527T3 (ja) |
IL (1) | IL207712A (ja) |
WO (1) | WO2009128044A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012160249A (ja) * | 2011-01-28 | 2012-08-23 | Freescale Semiconductor Inc | 負バイアス温度不安定性に耐性のあるラッチングセンスアンプを有するメモリおよび関連する方法 |
JP2015504634A (ja) * | 2011-11-22 | 2015-02-12 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | ファジー・アルゴリズムおよび動的キーを特徴とする保持ベースの固有指紋識別 |
Families Citing this family (12)
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DE102010024622B4 (de) * | 2010-06-22 | 2012-12-13 | Infineon Technologies Ag | Identifikationsschaltung und Verfahren zum Erzeugen eines Identifikationsbits |
FR2964278A1 (fr) * | 2010-08-31 | 2012-03-02 | St Microelectronics Rousset | Extraction de cle dans un circuit integre |
US8848477B2 (en) | 2010-10-04 | 2014-09-30 | Intrinsic Id B.V. | Physical unclonable function with improved start-up behavior |
US20130141137A1 (en) * | 2011-06-01 | 2013-06-06 | ISC8 Inc. | Stacked Physically Uncloneable Function Sense and Respond Module |
US20130155795A1 (en) * | 2011-12-19 | 2013-06-20 | Mayank Gupta | Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory |
US9093128B2 (en) * | 2012-11-05 | 2015-07-28 | Infineon Technologies Ag | Electronic device with a plurality of memory cells and with physically unclonable function |
US20150063010A1 (en) * | 2013-08-27 | 2015-03-05 | Synopsys, Inc. | Negative bias thermal instability stress testing for static random access memory (sram) |
US9729317B2 (en) * | 2014-01-30 | 2017-08-08 | Mentor Graphics Corporation | Optical physical uncloneable function |
US9202554B2 (en) | 2014-03-13 | 2015-12-01 | International Business Machines Corporation | Methods and circuits for generating physically unclonable function |
US10142335B2 (en) | 2015-12-18 | 2018-11-27 | International Business Machines Corporation | Dynamic intrinsic chip identification |
US10146464B2 (en) | 2016-06-30 | 2018-12-04 | Nxp B.V. | Method for performing multiple enrollments of a physically uncloneable function |
US11343108B2 (en) * | 2019-06-12 | 2022-05-24 | Arizona Board Of Regents On Behalf Of Northern Arizona University | Generation of composite private keys |
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- 2009-04-16 WO PCT/IB2009/051592 patent/WO2009128044A1/en active Application Filing
- 2009-04-16 CN CN200980109768.XA patent/CN101981540B/zh active Active
- 2009-04-16 US US12/921,901 patent/US8339875B2/en active Active
- 2009-04-16 KR KR1020107022994A patent/KR101690196B1/ko active IP Right Grant
- 2009-04-16 ES ES09732238.2T patent/ES2584527T3/es active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012160249A (ja) * | 2011-01-28 | 2012-08-23 | Freescale Semiconductor Inc | 負バイアス温度不安定性に耐性のあるラッチングセンスアンプを有するメモリおよび関連する方法 |
JP2015504634A (ja) * | 2011-11-22 | 2015-02-12 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | ファジー・アルゴリズムおよび動的キーを特徴とする保持ベースの固有指紋識別 |
Also Published As
Publication number | Publication date |
---|---|
CN101981540B (zh) | 2013-03-20 |
IL207712A (en) | 2017-06-29 |
ES2584527T3 (es) | 2016-09-28 |
EP2269133B1 (en) | 2016-05-11 |
EP2269133A1 (en) | 2011-01-05 |
US8339875B2 (en) | 2012-12-25 |
KR101690196B1 (ko) | 2016-12-27 |
JP5586582B2 (ja) | 2014-09-10 |
IL207712A0 (en) | 2010-12-30 |
CN101981540A (zh) | 2011-02-23 |
KR20100135258A (ko) | 2010-12-24 |
US20110103161A1 (en) | 2011-05-05 |
WO2009128044A1 (en) | 2009-10-22 |
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