JP2011515871A - 引張り歪み及び/又は圧縮歪みを有する半導体デバイス並びに製造方法及び設計構造体 - Google Patents
引張り歪み及び/又は圧縮歪みを有する半導体デバイス並びに製造方法及び設計構造体 Download PDFInfo
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Abstract
【解決手段】 引張り歪み及び/又は圧縮歪みが加えられた半導体デバイス、及びその半導体デバイスを製造する方法、及びチャネルの歪みを増大させるための設計構造体を提供する。本方法は、NFET及びPFETのゲート構造体を形成するステップと、NFET及びPFETのゲート構造体上の側壁を、同じ堆積及びエッチング・プロセスを用いて形成するステップとを含む。本方法はまた、NFET及びPFETのソース及びドレイン領域内に応力材料を供給するステップを含む。
【選択図】 図7
Description
12:浅いトレンチ分離(STI)構造体
14:ゲート誘電体材料
16:ゲート材料
18:キャップ材料
20:スペーサ(側壁)
22、28、28a:凹部
24、30:応力材料
26:マスク(マスキング層)
900:設計フロー
910:設計プロセス
920、990:設計構造体
930:ライブラリ要素
940:設計仕様
950:特性評価データ
960:検証データ
970:設計ルール
980:ネットリスト
985:試験データ・ファイル
995:ステージ
Claims (25)
- 半導体構造体を形成する方法であって、
NFET及びPFETのゲート構造体(14、16,18)を形成するステップと、
前記NFET及び前記PFETの前記ゲート構造体上の側壁(20)を、同じ堆積及びエッチング・プロセスを用いて形成するステップと、
前記NFET及び前記PFETのソース及びドレイン領域内に応力材料(24、30)を供給するステップと
を含む方法。 - 前記NFET及び前記PFETの前記ソース及びドレイン領域内に、単一のマスキング・プロセスで凹部(22)を形成するステップをさらに含む、請求項1に記載の方法。
- 前記応力材料(24、30)は前記凹部(22)内で成長させる、請求項2に記載の方法。
- 前記凹部(22)はエッチング・プロセスによって形成される、請求項2に記載の方法。
- 前記NFET及び前記PFETのうちの一方の前記凹部(22)を付加的にエッチングして、前記NFET及び前記PFETのうちの一方の前記凹部を、前記NFET及び前記PFETのうちの他方の前記凹部よりも深くするステップをさらに含む、請求項4に記載の方法。
- 前記凹部(22)を単一種類の応力材料(24)で充填するステップと、
前記NFET及び前記PFETのうちの一方をブロックするステップと、
前記NFET及び前記PFETのうちのブロックされない方の前記単一種類の応力材料(24)をエッチング除去して、凹部(28)を再形成するステップと、
前記再形成された凹部(28)内を異なる種類の応力材料(30)で充填するステップと
をさらに含む、請求項2に記載の方法。 - 前記単一種類の応力材料(24)はeSiGeであり、
前記異なる種類の応力材料(30)はeSi:Cであり、
前記応力材料をエッチング除去するステップは、前記NFETに対して実行される、
請求項6に記載の方法。 - 前記単一種類の応力材料(24)はeSi:Cであり、
前記異なる種類の応力材料(30)はeSiGeであり、
前記応力材料をエッチング除去するステップは、前記PFETに対して実行される、
請求項6に記載の方法。 - 前記再形成された凹部(28)は、前記凹部(22)よりも深くエッチングされる、請求項6に記載の方法。
- 前記応力材料(24、30)は、PFETに対してeSiGeでありNFETに対してeSi:Cであり、前記凹部(22、28)内の所定の深さまで成長させる、請求項1に記載の方法。
- デバイス性能を高める方法であって、
NFET及びPFETのゲート構造体(14、16,18)を形成するステップと、
前記NFET及び前記PFETの前記ゲート構造体上の側壁(20)を、同じ堆積及びエッチング・プロセスを用いて形成するステップと、
前記NFET及び前記PFETのソース及びドレイン領域内に凹部(22、28)を形成するステップと、
前記PFETの前記ソース及びドレイン領域の前記凹部(22)を第1の種類の応力材料(24)で充填し、前記NFETの前記ソース及びドレイン領域の前記凹部(28)を第2の種類の応力材料(30)で充填するステップと
を含む方法。 - 前記NFET及び前記PFETの前記ソース及びドレイン領域内に前記凹部(22)を、単一のマスキング・プロセスで形成するステップをさらに含む、請求項11に記載の方法。
- 前記第1の種類の応力材料(24)及び前記第2の種類の応力材料(30)は、別々の処理ステップにより前記凹部(22、28)内で成長させる、請求項11に記載の方法。
- 前記第2の種類の応力材料(30)は、前記第1の種類の応力材料(24)よりも深い、請求項13に記載の方法。
- 前記NFETの前記凹部(28)を、前記第2の種類の応力材料(30)で充填する前に、前記第1の種類の応力材料(24)で充填するステップと、
前記PFETをブロックするステップと、
前記NFETの前記ソース及びドレイン領域内の前記第1の種類の応力材料(24)をエッチング除去するステップと、
前記NFETの前記ソース及びドレイン領域内を前記第2の種類の応力材料(30)で充填するステップと
をさらに含む、請求項11に記載の方法。 - 前記第1の種類の応力材料(24)及び前記第2の種類の応力材料(30)は、それぞれ、eSiGe及びeSi:Cである、請求項11に記載の方法。
- 前記NFET及び前記PFETのうちの一方の前記ソース及びドレイン領域の前記凹部(22、28)を付加的にエッチングして、前記NFET及び前記PFETのうちの一方の前記凹部を、前記NFET及び前記PFETのうちの他方の前記凹部よりも深くするステップをさらに含む、請求項11に記載の方法。
- デバイス性能を高める方法であって、
誘電体材料(14)、ゲート材料(16)及びキャップ材料(18)をパターン化することによって、NFET及びPFETのゲート構造体を形成するステップと、
前記NFET及び前記PFETの前記ゲート構造体上の側壁(20)を、同じ堆積及びエッチング・プロセスを用いて形成するステップと、
前記NFET及び前記PFETのソース及びドレイン領域内に凹部(22)を形成するステップと、
前記凹部(22)を第1の種類の応力材料(24)で充填するステップと、
前記NFET及び前記PFETのうちの一方を保護するステップと、
前記NFET及び前記PFETのうちのブロックされない方の中の前記第1の種類の応力材料(24)をエッチング除去して、凹部(28)を再形成するステップと、
前記再形成された凹部(28)を、前記第1の種類の応力材料(24)とは異なる第2の応力材料(30)で充填するステップと
を含む方法。 - 前記再形成された凹部(28)は、前記凹部(22)よりも深い位置にある、請求項18に記載の方法。
- 前記側壁(20)は窒化物の側壁である、請求項18に記載の方法。
- 前記第1の種類の応力材料(24)はeSiGeであり、前記第2の種類の応力材料(30)はeSi:Cである、請求項18に記載の方法。
- 集積回路を設計、製造又は検査するための、機械可読媒体内で具体化された設計構造体であって、
NFET及びPFETのゲート構造体(14、16、18)を形成することと、
前記NFET及び前記PFETの前記ゲート構造体上の側壁(20)を、同じ堆積及びエッチング・プロセスを用いて形成することと、
前記NFET及び前記PFETのソース及びドレイン領域内に応力材料(24、30)を供給することと
を含む設計構造体。 - 前記設計構造体(990)は、集積回路のレイアウト・データの交換のために用いられるデータ形式で記憶媒体上に常駐する、請求項22に記載の設計構造体。
- 完全に同じに形成された側壁(20)を有する、NFET及びPFETのゲート構造体(14、16、18)と、
前記NFET及び前記PFETのソース及びドレイン領域内の凹部(22、28)内の応力材料(24、30)と
を含む構造体。 - 前記NFET用の前記応力材料(30)はeSi:Cであり、前記PFET用の前記応力材料(24)はeSiGeであり、前記NFET用の前記応力材料(30)は、前記PFET用の前記応力材料(24)よりも深い位置にある、請求項24に記載の構造体。
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PCT/US2009/037910 WO2009120612A2 (en) | 2008-03-25 | 2009-03-23 | Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure |
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US7892932B2 (en) | 2011-02-22 |
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