JP2011503871A - メサ構造とメサ段差を含むバッファ層とを備えた電力半導体デバイス - Google Patents
メサ構造とメサ段差を含むバッファ層とを備えた電力半導体デバイス Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 22
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 description 19
- 238000006731 degradation reaction Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 11
- 230000005684 electric field Effects 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000005527 interface trap Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
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Abstract
Description
本出願は、2007年11月9日出願の「SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR」という名称の米国特許仮出願第60/986,694号明細書の利益および優先権を主張する。同出願の開示は、参照によりその全体を本明細書に組み込む。
本発明は、Army Research Laboratoryにより授与された契約番号W911NF−04−2−0022のもとに政府の支援でなされた。政府は本発明に一定の権利を有する。
Claims (15)
- 第1の導電型を有するコレクタと、
前記コレクタ上の、前記第1の導電型を有するドリフト層と、
前記ドリフト層上の、前記第1の導電型と反対の第2の導電型を有するベース層と、
前記ベース層上の、前記第1の導電型を有し前記ベース層とp−n接合部を形成するバッファ層であって、前記ベース層のドーピング濃度よりも低いドーピング濃度を有するバッファ層と、
前記バッファ層上の、前記第1の導電型を有し側壁を有するエミッタメサと
を備え、
前記バッファ層は、前記エミッタメサの側壁の近傍でそこから横方向に間隔を置いて配置されたメサ段差を備え、前記エミッタメサの下の前記バッファ層の第1の厚さは、前記メサ段差外側の前記バッファ層の第2の厚さよりも厚いことを特徴とするバイポーラ接合トランジスタ。 - 前記エミッタメサ上の局所エミッタコンタクト領域であって、第1の導電型を有し、前記エミッタメサのドーピング濃度よりも高いドーピング濃度を有し、前記エミッタメサの側壁から横方向に間隔を置いて配置されたエミッタコンタクト領域と、
前記局所エミッタコンタクト領域上のエミッタオーミックコンタクトと
をさらに備えることを特徴とする請求項1に記載のバイポーラ接合トランジスタ。 - 前記局所エミッタコンタクト領域は、前記エミッタメサの側壁から約2μm以上の間隔で配置されることを特徴とする請求項2に記載のバイポーラ接合トランジスタ。
- 前記エミッタメサの側壁上の、前記局所エミッタコンタクト領域と前記バッファ層の両方に接触するように延びる導電層をさらに備え、前記エミッタオーミックコンタクトは、前記導電層とオーミックコンタクトを形成することを特徴とする請求項2に記載のバイポーラ接合トランジスタ。
- 前記ベース層の中に延びるベースコンタクト領域であって、第2の導電型を有し、前記ベース層のドーピング濃度よりも高いドーピング濃度を有するベースコンタクト領域と、
前記ベースコンタクト領域上のベースオーミックコンタクトと
をさらに備えることを特徴とする請求項3に記載のバイポーラ接合トランジスタ。 - 前記ベース層の中に延びるベースコンタクト領域であって、第2の導電型を有し、かつ前記ベース層のドーピング濃度よりも高いドーピング濃度を有するベースコンタクト領域と、
前記ベースコンタクト領域上のベースオーミックコンタクトと
をさらに備えることを特徴とする請求項1に記載のバイポーラ接合トランジスタ。 - 前記メサ段差は、約0.3μm以下の高さを有することを特徴とする請求項1に記載のバイポーラ接合トランジスタ。
- 前記メサ段差は、前記エミッタメサの側壁から約2μm以上の間隔で配置されることを特徴とする請求項1に記載のバイポーラ接合トランジスタ。
- 前記バッファ層は、前記ベース層のドーピング濃度よりも低いドーピング濃度を有することを特徴とする請求項1に記載のバイポーラ接合トランジスタ。
- 前記バッファ層は、前記バッファ層と前記ベース層の間のp−n接合部のビルトイン電位によって前記バッファ層の、前記第2の厚さを有する部分が完全に空乏化されるように選択されたドーピング濃度を有することを特徴とする請求項1に記載のバイポーラ接合トランジスタ。
- 前記コレクタ、前記ドリフト層、前記ベース層、前記バッファ層および前記エミッタメサは炭化ケイ素を含むことを特徴とする請求項1に記載のバイポーラ接合トランジスタ。
- 第1の導電型を有する第1の層と、
前記第1の層上の第2の層であって、前記第1の導電型と反対の第2の導電型を有し、前記第1の層の第1のドーピング濃度よりも高い第2のドーピング濃度を有する第2の層と、
前記第2の層上の、前記第1の導電型を有し前記第2の層とp−n接合部を形成する第3の層であって、前記第2の層の前記第2のドーピング濃度よりも低い第3のドーピング濃度を有する第3の層と、
前記第3の層上の、前記第1の導電型を有し側壁を有するメサと
を備え、
前記第3の層は、前記メサの側壁の近傍でそこから横方向に間隔を置いて配置されたメサ段差を備え、前記メサの下の前記第3の層の第1の厚さは、前記メサ段差外側の前記第3の層の第2の厚さよりも厚いことを特徴とする電力半導体デバイス。 - 前記メサ上のコンタクト領域であって、第1の導電型を有し、前記メサの第5のドーピング濃度よりも高い第4のドーピング濃度を有し、前記メサの側壁から横方向に間隔を置いて配置されたコンタクト領域と、
前記コンタクト領域上のオーミックコンタクトと
をさらに備えることを特徴とする請求項12に記載の電力半導体デバイス。 - 前記メサの側壁上の、前記コンタクト領域と前記第3の層の両方に接触するように延びる導電層をさらに備え、前記オーミックコンタクトは、前記導電層とオーミックコンタクトを形成することを特徴とする請求項13に記載の電力半導体デバイス。
- 電子デバイスを形成する方法であって、
第1の導電型を有するドリフト層を設けるステップと、
前記ドリフト層上に、前記第1の導電型と反対の第2の導電型を有する半導体層を設けるステップと、
前記半導体層上に、前記第1の導電型を有するバッファ層を設けるステップと、
前記バッファ層を選択的にエッチングして、前記バッファ層の、第1の厚さを有する第1の部分、および前記バッファ層の、前記第1の厚さよりも薄い第2の厚さを有する第2の部分を画定するメサ段差を形成するステップと、
前記バッファ層の前記第1の部分上にメサを設けるステップであって、前記メサは、前記第1の導電型を有するとともに、前記バッファ層の前記第1の部分を部分的に露出し前記バッファ層の前記メサ段差から横方向に間隔を置いて配置されたメサ側壁を有する、ステップと
を含む電子デバイスを形成する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US98669407P | 2007-11-09 | 2007-11-09 | |
US60/986,694 | 2007-11-09 | ||
PCT/US2008/010538 WO2009061340A1 (en) | 2007-11-09 | 2008-09-08 | Power semiconductor devices with mesa structures and buffer layers including mesa steps |
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JP2011503871A true JP2011503871A (ja) | 2011-01-27 |
JP2011503871A5 JP2011503871A5 (ja) | 2012-07-12 |
JP5372002B2 JP5372002B2 (ja) | 2013-12-18 |
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JP2010533058A Active JP5372002B2 (ja) | 2007-11-09 | 2008-09-08 | メサ構造とメサ段差を含むバッファ層とを備えた電力半導体デバイス |
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US (1) | US7838377B2 (ja) |
EP (1) | EP2208230B1 (ja) |
JP (1) | JP5372002B2 (ja) |
KR (1) | KR101494935B1 (ja) |
CN (1) | CN101855726B (ja) |
WO (1) | WO2009061340A1 (ja) |
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US7838377B2 (en) | 2010-11-23 |
WO2009061340A1 (en) | 2009-05-14 |
JP5372002B2 (ja) | 2013-12-18 |
US20090121319A1 (en) | 2009-05-14 |
EP2208230A1 (en) | 2010-07-21 |
KR20100085971A (ko) | 2010-07-29 |
EP2208230B1 (en) | 2015-10-21 |
CN101855726B (zh) | 2015-09-16 |
KR101494935B1 (ko) | 2015-02-23 |
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