JP2011130405A5 - - Google Patents

Download PDF

Info

Publication number
JP2011130405A5
JP2011130405A5 JP2010111048A JP2010111048A JP2011130405A5 JP 2011130405 A5 JP2011130405 A5 JP 2011130405A5 JP 2010111048 A JP2010111048 A JP 2010111048A JP 2010111048 A JP2010111048 A JP 2010111048A JP 2011130405 A5 JP2011130405 A5 JP 2011130405A5
Authority
JP
Japan
Prior art keywords
reset flip
type
flops
gate
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010111048A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011130405A (ja
JP5462703B2 (ja
Filing date
Publication date
Priority claimed from US12/640,004 external-priority patent/US8736332B2/en
Application filed filed Critical
Publication of JP2011130405A publication Critical patent/JP2011130405A/ja
Publication of JP2011130405A5 publication Critical patent/JP2011130405A5/ja
Application granted granted Critical
Publication of JP5462703B2 publication Critical patent/JP5462703B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2010111048A 2009-12-17 2010-05-13 順序回路におけるリーク電流の低減システム Expired - Fee Related JP5462703B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/640,004 2009-12-17
US12/640,004 US8736332B2 (en) 2009-12-17 2009-12-17 Leakage current reduction in a sequential circuit

Publications (3)

Publication Number Publication Date
JP2011130405A JP2011130405A (ja) 2011-06-30
JP2011130405A5 true JP2011130405A5 (https=) 2013-06-27
JP5462703B2 JP5462703B2 (ja) 2014-04-02

Family

ID=42514259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010111048A Expired - Fee Related JP5462703B2 (ja) 2009-12-17 2010-05-13 順序回路におけるリーク電流の低減システム

Country Status (6)

Country Link
US (1) US8736332B2 (https=)
EP (1) EP2339752B1 (https=)
JP (1) JP5462703B2 (https=)
KR (1) KR20110069664A (https=)
CN (1) CN101777908A (https=)
TW (1) TW201123731A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8307226B1 (en) * 2011-12-20 2012-11-06 Intel Corporation Method, apparatus, and system for reducing leakage power consumption
US9100002B2 (en) 2013-09-12 2015-08-04 Micron Technology, Inc. Apparatus and methods for leakage current reduction in integrated circuits
US9496851B2 (en) * 2014-09-10 2016-11-15 Qualcomm Incorporated Systems and methods for setting logic to a desired leakage state
CN105720966B (zh) * 2014-12-18 2020-12-11 马维尔亚洲私人有限公司 具有备用电路单元的集成电路
KR101971472B1 (ko) * 2014-12-26 2019-08-13 전자부품연구원 저전력 구현을 위한 순차회로 설계방법
US9503086B1 (en) * 2015-09-16 2016-11-22 Apple Inc. Lockup latch for subthreshold operation
CN105515565B (zh) * 2015-12-14 2018-07-13 天津光电通信技术有限公司 一种硬件逻辑资源复用模块及复用实现的方法
US10423203B2 (en) 2016-12-28 2019-09-24 Intel Corporation Flip-flop circuit with low-leakage transistors

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW392307B (en) * 1998-01-13 2000-06-01 Mitsubishi Electric Corp A method of the manufacture and the setup of the semiconductor apparatus
JPH11340812A (ja) 1998-05-22 1999-12-10 Mitsubishi Electric Corp 半導体装置
US6169419B1 (en) * 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6191606B1 (en) 1998-09-10 2001-02-20 Intel Corporation Method and apparatus for reducing standby leakage current using input vector activation
US7302652B2 (en) * 2003-03-31 2007-11-27 Intel Corporation Leakage control in integrated circuits
US7096374B2 (en) * 2003-05-21 2006-08-22 Agilent Technologies, Inc. Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state
KR100574967B1 (ko) 2004-01-29 2006-04-28 삼성전자주식회사 Ｍｔｃｍｏｓ용 제어회로
US7305335B2 (en) * 2004-11-23 2007-12-04 Schweitzer Engineering Laboratories, Inc. Permanent three-pole independent pole operation recloser simulator feature in a single-pole trip capable recloser control
US20070168792A1 (en) * 2005-12-09 2007-07-19 International Business Machines Corporation Method to Reduce Leakage Within a Sequential Network and Latch Circuit
JP4953716B2 (ja) * 2006-07-25 2012-06-13 パナソニック株式会社 半導体集積回路およびその関連技術
US7949971B2 (en) * 2007-03-27 2011-05-24 International Business Machines Corporation Method and apparatus for on-the-fly minimum power state transition
GB2447944B (en) * 2007-03-28 2011-06-29 Advanced Risc Mach Ltd Reducing leakage power in low power mode
US7735045B1 (en) * 2008-03-12 2010-06-08 Xilinx, Inc. Method and apparatus for mapping flip-flop logic onto shift register logic

Similar Documents

Publication Publication Date Title
JP2011130405A5 (https=)
JP5274670B2 (ja) 不揮発性状態保持ラッチ
US20130015904A1 (en) Power gating control module, integrated circuit device, signal processing system, electronic device, and method therefor
CN101802751B (zh) 多媒体处理功率管理的功率门控
US9785211B2 (en) Independent power collapse methodology
US9246489B1 (en) Integrated clock gating cell using a low area and a low power latch
CN205210876U (zh) 主从式电路及电子装置
US9755623B2 (en) Multi-bit flip-flop with shared clock switch
JP2014510964A (ja) 低電力スタンバイモード制御回路用装置
JP5462703B2 (ja) 順序回路におけるリーク電流の低減システム
TW201503131A (zh) 記憶體儲存電路及驅動記憶體儲存電路之方法
US7996695B2 (en) Circuits and methods for sleep state leakage current reduction
CN104617924A (zh) 高速低功耗多阈值异步置位复位保持型d型触发器
US8884669B2 (en) Electronic device with power mode control buffers
Oruganti et al. Design of a power efficient SPI interface
CN109842402B (zh) 一种低功耗隔离电路及其方法、芯片
TWI470978B (zh) 功率放大裝置及應用該功率放大裝置之無線信號傳送器
CN101977050B (zh) 一种新型绝热逻辑门电路
CN102457253A (zh) 触发器电路设计
US9013218B2 (en) Dual-port negative level sensitive reset data retention latch
US9018976B2 (en) Dual-port positive level sensitive reset preset data retention latch
CN102522829B (zh) 电源管理电路
US9948282B2 (en) Low-power retention flip-flops
US9007091B2 (en) Dual-port positive level sensitive preset data retention latch
CN103535111A (zh) 一种电源电路及无线上网卡