JP2011091075A - Hetero junction field-effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero junction field-effect transistor that suppresses current collapse and reduces a gate leakage current, and to provide a method of manufacturing the same. <P>SOLUTION: The hetero junction field-effect transistor is formed of a nitride semiconductor, and includes a semiconductor layer, and a gate electrode 90 arranged on the semiconductor layer so that a lower part is buried in the semiconductor layer. The semiconductor layer includes a barrier layer 40, and a cap layer 50 formed on the barrier layer 40 and having a thickness of ≤28 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a structure of a heterojunction field effect transistor made of a semiconductor containing nitride and a method for manufacturing the same.

  In a conventional heterojunction field effect transistor (FET) made of a nitride semiconductor, the gate electrode is formed directly on the semiconductor surface. When the gate electrode is operated by applying a pulse voltage, the drain A phenomenon (current collapse) in which the current is greatly reduced occurs, and the output and efficiency when actually operating at a high frequency are greatly reduced as compared with the output and efficiency that can be predicted from the DC characteristics.

  Since current collapse is caused by trap levels formed on the semiconductor surface, in order to suppress current collapse, it is effective to keep the gate electrode / semiconductor interface to which the electric field is most intense away from the semiconductor surface. Therefore, it is desirable to have a recessed gate structure in which the gate electrode is formed after etching only the region where the gate electrode is formed on the semiconductor surface. The deeper the recess portion is, the greater the effect is because the gate electrode / semiconductor interface is further away from the semiconductor surface.

  However, in order to form the recess gate structure, it is necessary to etch the recess depth of the semiconductor layer directly under the gate electrode with good controllability, and it is difficult to control this only by the etching rate.

  Therefore, in the case of a heterojunction FET using an AlGaN / GaN heterostructure, a GaN cap layer equal to the etching depth is formed on the outermost surface to obtain a GaN / AlGaN / GaN structure, and the difference in etching rate between GaN and AlGaN is determined. A method of selectively etching only the GaN cap layer is often used (see, for example, Non-Patent Document 1).

IEEE EDL, VOL.29, NO.4, APRIL 2008, p303

  Many n-type impurities are mixed in the surface of the AlGaN or GaN layer, particularly on the surface side, during epitaxial growth or a process for manufacturing a transistor. Since the region where the effect of polarization by AlGaN works effectively is a depletion layer, the n-type impurity existing in this region is not activated and does not form a current leakage path.

  However, since the polarization effect does not reach in a region far from AlGaN, the n-type impurity mixed in this region is activated to become a carrier, which can be a current leakage path.

  Accordingly, when the outermost GaN cap layer is so thick that the polarization effect of AlGaN does not reach, when the transistor is operated by applying a high voltage between the gate electrode and the drain electrode, a large voltage is applied from the gate electrode to the drain electrode. Leakage current occurs, resulting in a decrease in breakdown voltage that leads to a decrease in output and efficiency, a deterioration in noise characteristics, a decrease in reliability, and the like.

  In view of the above-described problems, an object of the present invention is to provide a nitride semiconductor device that suppresses current collapse and reduces gate leakage current, and a method for manufacturing the same.

  The heterojunction field effect transistor of the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and includes a semiconductor layer and a gate electrode provided on the semiconductor layer so as to be buried in the lower portion of the semiconductor layer. The semiconductor layer includes a barrier layer and a cap layer having a thickness of 28 nm or less formed on the barrier layer.

  The method for manufacturing a heterojunction field effect transistor comprising a nitride semiconductor according to the present invention includes: (a) a step of forming a cap layer having a thickness of 28 nm or less on the barrier layer; and (b) etching the cap layer. Forming a trench having a predetermined length; and (c) forming a gate electrode in the trench.

  The heterojunction field effect transistor of the present invention includes a semiconductor layer and a gate electrode provided on the semiconductor layer so as to be buried in the lower portion of the semiconductor layer. The semiconductor layer includes the barrier layer and the barrier layer. And a cap layer having a thickness of 28 nm or less. Thereby, generation | occurrence | production of a gate leak current can be suppressed, maintaining the recessed gate structure aiming at suppression of current collapse.

  The method for manufacturing a heterojunction field effect transistor comprising a nitride semiconductor according to the present invention includes: (a) a step of forming a cap layer having a thickness of 28 nm or less on the barrier layer; and (b) etching the cap layer. Forming a trench having a predetermined length; and (c) forming a gate electrode in the trench. By forming an electrode in the trench, the generation of a gate leakage current is suppressed by setting the cap layer to 28 nm or less while maintaining a recessed gate structure for the purpose of suppressing current collapse.

It is a figure which shows the structure of the heterojunction FET of this invention. It is the figure which showed the relationship between the thickness of a cap layer, gate current, and gate edge electric field strength. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the structure of the heterojunction FET (modification) of this invention. It is a figure which shows the manufacturing process of the heterojunction FET of this invention. It is a figure which shows the manufacturing process of the heterojunction FET of this invention. It is a figure which shows the manufacturing process of the heterojunction FET of this invention. It is a figure which shows the manufacturing process of the heterojunction FET of this invention. It is a figure which shows the manufacturing process of the heterojunction FET of this invention. It is a figure which shows the manufacturing process of the heterojunction FET (modification) of this invention. It is a figure which shows the manufacturing process of the heterojunction FET (modification) of this invention. It is a figure which shows the manufacturing process of the heterojunction FET (modification) of this invention.

(Embodiment 1)
<Configuration>
FIG. 1 shows an example of the structure of a heterojunction FET made of a nitride semiconductor according to the first embodiment. The heterojunction FET according to the first embodiment includes a semi-insulating SiC substrate 10, a buffer layer 20 formed on the SiC substrate 10, a channel layer 30 made of GaN formed on the buffer layer 20, and a channel layer A barrier layer 40 made of AlGaN formed on the gate electrode 90, a gate electrode 90 made of Ni / Au formed on the barrier layer 40 and a cap layer 50 made of GaN, and Ti / Al formed on the cap layer 50 A source electrode 70 and a drain electrode 80, and an element isolation region 60. The gate electrode 90 is formed in a region where the cap layer 50 is removed. The lower surface of the gate electrode 90 is formed in contact with the upper surface of the barrier layer 40.

  That is, the heterojunction FET of the present embodiment is characterized in that the lower surface of the gate electrode 90 is in contact with the upper surface of the barrier layer 40. Thereby, a recess gate structure can be realized and current collapse can be suppressed.

  In the above structure, by setting the thickness of the cap layer 50 to 28 nm or less, the gate leakage current can be kept sufficiently low while the effect of suppressing the current collapse by the recess gate structure is maintained. The reason why the thickness of the cap layer 50 is 28 nm or less will be described below.

<Cap layer thickness>
FIG. 2 is a graph obtained by measuring a current value (gate current) that flows between the gate electrode 90 and the drain electrode 80 when a voltage of −10 V is applied to the gate electrode, using an actually manufactured device. The GaN cap layer 50 has four different thicknesses of 0, 20, 50, and 100 nm. Then, as shown in FIG. 2, when the GaN cap layer 50 was thinner than 20 nm, the gate leakage current was a sufficiently low value of 2.0 × 10 ⁻⁶ (A / mm) or less. On the other hand, when the GaN cap layer 50 is thicker than 50 nm, the gate leakage current is about 1.0 × 10 ⁻⁴ (A / mm), which is about two orders of magnitude larger than the case of 20 nm or less. There is concern about deterioration.

  As a factor that causes such a large gate leakage current, there is a carrier due to an n-type impurity mixed in the GaN cap 50 particularly on the surface side during the epitaxial growth or the HEMT manufacturing process. The region on the AlGaN barrier layer 40 side of the GaN cap layer 50 receives the effect of polarization by the AlGaN barrier layer 40 and is therefore depleted even if n-type impurities are mixed. Therefore, the mixed n-type impurity is not activated and does not behave as a carrier, so that the region does not become a leak path. Therefore, when the GaN cap layer 50 is thin enough to exert the polarization effect of the AlGaN barrier layer 40, no leak current is generated even if n-type impurities are mixed in the GaN cap layer 50.

  On the other hand, when an n-type impurity is mixed in a region far from the effect of polarization by the AlGaN layer 40 in the GaN cap layer 50, the n-type impurity is activated and behaves as a carrier because the region is not depleted. It will be. Therefore, when the GaN cap layer 50 is so thick that the effect of polarization of the AlGaN layer 40 does not reach and n-type impurities are mixed in a region where the effect of polarization does not reach, the region becomes a leak path and a large leak current is generated.

  FIG. 2 also shows the result of calculating the gate leakage current due to this effect. In this calculation, the carrier concentration generated on the surface side of the GaN cap layer 50 was first derived from the band structure calculated using the Poisson equation in the structure where the thickness of the GaN cap layer 50 is different. Subsequently, using them, the current flowing through the Schottky barrier from the gate electrode 90 into the GaN cap layer 50 was calculated. Finally, the current value in the actual HEMT when the GaN cap layer 50 is not formed is added to the tunnel current calculated assuming that the current value flows outside the GaN cap layer 50, and plotted in FIG. The calculated value is in good agreement with the actually measured value, and it has been found from this calculation result that a large leakage current occurs when the thickness of the GaN cap layer 50 is greater than 28 nm. Therefore, in order to suppress the gate leakage current to a sufficiently small value, the thickness of the GaN cap layer 50 needs to be 28 nm or less.

  That is, the heterojunction FET made of a nitride semiconductor of the present embodiment includes a semiconductor layer and a gate electrode 90 provided on the semiconductor layer so as to be buried in the lower portion of the semiconductor layer. A barrier layer 40 and a cap layer 50 having a thickness of 28 nm or less formed on the barrier layer 40 are provided. Thereby, gate leakage can be reduced while current collapse is suppressed by the recessed gate structure.

  FIG. 2 also shows the result of calculating the electric field strength generated at the gate electrode end on the drain electrode 80 side when the thickness of the GaN cap layer 50 is different by solving the Poisson equation. Since current collapse increases as the electric field strength generated at the gate electrode end increases, it can be seen from this calculation result that the thicker the GaN cap layer 50 is, the more preferable the structure is from the viewpoint of suppressing current collapse. That is, the suppression of current collapse and the suppression of gate leakage current are in a trade-off relationship with respect to the thickness of the GaN cap layer 50, and the thickness of the GaN cap layer 50 can be as long as it is 28 nm or less at which no large leakage current occurs. The thicker is preferable. However, even if the thickness of the GaN cap layer 50 is about 2 nm, there is an effect of reducing the electric field strength by about 30% compared to the case where the GaN cap layer 50 is not provided. I can say that. Therefore, the thickness of the GaN cap layer 50 may be at least 2 nm.

  Further, in consideration of the variation in thickness when forming the GaN cap layer 50, it is necessary to further increase the thickness in order to prevent a region of 2 nm or less from occurring on the entire wafer surface. The thickness of the GaN cap layer 50 may be 7 nm or more.

<Modification>
FIG. 1 shows a typical example of the heterojunction FET according to the present embodiment, but the same effect can be obtained by the following modification.

  For example, a spacer layer 100 made of a material (for example, AlN) having a larger band gap than the material forming these layers may be formed between the channel layer 30 and the barrier layer 40 (FIG. 3). With such a structure, the confinement effect of the two-dimensional electron gas (2DEG) generated on the barrier layer 40 side of the channel layer 30 can be increased, so that the concentration is increased and the alloy scattering is also reduced, so that the mobility is increased. As a result, the transistor can be increased in current and output.

The channel layer 30, spacer layer 100, the barrier layer 40, the bandgap respective B ₃₀ of the cap layer 50, B _40, B _50, when the B _100, they are _{B 30 <B 40 <B 100} , B 50 If the relationship <B ₄₀ is satisfied, the heterojunction FET is operated, the concentration and mobility of the two-dimensional electron gas by the spacer layer 100 are improved, and only the cap layer 50 in the region of the gate electrode 90 is selectively removed. I can do it. Therefore, as described above, the cap layer is not necessarily made of GaN and the barrier layer is not made of AlGaN, and is composed of a compound semiconductor composed of at least two elements including N among Al, Ga, and N having different constituent compositions. It only has to be done.

For example, the compound semiconductors constituting the channel layer 30, the spacer layer 100, the barrier layer 40, and the cap layer 50 are Al _X30 Ga _{1 -X30} N, Al _X100 Ga _{1 -X100} N, Al _X40 Ga _{1 -X40} N, and Al _{X50, respectively. Assuming} Ga _{1 -X50} N, 0 ≦ X ₃₀ <1, 0 ≦ X ₁₁₀ <1, 0 ≦ X ₄₀ <1, 0 ≦ X ₅₀ <1, X ₃₀ <X ₄₀ <X _100, X ₅₀ <X ₄₀ What is necessary is just to be comprised with the compound semiconductor which satisfy | fills the relationship. When the channel layer 30, the spacer layer 100, the barrier layer 40, and the cap layer 50 are composed of a compound composed of at least two elements including N among Al, Ga, and N, a large polarization effect is generated in the barrier layer 40. A high-concentration two-dimensional electron gas can be generated on the barrier layer 40 side of the channel layer 30, which is advantageous for increasing the current and output of the transistor.

  Furthermore, it is not necessary to be composed of a compound composed of at least two elements including N out of Al, Ga, and N. For example, it is composed of a compound semiconductor composed of at least two elements including N among In, Al, Ga, and N. May be.

The heterojunction FET has a higher breakdown voltage as the dielectric breakdown field of the semiconductor material used for the channel layer 30 is higher. Since Al _X Ga _{1 -X} N has a higher band gap and a higher breakdown electric field as the Al composition is higher, the Al composition is higher when the channel layer 30 is composed of Al _X30 Ga _{1 -X30} N as described above. (X ₃₀ is close to 1) is preferred. In addition, since the gate leakage current flowing from the gate electrode 90 to the hetero interface through the barrier layer 40 is suppressed as the band gap of the semiconductor material used for the barrier layer 40 is larger, Al _X40 Ga _{1 -X40} used as the barrier layer 40 Similarly, it is preferable that N has a higher Al composition.

  In addition, the channel layer 30, the spacer layer 100, the barrier layer 40, and the cap layer 50 do not necessarily have a single-layer structure with the same composition. As long as the above-described band gap condition is satisfied, the In composition and the Al composition The Ga composition may vary spatially, or a multilayer film composed of several different layers may be used. These layers may contain n-type and p-type impurities.

  The semi-insulating SiC substrate 10 may be Si, sapphire, GaN, AlN, or the like. When GaN is used for the substrate 10, the channel layer 30, the spacer layer 100, the barrier layer 40, etc. can be formed without forming the buffer layer 20. Therefore, it is not necessary to form the buffer layer 20 on the substrate 10.

  Further, as shown in FIG. 4, a high concentration doping region 110 in which an n-type impurity is doped at a high concentration is formed in at least a part of the semiconductor layer below the source electrode 70 and the drain electrode 80. Also good. With such a structure, the resistance between the two-dimensional electron gas generated on the barrier layer 40 side of the channel layer 30 and the source / drain electrodes can be reduced, so that the current of the transistor can be increased and the output can be increased. It is advantageous and can be said to be a more preferable structure. In the figure, the high-concentration doping region 110 is formed from the semiconductor surface to the channel layer 30; however, the region is not necessarily limited to this region. If it is formed in at least a part of the semiconductor layer below the drain electrode 80, the above-described effects can be obtained.

  At least a part of the semiconductor layer below the source electrode 70 and the drain electrode 80 may be removed as shown in FIG. By adopting such a structure, it is possible to reduce the two-dimensional electron gas generated on the barrier layer 40 side of the channel layer 30 and the resistance on the source / drain electrode side, thereby increasing the current of the transistor and increasing the output. It is advantageous and can be said to be a more preferable structure. In FIG. 5, the region from the semiconductor surface to the barrier layer 40 is removed for forming the source / drain electrodes. However, the region is not necessarily limited to this region. If the inside of at least a part of the semiconductor layer below the source electrode 70 and the drain electrode 80 is removed, the above-described effect can be obtained.

  Further, the source electrode 70 and the drain electrode 80 are not necessarily made of Ti / Al, and metals such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, and W can be obtained if ohmic characteristics are obtained. Alternatively, it may be formed of a multilayer film composed of these.

  If the bottom surface of the gate electrode 90 is not in contact with the surface of the cap layer 50, current collapse can be suppressed as compared with the case where the gate electrode 90 is in contact with the surface of the cap layer 50. For example, a structure in contact with the inside of the cap layer 50 (FIG. 6) or a structure in contact with the inside of the barrier layer 40 (FIG. 7) may be used. However, in order to etch the etching depth of the semiconductor layer immediately below the gate electrode 90 with good controllability, it is preferable to use a difference in rate when etching layers having different structures. In that case, FIG. 3 to 5, a structure in which the bottom surface of the gate electrode 90 is in contact with the vicinity of the vicinity of the interface between the barrier layer 40 and the cap layer 50 is more preferable.

  The gate electrode 90 does not necessarily have a square cross section, and may be a gate electrode 91 having a T-type or Y-type structure as shown in FIG. With such a structure, the gate resistance can be reduced while maintaining the area where the gate electrode 91 is in contact with the semiconductor. Further, as shown in FIG. 9, the gate electrode 91 may be formed so as to be in contact with the surface of the cap 50. With such a structure, the electric field concentrated on the edge portion of the gate electrode 91 on the drain electrode 80 side during high voltage operation can be relaxed, and current collapse can be suppressed and the breakdown voltage can be increased.

  Further, in the structure of the gate electrode 91 shown in FIG. 8, at least one part of at least one kind of atoms of Al, Ga, Si, Hf, and Ti is formed in at least a part between the collar portion of the gate electrode 91 and the cap layer 50. A structure as shown in FIG. 10 in which an insulating film 120 made of oxide, nitride, oxynitride, or the like is formed may be used. With such a structure, the electric field concentrated on the edge portion of the gate electrode 91 on the drain electrode 80 side during high voltage operation can be relaxed, and current collapse can be suppressed and the breakdown voltage can be increased. Further, by forming the insulating film 120 only below the gate electrode 91 as shown in FIG. 11, the capacitance generated between the source electrode 70 and the gate electrode 91 or between the gate electrode 91 and the drain electrode 80 is reduced. The gain and efficiency at the time of high frequency operation can be improved.

  Further, the gate electrode 90 shown in FIGS. 1 and 3 to 7 and the gate electrode 91 shown in FIGS. 8 to 11 are not necessarily Ni / Al, Ti, Al, Pt, Au, Ni, Pd, etc. It may be formed of a metal such as IrSi, PtSi, NiSi 2 or the like, a nitride metal such as TiN or WN, or a multilayer film composed of these.

  Although various modifications have been described above, it is not necessary to employ all of the above-described structures individually. For example, as shown in FIG.

  Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device in a structure in which a protective film, a wiring, a via hole, and the like are formed.

<Manufacturing process>
13 to 20 are diagrams showing an example of a manufacturing process of the heterojunction FET according to the first embodiment. In these drawings, the same or corresponding components as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, the manufacturing process of the heterojunction FET according to the first embodiment will be described with reference to FIGS.

  First, an epitaxial growth method such as MOCVD or MBE is applied to the substrate 10 to form a buffer layer 20, a channel layer 30 made of GaN, a barrier layer 40 made of AlGaN, and a cap layer 50 made of GaN containing n-type impurities. Epitaxial growth is performed sequentially from the bottom (FIG. 13). By adjusting the flow rate, pressure, temperature, and time of trimethylammonium, trimethylgallium, trimethylindium, ammonia, or silane or oxygen, which are source gases for nitride semiconductor, the channel layer 30 and the barrier layer 40. The cap layer 50 can be formed to have a desired composition, film thickness, and doping concentration. The cap layer 50 has a thickness of 2 to 28 nm, or 7 to 28 nm.

  In the case where the spacer layer 100 is provided as shown in FIG. 3, after the channel layer 30 is grown on the buffer 20, the spacer layer made of a material having a larger band gap than the material forming the channel layer 30 and the barrier layer 40. 100 is formed, and then the barrier layer 40 is formed on the spacer layer 100.

  Next, a source electrode 70 and a drain electrode 80 made of a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, Pt, or a multilayer film composed of these metals are deposited. It deposits using the method and a sputtering method, and forms by the lift-off method etc. (FIG. 14).

When providing the high concentration doping region 110 as shown in FIG. 4, before forming the source electrode 70 and the drain electrode 80, the source electrode 80 and the drain electrode 90 are formed using the resist pattern 140 of FIG. 18 as a mask. With respect to the semiconductor layer under the region, n-type ions are implanted into a desired region in a nitride semiconductor such as silicon by an ion implantation method or the like. The implantation dose is 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻² and the implantation energy is 10 to 1000 keV. Thereafter, a high concentration doping region 110 is formed by activating the implanted ions by performing a heat treatment (FIG. 18).

After forming the source electrode 70 and the drain electrode 80 after the step of FIG. 14, the source electrode 70 and the drain electrode 80 are formed by a dry etching method using Cl ₂ or the like using the resist pattern 150 as a mask as shown in FIG. By removing at least a part of the semiconductor layer below the region where the drain electrode 80 is to be formed, a heterojunction FET having a structure as shown in FIG. 5 can be manufactured.

  Thereafter, an element isolation region 60 is formed in the channel layer 30, the barrier layer 40, and the cap layer 50 outside the region for forming the transistor by using, for example, ion implantation or etching (FIG. 15).

Then, using the resist pattern 130 as a mask, the cap layer 50 in the region where the gate electrode 90 is to be formed is removed by a dry etching method using Cl ₂ or the like (FIG. 16). When the Al composition ratios of the cap layer 50 and the barrier layer 40 are different, the cap layer is selectively capped by using, for example, a fluorine-based gas such as oxygen or SF ₆ in addition to a chlorine-based gas such as Cl _{2 at} the time of etching. Only the layer 50 can be etched, and the controllability of the etching depth is improved. Note that the heterojunction FETs having various gate electrode structures shown in FIGS. 6 and 7 can be formed by adjusting the etching time and the gas flow rate to have a desired etching depth.

  After removing the resist pattern 130, a metal such as Ti, Al, Pt, Au, Ni and Pd, a silicide such as IrSi, PtSi and NiSi2, a nitride metal such as TiN and WN, or a multilayer film composed of these metals A gate electrode 90 is deposited by vapor deposition or sputtering, and formed by lift-off or the like (FIG. 17). Here, if a resist pattern wider than the etching region is used, a T-shaped gate electrode 90 as shown in FIG. 9 is formed.

  That is, in the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 50 having a thickness of 28 nm or less on the barrier layer 40; Etching to form a trench having a predetermined length, and (c) forming a gate electrode 90 in the trench. By making the recess gate structure, current collapse is suppressed, and by making the thickness of the cap layer 50 28 nm or less, gate leakage can be reduced.

  When forming the insulating film 13 as shown in FIG. 10, before performing the etching for forming the gate electrode shown in FIG. 16, for example, using an evaporation method or a plasma CVD method, Al, Ga, Si, Hf, An insulating film 120 made of oxide, nitride, or oxynitride of at least one atom of Ti is deposited (FIG. 20). Thereafter, by forming the gate electrode 91, the heterojunction FET having the structure shown in FIG. 10 can be manufactured. In order to finally use as a device, it is necessary to form a wiring after part of the source electrode 70 and the drain electrode 80 covered with the insulating film 120 is removed by wet etching using, for example, hydrofluoric acid. is there.

  Further, after the gate electrode 91 is formed as described above, the insulating film 120 is completely removed by wet etching using hydrofluoric acid or the like, whereby a heterojunction FET having a structure as shown in FIG. 8 can be manufactured. . Further, by adjusting the processing conditions (time and concentration) of wet etching using hydrofluoric acid or the like, a heterojunction FET having the structure shown in FIG. 11 in which the insulating film 120 in a desired region is left can be manufactured.

  Note that the three steps of forming the source electrode 70 and the drain electrode 80 shown in FIG. 14, forming the element isolation region 60 shown in FIG. 15, and forming the gate electrode 90 (91) shown in FIGS. There is no need to change the order of the steps. For example, the element isolation region 60 may be formed before the source electrode 70 and the drain electrode 80 are formed.

  Moreover, it is not necessary to employ all the processes described above, and a process combining them may be used.

  With the above method, the heterojunction FET of this embodiment can be manufactured. Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device through a formation process of a protective film, a wiring, a via hole, and the like.

<Effect>
According to the heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, the heterojunction FET made of a nitride semiconductor of the present embodiment includes a semiconductor layer and a gate electrode 90 provided on the semiconductor layer so as to be buried in the lower portion of the semiconductor layer. A barrier layer 40 and a cap layer 50 having a thickness of 28 nm or less formed on the barrier layer 40 are provided. Thereby, gate leakage can be reduced while current collapse is suppressed by the recessed gate structure.

  Further, the lower surface of the gate electrode 90 is located in the barrier layer 40. Thereby, a recess gate structure can be realized and current collapse can be suppressed.

  Alternatively, the heterojunction FET of the present embodiment is characterized in that the lower surface of the gate electrode 90 is located in the barrier layer 40. Even in such a structure, there is an effect of suppressing current collapse by the recess gate structure.

  In addition, according to the method of manufacturing the heterojunction FET of the present embodiment, the following effects can be obtained as already described. That is, in the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 50 having a thickness of 28 nm or less on the barrier layer 40; Etching to form a trench having a predetermined length, and (c) forming a gate electrode 90 in the trench. By making the recess gate structure, current collapse is suppressed, and by making the thickness of the cap layer 50 28 nm or less, gate leakage can be reduced.

  10 substrate, 20 buffer layer, 30 channel layer, 40 barrier layer, 50 cap layer, 60 element isolation region, 70 source electrode, 80 drain electrode, 90 gate electrode, 100 spacer layer, 110 highly doped region, 120 insulating film, 130, 140, 150 Resist pattern.

Claims (4)

A heterojunction field effect transistor made of a nitride semiconductor,
A semiconductor layer;
A gate electrode provided on the semiconductor layer so as to bury a lower part in the semiconductor layer,
The semiconductor layer includes a barrier layer,
A heterojunction field effect transistor comprising: a cap layer having a thickness of 28 nm or less formed on the barrier layer.   The heterojunction field effect transistor according to claim 1, wherein a lower surface of the gate electrode is in contact with an upper surface of the barrier layer.   The heterojunction field effect transistor according to claim 1, wherein a lower surface of the gate electrode is located in the barrier layer. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a cap layer having a thickness of 28 nm or less on the barrier layer;
(B) etching the cap layer to form a trench having a predetermined length;
(C) forming a gate electrode in the trench;
A method of manufacturing a heterojunction field effect transistor comprising:

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