JP2011044580A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2011044580A JP2011044580A JP2009191697A JP2009191697A JP2011044580A JP 2011044580 A JP2011044580 A JP 2011044580A JP 2009191697 A JP2009191697 A JP 2009191697A JP 2009191697 A JP2009191697 A JP 2009191697A JP 2011044580 A JP2011044580 A JP 2011044580A
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- film
- dielectric constant
- high dielectric
- semiconductor device
- constant film
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Abstract
【解決手段】半導体装置は、第1,第2のMISトランジスタnTr,pTrを備えている。第1のMISトランジスタnTrは、第1の活性領域10a上に形成され、第1の高誘電率膜14Xaを有する第1のゲート絶縁膜14Aと、第1のゲート電極18Aとを備えている。第2のMISトランジスタpTrは、第2の活性領域10b上に形成され、第2の高誘電率膜14xを有する第2のゲート絶縁膜14Bと、第2のゲート電極18Bとを備えている。第2の高誘電率膜14xは、第1の調整用金属を含む。第1の高誘電率膜14Xaは、第2の高誘電率膜14xよりも窒素濃度が高く、且つ、第1の調整用金属を含まない。
【選択図】図3
Description
図10は、Alキャップ膜の膜厚を変化させて、HfSiO膜及びHfSiON膜の各々にAlを拡散させた場合の、フラットバンド電圧の変化量(ΔVfb)と酸化膜換算膜厚の変化量(ΔEOT)との関係を示す図である。
図11(a) は、ゲート絶縁膜における高誘電率膜の窒素濃度とn型MISトランジスタの実効仕事関数との関係を示す図である。図11(b) は、ゲート絶縁膜における高誘電率膜の窒素濃度と該高誘電率膜の酸化膜換算膜厚との関係を示す図である。
本発明の第1の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。
本発明の第2の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。なお、第2の実施形態に係る半導体装置及びその製造方法について、第1の実施形態に係る半導体装置及びその製造方法と相違する点を中心に説明し、共通する点については適宜省略して説明する。
本発明の第3の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。なお、第3の実施形態に係る半導体装置及びその製造方法について、第1の実施形態に係る半導体装置及びその製造方法と相違する点を中心に説明し、共通する点については適宜省略して説明する。
本発明の第1の実施形態の変形例に係る半導体装置及びその製造方法について図面を参照しながら説明する。なお、第1の実施形態の変形例に係る半導体装置及びその製造方法について、第1の実施形態に係る半導体装置及びその製造方法と相違する点を中心に説明し、共通する点については適宜省略して説明する。
10a 第1の活性領域
10b 第2の活性領域
11 素子分離領域
12a p型ウェル領域
12b n型ウェル領域
13 下地膜
13a 第1の下地膜
13b 第2の下地膜
14 高誘電率膜
14X 窒素を含む高誘電率膜
14Y Laを含む高誘電率膜
14Z La及び窒素を含む高誘電率膜
14M 窒素を含む高誘電率膜
14N 窒素を含む高誘電率膜
14Xa 窒素を含む第1の高誘電率膜
14Za La及び窒素を含む第1の高誘電率膜
14Na 窒素を含む第1の高誘電率膜
14b 第2の高誘電率膜
14Mb 窒素を含む第2の高誘電率膜
14x Alを含む第2の高誘電率膜
14Mx 窒素及びAlを含む第2の高誘電率膜
14y Al及び窒素を含む第2の高誘電率膜
14A 第1のゲート絶縁膜
14B 第2のゲート絶縁膜
15,15b 第1の調整用金属膜
15X,15Xb 窒素を含む第1の調整用金属膜
16 保護膜
17 金属膜
17a 第1の金属膜
17b 第2の金属膜
18 シリコン膜
18a 第1のシリコン膜
18b 第2のシリコン膜
18F ゲート電極形成膜
18A 第1のゲート電極
18B 第2のゲート電極
19a 第1のオフセットスペーサ
19b 第2のオフセットスペーサ
20a 浅いn型ソースドレイン領域
20b 浅いp型ソースドレイン領域
21a 第1の内側サイドウォール
21b 第2の内側サイドウォール
22a 第1の外側サイドウォール
22b 第2の外側サイドウォール
22A 第1のサイドウォール
22B 第2のサイドウォール
23a 深いn型ソースドレイン領域
23b 深いp型ソースドレイン領域
24a 第1の金属シリサイド膜
24b 第2の金属シリサイド膜
25a 第3の金属シリサイド膜
25b 第4の金属シリサイド膜
26 絶縁膜
27 層間絶縁膜
28a 第1のコンタクトホール
28b 第2のコンタクトホール
29a 第1のコンタクトプラグ
29b 第2のコンタクトプラグ
30 第2の調整用金属膜
Re レジストパターン
Claims (17)
- 第1のMISトランジスタと第2のMISトランジスタとを備えた半導体装置であって、
前記第1のMISトランジスタは、
半導体基板における第1の活性領域上に形成され、第1の高誘電率膜を有する第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された第1のゲート電極とを備え、
前記第2のMISトランジスタは、
前記半導体基板における第2の活性領域上に形成され、第2の高誘電率膜を有する第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された第2のゲート電極とを備え、
前記第2の高誘電率膜は、第1の調整用金属を含み、
前記第1の高誘電率膜は、前記第2の高誘電率膜よりも窒素濃度が高く、且つ、前記第1の調整用金属を含まないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の高誘電率膜は窒素を含む一方、前記第2の高誘電率膜は前記窒素を含まないことを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1の調整用金属は、アルミニウムであることを特徴とする半導体装置。 - 請求項1〜3のうちいずれか1項に記載の半導体装置において、
前記第1の高誘電率膜は第2の調整用金属を含む一方、前記第2の高誘電率膜は前記第2の調整用金属を含まないことを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第2の調整用金属は、ランタンであることを特徴とする半導体装置。 - 請求項1〜5のうちいずれか1項に記載の半導体装置において、
前記第1のゲート絶縁膜は、前記第1の活性領域上に形成された第1の下地膜と、前記第1の下地膜上に形成された前記第1の高誘電率膜とからなり、
前記第2のゲート絶縁膜は、前記第2の活性領域上に形成された第2の下地膜と、前記第2の下地膜上に形成された前記第2の高誘電率膜とからなることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記第1の下地膜及び前記第2の下地膜は、シリコン酸化膜からなることを特徴とする半導体装置。 - 請求項1〜7のうちいずれか1項に記載の半導体装置において、
前記第1の高誘電率膜及び前記第2の高誘電率膜は、比誘電率が10以上の金属酸化物からなることを特徴とする半導体装置。 - 請求項1〜8のうちいずれか1項に記載の半導体装置において、
前記第1のゲート電極は、前記第1のゲート絶縁膜上に形成された第1の金属膜と、前記第1の金属膜上に形成された第1のシリコン膜とからなり、
前記第2のゲート電極は、前記第2のゲート絶縁膜上に形成された第2の金属膜と、前記第2の金属膜上に形成された第2のシリコン膜とからなることを特徴とする半導体装置。 - 請求項1〜9のうちいずれか1項に記載の半導体装置において、
前記第1のゲート電極の側面上に形成された断面形状がL字状の第1のサイドウォールと、
前記第2のゲート電極の側面上に形成された断面形状がL字状の第2のサイドウォールと、
前記第1の活性領域及び前記第2の活性領域上に、前記第1のゲート電極及び前記第1のサイドウォール、並びに前記第2のゲート電極及び前記第2のサイドウォールを覆うように形成された絶縁膜とをさらに備えていることを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記絶縁膜は、前記第1の活性領域におけるチャネル領域のゲート長方向に引っ張り応力を生じさせる応力絶縁膜であり、
前記絶縁膜は、前記第1のサイドウォールの表面に接して形成されていることを特徴とする半導体装置。 - 請求項1〜11のうちいずれか1項に記載の半導体装置において、
前記第1のMISトランジスタは、n型MISトランジスタであり、
前記第2のMISトランジスタは、p型MISトランジスタであることを特徴とする半導体装置。 - 半導体基板における第1の活性領域上に形成された第1のMISトランジスタと前記半導体基板における第2の活性領域上に形成された第2のMISトランジスタとを有する半導体装置の製造方法であって、
前記第1の活性領域及び前記第2の活性領域の上に、高誘電率膜を形成する工程(a)と、
前記高誘電率膜における前記第2の活性領域の上に位置する第1の部分の上に、第1の調整用金属膜を形成する工程(b)と、
前記工程(b)の後に、前記高誘電率膜における前記第1の活性領域の上に位置する第2の部分に、第1の窒素を導入する工程(c)と、
前記工程(c)の後に、前記高誘電率膜における前記第2の部分の上及び前記第1の調整用金属膜の上に、ゲート電極形成膜を形成する工程(d)と、
前記ゲート電極形成膜、前記第1の調整用金属膜及び前記高誘電率膜を順次パターニングすることにより、前記第1の活性領域の上に、前記高誘電率膜における前記第2の部分からなる第1の高誘電率膜を有する第1のゲート絶縁膜、及び前記ゲート電極形成膜からなる第1のゲート電極を順次形成すると共に、前記第2の活性領域の上に、前記高誘電率膜における前記第1の部分からなる第2の高誘電率膜と前記第1の調整用金属膜とを有する第2のゲート絶縁膜、及び前記ゲート電極形成膜からなる第2のゲート電極を順次形成する工程(e)と、
前記工程(e)の後に、前記第2のゲート絶縁膜における前記第2の高誘電率膜に、前記第1の調整用金属膜に含まれる第1の調整用金属を拡散させる工程(f)とを備え、
前記第1の高誘電率膜は、前記第1の調整用金属を含まず前記第1の窒素を含み、
前記第2の高誘電率膜は、前記第1の調整用金属を含み、
前記第1の高誘電率膜は、前記第2の高誘電率膜よりも窒素濃度が高いことを特徴とする半導体装置の製造方法。 - 請求項13に記載の半導体装置の製造方法において、
前記工程(b)よりも後で、且つ前記工程(c)よりも前に、前記高誘電率膜における前記第2の部分に、第2の調整用金属を拡散させる工程(g)をさらに備え、
前記第1の高誘電率膜は前記第2の調整用金属を含む一方、前記第2の高誘電率膜は前記第2の調整用金属を含まないことを特徴とする半導体装置の製造方法。 - 請求項13に記載の半導体装置の製造方法において、
前記工程(a)よりも後で、且つ前記工程(b)よりも前に、前記高誘電率膜における前記第2の部分に、第2の窒素を導入する工程(h)をさらに備え、
前記第1の高誘電率膜は、前記第1の窒素及び前記第2の窒素を含むことを特徴とする半導体装置の製造方法。 - 請求項13〜15のうちいずれか1項に記載の半導体装置の製造方法において、
前記工程(a)よりも前に、前記第1の活性領域及び前記第2の活性領域の上に、下地膜を形成する工程(i)をさらに備え、
前記工程(a)は、前記下地膜の上に、前記高誘電率膜を形成する工程であり、
前記工程(e)は、前記ゲート電極形成膜、前記第1の調整用金属膜、前記高誘電率膜及び前記下地膜を順次パターニングすることにより、前記第1の活性領域の上に、前記下地膜からなる第1の下地膜と前記第1の高誘電率膜とを有する前記第1のゲート絶縁膜、及び前記第1のゲート電極を順次形成すると共に、前記第2の活性領域の上に、前記下地膜からなる第2の下地膜と前記第2の高誘電率膜と前記第1の調整用金属膜とを有する前記第2のゲート絶縁膜、及び前記第2のゲート電極を順次形成する工程であることを特徴とする半導体装置の製造方法。 - 請求項13〜15のうちいずれか1項に記載の半導体装置の製造方法において、
前記工程(d)は、前記高誘電率膜における前記第2の部分の上及び前記第1の調整用金属膜の上に、金属膜を形成する工程(d1)と、前記金属膜の上に、シリコン膜を形成し、前記金属膜と前記シリコン膜とを有する前記ゲート電極形成膜を形成する工程(d2)とを含み、
前記工程(e)は、前記シリコン膜、前記金属膜、前記第1の調整用金属膜及び前記高誘電率膜を順次パターニングすることにより、前記第1の活性領域の上に、前記第1のゲート絶縁膜、及び前記金属膜からなる第1の金属膜と前記シリコン膜からなる第1のシリコン膜とを有する前記第1のゲート電極を順次形成すると共に、前記第2の活性領域の上に、前記第2のゲート絶縁膜、及び前記金属膜からなる第2の金属膜と前記シリコン膜からなる第2のシリコン膜とを有する前記第2のゲート電極を順次形成する工程であることを特徴とする半導体装置の製造方法。
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US (2) | US20120139055A1 (ja) |
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JP2013118323A (ja) * | 2011-12-05 | 2013-06-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US10276697B1 (en) | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance FET with improved reliability performance |
KR20210086455A (ko) * | 2019-12-27 | 2021-07-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 방법 |
US11837660B2 (en) | 2019-12-27 | 2023-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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US8461049B2 (en) * | 2011-10-11 | 2013-06-11 | United Microelectronics Corp. | Method for fabricating semiconductor device |
KR102155511B1 (ko) * | 2013-12-27 | 2020-09-15 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102395061B1 (ko) | 2015-07-02 | 2022-05-10 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR102438374B1 (ko) * | 2017-09-22 | 2022-08-30 | 삼성전자주식회사 | 반도체 장치 |
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US10276697B1 (en) | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance FET with improved reliability performance |
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WO2011021316A1 (ja) | 2011-02-24 |
JP5268829B2 (ja) | 2013-08-21 |
US20140346610A1 (en) | 2014-11-27 |
US8969970B2 (en) | 2015-03-03 |
US20120139055A1 (en) | 2012-06-07 |
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