JP2011014904A - ビアがガウジングされた相互接続構造体及びその製造方法 - Google Patents

ビアがガウジングされた相互接続構造体及びその製造方法 Download PDF

Info

Publication number
JP2011014904A
JP2011014904A JP2010142938A JP2010142938A JP2011014904A JP 2011014904 A JP2011014904 A JP 2011014904A JP 2010142938 A JP2010142938 A JP 2010142938A JP 2010142938 A JP2010142938 A JP 2010142938A JP 2011014904 A JP2011014904 A JP 2011014904A
Authority
JP
Japan
Prior art keywords
dielectric material
forming
conductive
dielectric
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010142938A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011014904A5 (https=
Inventor
Chih-Chao Yang
チーチャオ・ヤン
Eduardus Standaert Theodorus
テオドラス・エドワーダス・スタンダート
Daniel C Edelstein
ダニエル・シー・エデルスタイン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2011014904A publication Critical patent/JP2011014904A/ja
Publication of JP2011014904A5 publication Critical patent/JP2011014904A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2010142938A 2009-06-30 2010-06-23 ビアがガウジングされた相互接続構造体及びその製造方法 Pending JP2011014904A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/494,564 US7964966B2 (en) 2009-06-30 2009-06-30 Via gouged interconnect structure and method of fabricating same

Publications (2)

Publication Number Publication Date
JP2011014904A true JP2011014904A (ja) 2011-01-20
JP2011014904A5 JP2011014904A5 (https=) 2013-10-03

Family

ID=43379790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010142938A Pending JP2011014904A (ja) 2009-06-30 2010-06-23 ビアがガウジングされた相互接続構造体及びその製造方法

Country Status (3)

Country Link
US (1) US7964966B2 (https=)
JP (1) JP2011014904A (https=)
KR (1) KR20110001894A (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110003191A (ko) * 2009-07-03 2011-01-11 삼성전자주식회사 소자 분리막 및 반도체 소자의 형성 방법
US9177917B2 (en) * 2010-08-20 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US9054110B2 (en) * 2011-08-05 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen
US8835305B2 (en) * 2012-07-31 2014-09-16 International Business Machines Corporation Method of fabricating a profile control in interconnect structures
US9030013B2 (en) * 2012-09-21 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures comprising flexible buffer layers
US8749060B2 (en) * 2012-09-21 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US10043706B2 (en) * 2013-01-18 2018-08-07 Taiwan Semiconductor Manufacturing Company Limited Mitigating pattern collapse
US10032712B2 (en) * 2013-03-15 2018-07-24 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structure
CN111554659B (zh) * 2013-03-29 2022-05-24 联华电子股份有限公司 插塞结构及其制作工艺
US9349691B2 (en) 2014-07-24 2016-05-24 International Business Machines Corporation Semiconductor device with reduced via resistance
US9991200B2 (en) 2014-09-25 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Air gap structure and method
US9685370B2 (en) 2014-12-18 2017-06-20 Globalfoundries Inc. Titanium tungsten liner used with copper interconnects
US10211148B2 (en) * 2015-12-14 2019-02-19 International Business Machines Corporation Structural enhancement of Cu nanowires
US9935051B2 (en) 2016-08-18 2018-04-03 International Business Machines Corporation Multi-level metallization interconnect structure
JP2018107227A (ja) * 2016-12-26 2018-07-05 ソニーセミコンダクタソリューションズ株式会社 半導体装置、半導体装置の製造方法、及び、固体撮像素子
US10615117B2 (en) * 2016-12-29 2020-04-07 Intel Corporation Self-aligned via
WO2018190817A1 (en) * 2017-04-12 2018-10-18 Intel Corporation Integrated circuit interconnects
KR102438179B1 (ko) * 2017-11-02 2022-08-30 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지, 및 상기 반도체 장치의 제조 방법
US20200111741A1 (en) * 2018-10-09 2020-04-09 International Business Machines Corporation Vertical electrical fuse
US11177169B2 (en) * 2019-06-21 2021-11-16 International Business Machines Corporation Interconnects with gouged vias
CN119364753B (zh) * 2023-07-12 2026-02-13 长鑫科技集团股份有限公司 半导体结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008036115A1 (en) * 2006-03-01 2008-03-27 International Business Machines Corporation Novel structure and method for metal integration
US20080128907A1 (en) * 2006-12-01 2008-06-05 International Business Machines Corporation Semiconductor structure with liner
JP2008543078A (ja) * 2005-05-31 2008-11-27 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 補強層を設けることによって低ｋ誘電体内に埋め込まれる銅含有線を形成するための技術
JP2009027048A (ja) * 2007-07-23 2009-02-05 Panasonic Corp 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5162869B2 (ja) * 2006-09-20 2013-03-13 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7846834B2 (en) * 2008-02-04 2010-12-07 International Business Machines Corporation Interconnect structure and method for Cu/ultra low k integration
US7834457B2 (en) * 2008-02-28 2010-11-16 International Business Machines Corporation Bilayer metal capping layer for interconnect applications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008543078A (ja) * 2005-05-31 2008-11-27 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 補強層を設けることによって低ｋ誘電体内に埋め込まれる銅含有線を形成するための技術
WO2008036115A1 (en) * 2006-03-01 2008-03-27 International Business Machines Corporation Novel structure and method for metal integration
JP2009528702A (ja) * 2006-03-01 2009-08-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 金属統合のための新規な構造体及び方法
US20080128907A1 (en) * 2006-12-01 2008-06-05 International Business Machines Corporation Semiconductor structure with liner
JP2009027048A (ja) * 2007-07-23 2009-02-05 Panasonic Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US20100327446A1 (en) 2010-12-30
US7964966B2 (en) 2011-06-21
KR20110001894A (ko) 2011-01-06

Similar Documents

Publication Publication Date Title
JP5430946B2 (ja) 相互接続構造体形成方法
US7964966B2 (en) Via gouged interconnect structure and method of fabricating same
US8354751B2 (en) Interconnect structure for electromigration enhancement
US7867895B2 (en) Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric
JP5462807B2 (ja) 高い漏れ抵抗を有する相互接続構造体
US7834457B2 (en) Bilayer metal capping layer for interconnect applications
JP5255292B2 (ja) ２層金属キャップを有する相互接続構造体及びその製造方法
JP5419328B2 (ja) 障壁冗長構成要素を有する相互接続構造体および相互接続構造体を形成する方法
US8232196B2 (en) Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration
JP5089575B2 (ja) 相互接続構造体及びその製造方法
US7846834B2 (en) Interconnect structure and method for Cu/ultra low k integration
US20080128907A1 (en) Semiconductor structure with liner
KR20100098673A (ko) 상호접속 구조에 대한 귀금속 캡
JP5385610B2 (ja) 相互接続構造体の形成方法
KR100632038B1 (ko) 다층 금속 배선의 제조 방법
JP2005129746A (ja) 半導体装置の製造方法および半導体装置

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130301

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20130801

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130805

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20130805

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130801

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20130924

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131022

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140120

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140123

RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20140216

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140507