JP2010504698A5 - - Google Patents

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Publication number
JP2010504698A5
JP2010504698A5 JP2009529261A JP2009529261A JP2010504698A5 JP 2010504698 A5 JP2010504698 A5 JP 2010504698A5 JP 2009529261 A JP2009529261 A JP 2009529261A JP 2009529261 A JP2009529261 A JP 2009529261A JP 2010504698 A5 JP2010504698 A5 JP 2010504698A5
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JP
Japan
Prior art keywords
data
clock
bit
sampling
header
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JP2009529261A
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English (en)
Japanese (ja)
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JP5325107B2 (ja
JP2010504698A (ja
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Priority claimed from PCT/US2007/020526 external-priority patent/WO2008036413A1/en
Publication of JP2010504698A publication Critical patent/JP2010504698A/ja
Publication of JP2010504698A5 publication Critical patent/JP2010504698A5/ja
Application granted granted Critical
Publication of JP5325107B2 publication Critical patent/JP5325107B2/ja
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JP2009529261A 2006-09-21 2007-09-21 シリアルディジタルデータ通信インターフェイス Active JP5325107B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US84617706P 2006-09-21 2006-09-21
US60/846,177 2006-09-21
PCT/US2007/020526 WO2008036413A1 (en) 2006-09-21 2007-09-21 Serial digital data communication interface

Publications (3)

Publication Number Publication Date
JP2010504698A JP2010504698A (ja) 2010-02-12
JP2010504698A5 true JP2010504698A5 (enExample) 2011-12-08
JP5325107B2 JP5325107B2 (ja) 2013-10-23

Family

ID=39092977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009529261A Active JP5325107B2 (ja) 2006-09-21 2007-09-21 シリアルディジタルデータ通信インターフェイス

Country Status (5)

Country Link
US (1) US8027421B2 (enExample)
EP (1) EP2064828B1 (enExample)
JP (1) JP5325107B2 (enExample)
CN (1) CN101529790B (enExample)
WO (1) WO2008036413A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7890684B2 (en) * 2006-08-31 2011-02-15 Standard Microsystems Corporation Two-cycle return path clocking
EP2341445B1 (en) * 2009-12-30 2017-09-06 Intel Deutschland GmbH Method for high speed data transfer
US9712206B2 (en) * 2010-12-27 2017-07-18 Microchip Technology Incorporated Preamble design and processing method for on-the-fly, frame-by-frame air data rate detection in wireless receivers
US8984197B2 (en) * 2012-12-11 2015-03-17 Agileswitch, Llc Power stack control systems
JP6201331B2 (ja) * 2013-02-15 2017-09-27 オムロン株式会社 同期シリアルインタフェース回路
US9037893B2 (en) * 2013-03-15 2015-05-19 Analog Devices, Inc. Synchronizing data transfer from a core to a physical interface
US10386214B2 (en) * 2015-11-30 2019-08-20 Analog Devices Global Electromagnetic flow sensor interface allowing dc coupling
JP7070496B2 (ja) * 2019-04-24 2022-05-18 オムロン株式会社 シリアルデータ通信装置
CN112019318B (zh) * 2020-08-20 2021-08-20 珠海格力电器股份有限公司 提高设备通信可靠性的方法
CN113886300B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53119604A (en) * 1977-03-28 1978-10-19 Toshiba Corp Transmission system for control signal of key telephone set
JPS6376640A (ja) * 1986-09-19 1988-04-06 Nec Corp 調歩同期信号受信回路
US4965884A (en) * 1989-11-22 1990-10-23 Northern Telecom Limited Data alignment method and apparatus
US5727004A (en) * 1995-03-14 1998-03-10 Adaptive Networks, Inc. Method and apparatus for data encoding and communication over noisy media
EP0738057A3 (de) 1995-04-12 1998-05-20 Siemens Aktiengesellschaft Verfahren und Anordnung zur Bitsynchronisation
JP2821438B2 (ja) * 1996-08-14 1998-11-05 静岡日本電気株式会社 マイクロコンピュータ
ATE201118T1 (de) 1996-11-08 2001-05-15 Cit Alcatel Datenübertragungssynchronisierungsverfahren zwischen einem sender und einem empfänger
JP2000174736A (ja) * 1998-12-08 2000-06-23 Sharp Corp ビット同期回路
WO2001095552A2 (en) * 2000-06-02 2001-12-13 Connectcom Microsystems, Inc. High frequency network receiver
US7158592B2 (en) * 2000-10-31 2007-01-02 Agere Systems, Inc. Method and apparatus for synchronizing data transfer
US6892314B2 (en) 2001-04-02 2005-05-10 International Business Machines Corporation Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
DE60135505D1 (de) * 2001-10-02 2008-10-02 Hitachi Ltd Vorrichtung zum transfer serieller daten
KR100441606B1 (ko) * 2001-10-05 2004-07-23 삼성전자주식회사 복수의 모듈들간의 데이터 송수신 시스템 및 송수신제어방법
JP2003134098A (ja) * 2001-10-24 2003-05-09 Matsushita Electric Ind Co Ltd シリアル受信装置
US7317489B2 (en) * 2004-01-09 2008-01-08 Analog Devices, Inc Teletext data detection by data content based synchronization and error reduction
KR100608362B1 (ko) * 2004-04-22 2006-08-08 주식회사 하이닉스반도체 펄스 발생기
US7890684B2 (en) * 2006-08-31 2011-02-15 Standard Microsystems Corporation Two-cycle return path clocking

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