JP2010251724A - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

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Publication number
JP2010251724A
JP2010251724A JP2010065782A JP2010065782A JP2010251724A JP 2010251724 A JP2010251724 A JP 2010251724A JP 2010065782 A JP2010065782 A JP 2010065782A JP 2010065782 A JP2010065782 A JP 2010065782A JP 2010251724 A JP2010251724 A JP 2010251724A
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JP
Japan
Prior art keywords
silicon
layer
substrate
silicon carbide
insulating layer
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Withdrawn
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JP2010065782A
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English (en)
Japanese (ja)
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JP2010251724A5 (enExample
Inventor
Toru Takayama
徹 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2010065782A priority Critical patent/JP2010251724A/ja
Publication of JP2010251724A publication Critical patent/JP2010251724A/ja
Publication of JP2010251724A5 publication Critical patent/JP2010251724A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2010065782A 2009-03-26 2010-03-23 半導体基板の作製方法 Withdrawn JP2010251724A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010065782A JP2010251724A (ja) 2009-03-26 2010-03-23 半導体基板の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009075824 2009-03-26
JP2010065782A JP2010251724A (ja) 2009-03-26 2010-03-23 半導体基板の作製方法

Publications (2)

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JP2010251724A true JP2010251724A (ja) 2010-11-04
JP2010251724A5 JP2010251724A5 (enExample) 2013-04-04

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JP2010065782A Withdrawn JP2010251724A (ja) 2009-03-26 2010-03-23 半導体基板の作製方法

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US (1) US8043937B2 (enExample)
JP (1) JP2010251724A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058355A1 (ja) 2021-10-06 2023-04-13 信越半導体株式会社 ヘテロエピタキシャル膜の作製方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513090B2 (en) * 2009-07-16 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, and semiconductor device
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
JP5728954B2 (ja) * 2011-01-13 2015-06-03 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP6572694B2 (ja) * 2015-09-11 2019-09-11 信越化学工業株式会社 ＳｉＣ複合基板の製造方法及び半導体基板の製造方法
CN117198983A (zh) * 2015-11-20 2023-12-08 环球晶圆股份有限公司 使半导体表面平整的制造方法
US11791226B2 (en) * 2019-09-26 2023-10-17 Qualcomm Incorporated Device on ceramic substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226307A (ja) * 1992-02-17 1993-09-03 Nippon Telegr & Teleph Corp <Ntt> 半導体基板の製造方法
JP2002502119A (ja) * 1998-01-28 2002-01-22 コミツサリア タ レネルジー アトミーク 半導体オン絶縁体特にＳｉＣＯＩ構造を製造する方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0788274B2 (ja) 1985-09-18 1995-09-27 三洋電機株式会社 ＳｉＣ単結晶の成長方法
JPH067594B2 (ja) 1987-11-20 1994-01-26 富士通株式会社 半導体基板の製造方法
JP2680617B2 (ja) 1988-08-05 1997-11-19 三洋電機株式会社 炭化ケイ素単結晶の成長方法
US5563428A (en) * 1995-01-30 1996-10-08 Ek; Bruce A. Layered structure of a substrate, a dielectric layer and a single crystal layer
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226307A (ja) * 1992-02-17 1993-09-03 Nippon Telegr & Teleph Corp <Ntt> 半導体基板の製造方法
JP2002502119A (ja) * 1998-01-28 2002-01-22 コミツサリア タ レネルジー アトミーク 半導体オン絶縁体特にＳｉＣＯＩ構造を製造する方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058355A1 (ja) 2021-10-06 2023-04-13 信越半導体株式会社 ヘテロエピタキシャル膜の作製方法
KR20240088776A (ko) 2021-10-06 2024-06-20 신에쯔 한도타이 가부시키가이샤 헤테로에피택셜막의 제작방법

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Publication number Publication date
US8043937B2 (en) 2011-10-25
US20100248445A1 (en) 2010-09-30

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