JP2010244596A5 - - Google Patents

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Publication number
JP2010244596A5
JP2010244596A5 JP2009089878A JP2009089878A JP2010244596A5 JP 2010244596 A5 JP2010244596 A5 JP 2010244596A5 JP 2009089878 A JP2009089878 A JP 2009089878A JP 2009089878 A JP2009089878 A JP 2009089878A JP 2010244596 A5 JP2010244596 A5 JP 2010244596A5
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JP
Japan
Prior art keywords
defective cell
fuse
information
state
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009089878A
Other languages
English (en)
Japanese (ja)
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JP2010244596A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2009089878A priority Critical patent/JP2010244596A/ja
Priority claimed from JP2009089878A external-priority patent/JP2010244596A/ja
Priority to US12/662,040 priority patent/US8238177B2/en
Publication of JP2010244596A publication Critical patent/JP2010244596A/ja
Publication of JP2010244596A5 publication Critical patent/JP2010244596A5/ja
Pending legal-status Critical Current

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JP2009089878A 2009-04-02 2009-04-02 集積回路 Pending JP2010244596A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009089878A JP2010244596A (ja) 2009-04-02 2009-04-02 集積回路
US12/662,040 US8238177B2 (en) 2009-04-02 2010-03-29 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009089878A JP2010244596A (ja) 2009-04-02 2009-04-02 集積回路

Publications (2)

Publication Number Publication Date
JP2010244596A JP2010244596A (ja) 2010-10-28
JP2010244596A5 true JP2010244596A5 (https=) 2012-04-05

Family

ID=42826081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009089878A Pending JP2010244596A (ja) 2009-04-02 2009-04-02 集積回路

Country Status (2)

Country Link
US (1) US8238177B2 (https=)
JP (1) JP2010244596A (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5664204B2 (ja) * 2010-12-15 2015-02-04 富士通株式会社 半導体メモリ
JP6063679B2 (ja) 2012-09-10 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置
KR20150006167A (ko) * 2013-07-08 2015-01-16 에스케이하이닉스 주식회사 반도체 시스템 및 그 리페어 방법
KR20160048584A (ko) * 2014-10-24 2016-05-04 에스케이하이닉스 주식회사 반도체 장치
KR20160138617A (ko) * 2015-05-26 2016-12-06 에스케이하이닉스 주식회사 스마트 셀프 리페어 장치 및 방법
KR20160148347A (ko) * 2015-06-16 2016-12-26 에스케이하이닉스 주식회사 셀프 리페어 장치 및 방법
KR102722985B1 (ko) * 2017-01-11 2024-10-29 에스케이하이닉스 주식회사 이퓨즈 회로
JP2018133764A (ja) * 2017-02-17 2018-08-23 株式会社リコー 冗長構成システム、切替方法、情報処理システムおよびプログラム
KR20220048735A (ko) * 2020-10-13 2022-04-20 삼성전자주식회사 테스트 시간을 줄이는 메모리 장치의 테스트 방법, 메모리 빌트-인 셀프 테스트(mbist) 회로 및 메모리 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550394A (en) * 1993-06-18 1996-08-27 Texas Instruments Incorporated Semiconductor memory device and defective memory cell correction circuit
US5657281A (en) * 1996-03-11 1997-08-12 Cirrus Logic, Inc. Systems and methods for implementing inter-device cell replacements
JP2002109899A (ja) * 2000-07-26 2002-04-12 Mitsubishi Electric Corp 半導体記憶装置およびそれを備える半導体集積回路装置
JP2002150789A (ja) * 2000-11-09 2002-05-24 Hitachi Ltd 不揮発性半導体記憶装置
JP2003196995A (ja) * 2001-12-26 2003-07-11 Mitsubishi Electric Corp 半導体記憶装置およびその試験方法
JP2004234729A (ja) * 2003-01-29 2004-08-19 Renesas Technology Corp 半導体記憶装置
JP2007323726A (ja) 2006-05-31 2007-12-13 Matsushita Electric Ind Co Ltd 半導体装置

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