JP2010199386A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010199386A JP2010199386A JP2009044037A JP2009044037A JP2010199386A JP 2010199386 A JP2010199386 A JP 2010199386A JP 2009044037 A JP2009044037 A JP 2009044037A JP 2009044037 A JP2009044037 A JP 2009044037A JP 2010199386 A JP2010199386 A JP 2010199386A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
【解決手段】層間絶縁膜を挟んで互いに対向して形成された上下の配線路の一方の配線幅を大、他方の配線幅を小とし、且つ、同一の配線層において互いに隣接する配線路の配線幅を大小交互に形成する。
【選択図】図1
Description
図1(a)は本実施例による半導体装置100の断面図である。以下、図1(a)を参照しつつ、半導体装置100の構成について説明する。
図4(a)は本実施例による半導体装置200の断面図である。第1の実施例は、2つの配線層が積層されてなる半導体装置100であるが、図4(a)に示す如く3つの配線層が積層されてなる半導体装置200にも適用可能である。
2 表面絶縁層
3 保護膜
4 第1絶縁層
5 第1下地金属層
6−1、6−2 第1配線路
7 第2絶縁層
8 第2下地金属層
9−1、9−2 第2配線路
10 封止層
11 第3絶縁層
12 第3下地金属層
13−1、13−2 第3配線路
14 半導体回路
15 電極パッド
16 電極ポスト
17 外部電極
100、110、200、210 半導体装置
300 WCSP
wb1、wb2、wm1、wm2、wt1、wt2 配線幅
pc1、pc2 配線間ピッチ
Claims (5)
- 半導体基板上に交互に積層された複数の絶縁層及び複数の配線層を含む半導体装置であって、
前記絶縁層の1を挟んで積層された2つの配線層のうちの上側の配線層に形成されている第1上側配線路の配線幅が、下側の配線層に前記第1上側配線路と対向して形成されている第1下側配線路の配線幅よりも小さく、且つ、
前記第1上側配線路に隣接して形成されている第2上側配線路の配線幅が、前記第1下側配線路に隣接し且つ前記第2上側配線路と対向して形成されている第2下側配線路の配線幅よりも大きいことを特徴とする半導体装置。 - 前記第2上側配線路の配線幅が前記第1上側配線路の配線幅よりも大きく且つ前記第2下側配線路の配線幅が前記第1下側配線路の配線幅よりも小さいことを特徴とする請求項1に記載の半導体装置。
- 前記第1下側配線路と前記第2下側配線路との間のピッチは、前記第1下側配線路の配線幅と前記第2下側配線路の配線幅との和の1〜2倍であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第1上側配線路と前記第2上側配線路との間のピッチは、前記第1上側配線路の配線幅と前記第2上側配線路の配線幅との和の1〜2倍であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記絶縁層及び前記配線層はそれぞれ3以上であることを特徴とする請求項1又は2に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009044037A JP5465894B2 (ja) | 2009-02-26 | 2009-02-26 | 半導体装置 |
US12/659,102 US8581408B2 (en) | 2009-02-26 | 2010-02-25 | Semiconductor device |
US14/052,064 US9129966B2 (en) | 2009-02-26 | 2013-10-11 | Semiconductor device |
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JP2009044037A JP5465894B2 (ja) | 2009-02-26 | 2009-02-26 | 半導体装置 |
Publications (2)
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JP2010199386A true JP2010199386A (ja) | 2010-09-09 |
JP5465894B2 JP5465894B2 (ja) | 2014-04-09 |
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JP2009044037A Active JP5465894B2 (ja) | 2009-02-26 | 2009-02-26 | 半導体装置 |
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US (2) | US8581408B2 (ja) |
JP (1) | JP5465894B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014183135A (ja) * | 2013-03-18 | 2014-09-29 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2019067859A (ja) * | 2017-09-29 | 2019-04-25 | 大日本印刷株式会社 | 貫通電極基板 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5819218B2 (ja) * | 2012-02-23 | 2015-11-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2018182223A (ja) * | 2017-04-20 | 2018-11-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5726454A (en) * | 1980-07-24 | 1982-02-12 | Nec Corp | Integrated circuit device |
JPS62104052A (ja) * | 1985-10-31 | 1987-05-14 | Nec Corp | 半導体装置 |
JPS6354750A (ja) * | 1986-08-25 | 1988-03-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH05144809A (ja) * | 1991-11-15 | 1993-06-11 | Nec Corp | 半導体装置 |
JPH0613590A (ja) * | 1992-06-26 | 1994-01-21 | Nec Corp | 半導体集積回路装置 |
JPH10270445A (ja) * | 1997-03-27 | 1998-10-09 | Yamaha Corp | 半導体装置とその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06136590A (ja) | 1992-10-27 | 1994-05-17 | Matsushita Electric Works Ltd | 回転式めっき装置 |
US7538433B2 (en) * | 2005-06-16 | 2009-05-26 | Panasonic Corporation | Semiconductor device |
US7851921B2 (en) * | 2006-07-31 | 2010-12-14 | Sanyo Electric Co., Ltd. | Device mounting board having multiple circuit substrates, and semiconductor module with the device mounting board |
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2009
- 2009-02-26 JP JP2009044037A patent/JP5465894B2/ja active Active
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2010
- 2010-02-25 US US12/659,102 patent/US8581408B2/en active Active
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2013
- 2013-10-11 US US14/052,064 patent/US9129966B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5726454A (en) * | 1980-07-24 | 1982-02-12 | Nec Corp | Integrated circuit device |
JPS62104052A (ja) * | 1985-10-31 | 1987-05-14 | Nec Corp | 半導体装置 |
JPS6354750A (ja) * | 1986-08-25 | 1988-03-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH05144809A (ja) * | 1991-11-15 | 1993-06-11 | Nec Corp | 半導体装置 |
JPH0613590A (ja) * | 1992-06-26 | 1994-01-21 | Nec Corp | 半導体集積回路装置 |
JPH10270445A (ja) * | 1997-03-27 | 1998-10-09 | Yamaha Corp | 半導体装置とその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014183135A (ja) * | 2013-03-18 | 2014-09-29 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2019067859A (ja) * | 2017-09-29 | 2019-04-25 | 大日本印刷株式会社 | 貫通電極基板 |
JP7098902B2 (ja) | 2017-09-29 | 2022-07-12 | 大日本印刷株式会社 | 貫通電極基板 |
Also Published As
Publication number | Publication date |
---|---|
US9129966B2 (en) | 2015-09-08 |
US20140042635A1 (en) | 2014-02-13 |
JP5465894B2 (ja) | 2014-04-09 |
US8581408B2 (en) | 2013-11-12 |
US20100213615A1 (en) | 2010-08-26 |
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