JP2010171944A - 発振回路 - Google Patents
発振回路 Download PDFInfo
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- JP2010171944A JP2010171944A JP2009271972A JP2009271972A JP2010171944A JP 2010171944 A JP2010171944 A JP 2010171944A JP 2009271972 A JP2009271972 A JP 2009271972A JP 2009271972 A JP2009271972 A JP 2009271972A JP 2010171944 A JP2010171944 A JP 2010171944A
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- 230000010355 oscillation Effects 0.000 title claims abstract description 50
- 230000003111 delayed effect Effects 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 9
- 230000011664 signaling Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 15
- 230000008707 rearrangement Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 238000005070 sampling Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000010076 replication Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
Abstract
【解決手段】発振回路200は、ゲート発振器201と較正回路202とを備える。ゲート発振器201は、制御信号Sctrlに従って発振信号を生成し、ゲート信号SGを受信して、発振信号のエッジとゲート信号SGのエッジを配列させる。較正回路202は、ゲート発振器201に結合されて、第一クロック信号と第二クロック信号を受信し、第一クロック信号と第二クロック信号に従って、ゲート発振器201の配列操作を検出し、検出された配列操作に従って、制御信号Sctrlを生成する。
【選択図】図2
Description
発振回路200
ゲート発振器201
較正回路202
発振回路300
ゲート発振器301
較正回路302
モニター303
フィードバックコントローラー304
遅延ユニット305
発振回路400
ゲート発振器401
較正回路402
モニター403
フィードバックコントローラー404
BMCDR500
ゲート発振器501
較正回路502
モニター503
カウンター504
コンバータ505
エッジ検出器506
DFF508
位相再配列検出器700
Dフリップフロップ(DEF)701と702
クロック信号CK1_AとCK2_A
第一クロック信号CK1
第二クロック信号CK2
表示信号SInd
制御信号Sctrl
フィードバック信号Sctrl
Claims (4)
- 制御信号に従って発振信号を生成し、ゲート信号を受信して、前記発振信号のエッジと前記ゲート信号のエッジを配列させるゲート発振器と、
前記ゲート発振器に結合されて、第一クロック信号と第二クロック信号を受信し、前記第一クロック信号と前記第二クロック信号に従って前記ゲート発振器の配列操作を検出し、検出された配列操作に従って制御信号を生成する較正回路とを備えることを特徴とする発振回路。 - 制御信号に従って発振信号を生成するゲート発振器と、
前記ゲート発振器に結合され、第一クロック信号と第二クロック信号を受信し、前記第一、第二クロック信号に従って前記発振信号の周波数又は期間の変化を検出し、検出された変化に従って前記制御信号を生成する較正回路とを備え、
少なくとも一つの前記第一、第二クロック信号は前記発振信号から派生し、前記第二クロック信号は前記第一クロック信号の遅延バージョンであることを特徴とする発振回路。 - 制御信号に従って操作するゲート発振器と、
前記ゲート発振器に結合され、前記ゲート発振器から第一クロック信号と第二クロック信号を受信し、前記第一、第二クロック信号に従って前記制御信号を生成する較正回路とを備えることを特徴とする発振回路。 - 制御信号に従って操作するゲート発振器と、
前記ゲート発振器に結合され、前記ゲート発振器から第一クロック信号と前記第一クロック信号の遅延バージョンである第二クロック信号を受信し、前記第一、第二クロック信号に従って前記制御信号を生成する較正回路とを備えることを特徴とする発振回路。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14576509P | 2009-01-20 | 2009-01-20 | |
US61/145,765 | 2009-01-20 | ||
US12/512,247 | 2009-07-30 | ||
US12/512,247 US8258830B2 (en) | 2009-01-20 | 2009-07-30 | Methods for calibrating gated oscillator and oscillator circuit utilizing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010171944A true JP2010171944A (ja) | 2010-08-05 |
JP5093216B2 JP5093216B2 (ja) | 2012-12-12 |
Family
ID=42336456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009271972A Expired - Fee Related JP5093216B2 (ja) | 2009-01-20 | 2009-11-30 | 発振回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8258830B2 (ja) |
JP (1) | JP5093216B2 (ja) |
CN (1) | CN101795125B (ja) |
TW (1) | TWI401888B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8898511B2 (en) | 2010-06-24 | 2014-11-25 | International Business Machines Corporation | Homogeneous recovery in a redundant memory system |
US8631271B2 (en) * | 2010-06-24 | 2014-01-14 | International Business Machines Corporation | Heterogeneous recovery in a redundant memory system |
WO2013006231A2 (en) | 2011-07-01 | 2013-01-10 | Rambus Inc. | Low-latency, frequency-agile clock multiplier |
US8643409B2 (en) | 2011-07-01 | 2014-02-04 | Rambus Inc. | Wide-range clock multiplier |
TWI495318B (zh) * | 2012-08-30 | 2015-08-01 | Realtek Semiconductor Corp | 時脈與資料回復電路以及時脈與資料回復方法 |
EP2944022B1 (en) * | 2013-01-08 | 2019-12-25 | Rambus Inc. | Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator |
JP6032082B2 (ja) * | 2013-03-25 | 2016-11-24 | 富士通株式会社 | 受信回路及び半導体集積回路 |
CN104518839B (zh) * | 2013-09-30 | 2017-06-27 | 华为技术有限公司 | 频偏检测方法和装置 |
ES2828711T3 (es) | 2014-04-21 | 2021-05-27 | Aclaris Therapeutics Inc | Formulaciones de peróxido y métodos y aplicadores para usar las mismas |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09119962A (ja) * | 1995-10-24 | 1997-05-06 | Advantest Corp | 可変遅延回路の遅延時間測定装置 |
WO2007072731A1 (ja) * | 2005-12-20 | 2007-06-28 | Advantest Corporation | 発振回路、試験装置、及び電子デバイス |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3991382A (en) * | 1974-06-11 | 1976-11-09 | Sansui Electric Co., Ltd. | Oscillation frequency control device for a local oscillator |
US4635280A (en) | 1985-05-28 | 1987-01-06 | Harris Corporation | Bit synchronizer for decoding data |
US5164966A (en) | 1991-03-07 | 1992-11-17 | The Grass Valley Group, Inc. | Nrz clock and data recovery system employing phase lock loop |
US5548249A (en) * | 1994-05-24 | 1996-08-20 | Matsushita Electric Industrial Co., Ltd. | Clock generator and method for generating a clock |
DE4443790C1 (de) * | 1994-12-08 | 1996-04-18 | Sgs Thomson Microelectronics | Verfahren und Vorrichtung zur Phasensynchronisation mit einem RDS-Signal |
US5815043A (en) * | 1997-02-13 | 1998-09-29 | Apple Computer, Inc. | Frequency controlled ring oscillator having by passable stages |
US6094105A (en) * | 1998-05-29 | 2000-07-25 | Intel Corporation | Oscillator with digital frequency control |
US6140880A (en) * | 1998-09-24 | 2000-10-31 | Cypress Semiconductor Corp. | Circuits, architectures and methods for detecting and correcting excess oscillator frequencies |
CA2250538A1 (en) * | 1998-10-30 | 2000-04-30 | Mosaid Technologies Incorporated | Duty cycle regulator |
US6084483A (en) * | 1999-03-10 | 2000-07-04 | Lexar Media, Inc. | Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit |
US6928128B1 (en) | 1999-05-03 | 2005-08-09 | Rambus Inc. | Clock alignment circuit having a self regulating voltage supply |
US6337601B1 (en) * | 1999-12-08 | 2002-01-08 | Ericsson Inc. | Ring oscillator with jitter reset |
US6809605B2 (en) * | 2002-01-10 | 2004-10-26 | Fujitsu Limited | Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit |
JP4158465B2 (ja) | 2002-09-10 | 2008-10-01 | 日本電気株式会社 | クロック再生装置、および、クロック再生装置を用いた電子機器 |
US6960950B2 (en) * | 2003-03-25 | 2005-11-01 | Intel Corporation | Circuit and method for generating a clock signal |
US7126396B1 (en) * | 2003-07-16 | 2006-10-24 | National Semiconductor Corporation | System for clock duty cycle stabilization |
KR100689832B1 (ko) * | 2005-06-21 | 2007-03-08 | 삼성전자주식회사 | 위상 동기 루프 및 방법 |
US7391275B2 (en) * | 2005-07-18 | 2008-06-24 | Seiko Epson Corporation | Circuits and methods for a ring oscillator with adjustable delay and/or resonator tank stage |
US7667544B2 (en) | 2006-01-12 | 2010-02-23 | Yokogawa Electric Corporation | Clock reproducing apparatus |
US20080001677A1 (en) * | 2006-05-22 | 2008-01-03 | Udi Shaked | Ring oscillator clock |
KR100847687B1 (ko) * | 2006-10-20 | 2008-07-23 | (주)에프씨아이 | 주파수합성기 및 주파수조절방법 |
KR100817081B1 (ko) | 2007-01-11 | 2008-03-26 | 삼성전자주식회사 | 동기 실패를 방지하는 장치 및 그에 따른 지연 동기 루프 |
-
2009
- 2009-07-30 US US12/512,247 patent/US8258830B2/en active Active
- 2009-11-30 JP JP2009271972A patent/JP5093216B2/ja not_active Expired - Fee Related
-
2010
- 2010-01-05 TW TW099100049A patent/TWI401888B/zh not_active IP Right Cessation
- 2010-01-12 CN CN2010100011169A patent/CN101795125B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09119962A (ja) * | 1995-10-24 | 1997-05-06 | Advantest Corp | 可変遅延回路の遅延時間測定装置 |
WO2007072731A1 (ja) * | 2005-12-20 | 2007-06-28 | Advantest Corporation | 発振回路、試験装置、及び電子デバイス |
Also Published As
Publication number | Publication date |
---|---|
TWI401888B (zh) | 2013-07-11 |
CN101795125B (zh) | 2013-05-01 |
US20100182056A1 (en) | 2010-07-22 |
CN101795125A (zh) | 2010-08-04 |
TW201029329A (en) | 2010-08-01 |
US8258830B2 (en) | 2012-09-04 |
JP5093216B2 (ja) | 2012-12-12 |
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