JP2010147955A - Circuit board including cavity and method of manufacturing the same - Google Patents

Circuit board including cavity and method of manufacturing the same Download PDF

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Publication number
JP2010147955A
JP2010147955A JP2008324910A JP2008324910A JP2010147955A JP 2010147955 A JP2010147955 A JP 2010147955A JP 2008324910 A JP2008324910 A JP 2008324910A JP 2008324910 A JP2008324910 A JP 2008324910A JP 2010147955 A JP2010147955 A JP 2010147955A
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cavity
conductive foil
substrate
lower substrate
upper substrate
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JP2010147955A5 (en
JP4859253B2 (en
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Goro Narita
悟郎 成田
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Element Denshi Kk
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Element Denshi Kk
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Priority to JP2008324910A priority Critical patent/JP4859253B2/en
Priority to TW098107827A priority patent/TWI371993B/en
Priority to CN2009101338368A priority patent/CN101764105B/en
Priority to KR1020090028940A priority patent/KR101074927B1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board having a cavity in which a cavity is configured between the substrates using two substrates, and to provide a method of manufacturing the same. <P>SOLUTION: The circuit board includes: a first circuit pattern 17 formed from a conductive foil 20a on a surface of an upper substrate 11; an adhesive sheet 13 provided on a backside of the upper substrate 11; a second circuit pattern 19 formed from conductive foil 21a on a surface of a lower substrate 12; and a cavity 14 formed, by removing the conductive foil 21b, on a backside of the lower substrate 12, and an insulating layer 34 around the cavity. The adhesive layer 13 on the backside of the upper substrate 11 is adhered with the insulating layer 34 on the backside of the lower substrate 12, and the cavity 14 surrounded with the upper substrate 11, the lower substrate 12 and the insulating layer 34 is formed between both the substrates. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、空洞部を有する回路基板およびその製造方法に関し、特に、２つの基板を用いてその間に空洞部が構成された空洞部を有する回路基板およびその製造方法に関するものである。   The present invention relates to a circuit board having a cavity and a method for manufacturing the same, and more particularly to a circuit board having a cavity having a cavity formed between two substrates and a method for manufacturing the same.

図７にＩＣチップを基板の中に埋め込んだ高密度な実装基板が示されている。   FIG. 7 shows a high-density mounting substrate in which an IC chip is embedded in the substrate.

この実装基板は第１の基板１００、第２の基板２００、第３の基板３００、ＩＣチップ４００、導電性接続部材５００および封止部材６００から構成される。第１の基板１００、第２の基板２００および第３の基板３００はプリント基板であり、所望の配線パターンが形成されている。第１の基板１００および第２の基板２００は貼り合わされ、一方の外表面にはＩＣチップ４００が収容可能な底面積および深さを有する凹部が形成される。ＩＣチップ４００は前記凹部に収容され、半田等の金属バンプよりなる導電性接続部材５００により凹部の底面と接続される。そして機械的強度を保持し、ＩＣチップ４００を保護するためにエポキシ樹脂等の封止部材６００により封止される。その後、第３の基板３００は前記凹部側に積層され、前記凹部を密封した多層のプリント基板が形成される（図８参照）。すなわち第１の基板１００、第２の基板２００および第３の基板３００からなる３層構造の貼り合わせ（積層）多層プリント基板において、中層の第２の基板２００のみに打抜き部７００を形成し、この打抜き部にＩＣチップ４００が埋め込まれている。   The mounting substrate includes a first substrate 100, a second substrate 200, a third substrate 300, an IC chip 400, a conductive connection member 500, and a sealing member 600. The first substrate 100, the second substrate 200, and the third substrate 300 are printed boards, and a desired wiring pattern is formed thereon. The first substrate 100 and the second substrate 200 are bonded together, and a concave portion having a bottom area and a depth that can accommodate the IC chip 400 is formed on one outer surface. The IC chip 400 is accommodated in the recess and is connected to the bottom surface of the recess by a conductive connection member 500 made of a metal bump such as solder. Then, in order to maintain mechanical strength and protect the IC chip 400, it is sealed with a sealing member 600 such as epoxy resin. Thereafter, the third substrate 300 is laminated on the concave portion side to form a multilayer printed board in which the concave portion is sealed (see FIG. 8). That is, in the laminated (laminated) multilayer printed circuit board having a three-layer structure including the first substrate 100, the second substrate 200, and the third substrate 300, the punched portion 700 is formed only on the second substrate 200 in the middle layer. An IC chip 400 is embedded in the punched portion.

また、最近、シリコン（ＭＥＭＳ）マイクと呼ばれるシリコン基板に振動板となるダイアフラムを組み込んだ小型マイクが普及してきた。ＭＥＭＳはMicro-Electro-Mechanical-Systemの略称である。   Recently, a small microphone in which a diaphragm serving as a diaphragm is incorporated in a silicon substrate called a silicon (MEMS) microphone has become widespread. MEMS is an abbreviation for Micro-Electro-Mechanical-System.

図８にシリコン（ＭＥＭＳ）マイクの一例を示す。周囲に残されたシリコン基板５１と、
シリコン基板５１の円形状の貫通孔に貼られている金属膜よりなるダイアフラム５２と、ダイアフラム５２に対向してエアギャップ５３を介してバックプレート電極５４を表面に設けたバックプレート５５と、シリコン基板５１上にダイアフラム５２と接続されたボンディングパッド５６と、バックプレート電極５４と接続されたボンディングパッド５７とが設けられている。 FIG. 8 shows an example of a silicon (MEMS) microphone. A silicon substrate 51 left around,
A diaphragm 52 made of a metal film attached to a circular through-hole of the silicon substrate 51, a back plate 55 provided with a back plate electrode 54 on the surface facing the diaphragm 52 through an air gap 53, and a silicon substrate A bonding pad 56 connected to the diaphragm 52 and a bonding pad 57 connected to the back plate electrode 54 are provided on 51.

ダイアフラム５２の振動をダイアフラム５２とバックプレート電極５４とで形成されるコンデンサの容量の変化で検出し、ＣＭＯＳＩＣで再生する。   The vibration of the diaphragm 52 is detected by a change in the capacitance of the capacitor formed by the diaphragm 52 and the back plate electrode 54, and reproduced by the CMOSIC.

図９に実装構造を説明する。プリント基板６１上にシリコン（ＭＥＭＳ）マイク６２とＣＭＯＳＩＣ６３とを組み込み、全体を箱型のケース６４で収納する。シリコン（ＭＥＭＳ）マイクのダイアフラム５２の近くケース６４には必ず音孔６５が設けられ、外部からの音をダイアフラム５２まで伝達する。ＣＭＯＳＩＣ６３とシリコン（ＭＥＭＳ）マイクとはボンディングワイヤーでプリント基板６１の配線で接続される。
特開平０９−３２１４３８号公報 FIG. 9 illustrates the mounting structure. A silicon (MEMS) microphone 62 and a CMOSIC 63 are incorporated on the printed circuit board 61, and the whole is housed in a box-shaped case 64. A sound hole 65 is always provided in the case 64 near the diaphragm 52 of the silicon (MEMS) microphone, and sounds from the outside are transmitted to the diaphragm 52. The CMOSIC 63 and the silicon (MEMS) microphone are connected to each other by a wiring of the printed circuit board 61 with a bonding wire.
JP 09-32438 A

しかしながら、上述した従来の実装基板では、多層の実装基板を用いてその間に空洞を形成するためには、間に挟まれて基板に打抜き部を形成するのが簡便な方法であるが、打抜き部を形成するには必ず３枚の基板が必要となるため、空洞を有する実装基板の小型化が困難である問題点があった。   However, in the above-described conventional mounting substrate, in order to form a cavity between them using a multilayer mounting substrate, it is a simple method to form a punched portion between the substrates. Since three substrates are necessarily required to form the substrate, there is a problem that it is difficult to reduce the size of the mounting substrate having a cavity.

また、上述したシリコン（ＭＥＭＳ）マイクなどを組み込む場合に音を取り込む音孔が必要となるが、ケースを用いて実装するために実装密度が向上できない問題点があった。   Further, when the above-described silicon (MEMS) microphone or the like is incorporated, a sound hole for capturing sound is required, but there is a problem that the mounting density cannot be improved because the mounting is performed using the case.

本発明はかかる問題点に鑑みてなされ、上基板と、前記上基板の表面の前記導電箔から形成した任意の第１の回路パターンと、前記上基板の裏面に設けた接着シートと、下基板と、前記下基板の表面の前記導電箔から形成した任意の第２の回路パターンと、前記下基板の裏面の前記導電箔を除去して形成した空洞とその周囲に設けた絶縁層と、前記上基板の裏面の前記接着シートと前記下基板の裏面の前記絶縁層とを接着して、前記上基板、前記下基板および前記絶縁層とで囲まれる空洞部と、前記上基板の前記第1の回路パターンと前記下基板の前記第２の回路パターンとを接続するスルーホール電極とを具備することを特徴とする。
また、本発明に依れば、前記空洞部に前記上基板あるいは前記下基板を貫通する貫通孔を設けたことを特徴とする。 The present invention has been made in view of such problems, an upper substrate, an arbitrary first circuit pattern formed from the conductive foil on the surface of the upper substrate, an adhesive sheet provided on the back surface of the upper substrate, and a lower substrate An arbitrary second circuit pattern formed from the conductive foil on the surface of the lower substrate, a cavity formed by removing the conductive foil on the back surface of the lower substrate, and an insulating layer provided around the cavity, Adhering the adhesive sheet on the back surface of the upper substrate and the insulating layer on the back surface of the lower substrate, the cavity surrounded by the upper substrate, the lower substrate and the insulating layer, and the first of the upper substrate And a through-hole electrode for connecting the second circuit pattern of the lower substrate to the second circuit pattern of the lower substrate.
According to the invention, a through-hole penetrating the upper substrate or the lower substrate is provided in the hollow portion.

更に、本発明に依れば、前記貫通孔上に回路素子のダイアフラムを配置することを特徴とする。   Furthermore, according to the present invention, a diaphragm of a circuit element is disposed on the through hole.

本発明の製造方法に依れば、両面に導電箔を設けた上基板を準備する工程と、前記上基板の一方の前記導電箔をエッチングして予定の空洞パターンを形成する工程と、両面に導電箔を設けた下基板を準備する工程と、前記下基板の一方の前記導電箔をエッチングして予定の空洞部となる部分を残す工程と、前記下基板の前記予定の空洞部となる部分の前記導電箔の周囲を絶縁層で埋め、前記予定の空洞部となる部分の前記導電箔をエッチングして前記空洞部を形成する工程と、前記上基板の前記予定の空洞パターンの周囲に接着層を付着する工程と、前記上基板と下基板とを前記接着層で貼り合わせて前記空洞部を形成する工程とを具備することを特徴とする。   According to the manufacturing method of the present invention, a step of preparing an upper substrate provided with conductive foil on both surfaces, a step of etching one conductive foil of the upper substrate to form a predetermined cavity pattern, A step of preparing a lower substrate provided with a conductive foil; a step of etching one of the conductive foils of the lower substrate to leave a portion to be a predetermined cavity; and a portion to be the predetermined cavity of the lower substrate A step of filling the periphery of the conductive foil with an insulating layer, etching the conductive foil in a portion to be the predetermined cavity, and forming the cavity, and bonding the periphery of the predetermined cavity pattern on the upper substrate A step of attaching a layer; and a step of bonding the upper substrate and the lower substrate with the adhesive layer to form the cavity.

また、本発明の製造方法に依れば、両面に導電箔を設けた上基板を準備する工程と、前記上基板の一方の前記導電箔をエッチングして予定の空洞パターンを形成する工程と、両面に導電箔を設けた下基板を準備する工程と、前記下基板の一方の前記導電箔をエッチングして予定の空洞部となる部分を残す工程と、前記下基板の前記予定の空洞部となる部分の前記導電箔の周囲を絶縁層で埋め、前記予定の空洞部となる部分の前記導電箔をエッチングして前記空洞部を形成する工程と、前記上基板の前記予定の空洞パターンの前記導電箔の周囲に接着層を付着する工程と、前記上基板と下基板とを前記接着層で貼り合わせて前記空洞部を形成する工程と、前記上基板および下基板を貫通するスルーホールを形成し、スルーホール電極を形成する工程と、前記上基板および下基板の外部に面する他方の導電箔をエッチングして前記上基板に第１の回路パターンを前記下基板に第２の回路パターンを形成する工程と、前記上基板あるいは下基板より前記空洞部まで到達する貫通孔を形成する工程とを具備することを特徴とする。   Further, according to the manufacturing method of the present invention, a step of preparing an upper substrate provided with conductive foil on both surfaces, a step of etching one of the conductive foils of the upper substrate to form a predetermined cavity pattern, A step of preparing a lower substrate provided with conductive foil on both sides, a step of etching one of the conductive foils of the lower substrate to leave a portion to be a predetermined cavity, and the predetermined cavity of the lower substrate; Filling the periphery of the portion of the conductive foil with an insulating layer and etching the portion of the conductive foil to be the predetermined cavity to form the cavity; and the predetermined cavity pattern of the upper substrate A step of attaching an adhesive layer around the conductive foil, a step of bonding the upper substrate and the lower substrate with the adhesive layer to form the cavity, and forming a through hole penetrating the upper substrate and the lower substrate And forming a through-hole electrode Etching the other conductive foil facing the outside of the upper substrate and the lower substrate to form a first circuit pattern on the upper substrate and a second circuit pattern on the lower substrate; and Alternatively, the method includes a step of forming a through hole reaching the cavity from the lower substrate.

更に、本発明の製造方法に依れば、前述した工程に続き、前記第１の回路パターンに回路素子を配置する工程を具備することを特徴とする。   Furthermore, according to the manufacturing method of the present invention, a step of arranging a circuit element in the first circuit pattern is provided following the step described above.

更に、本発明の製造方法に依れば、前記回路素子としてダイアフラムを有する半導体素子を用いることを特徴とする。   Furthermore, according to the manufacturing method of the present invention, a semiconductor element having a diaphragm is used as the circuit element.

本発明に依れば、上基板と下基板の間に挟まれた導電箔を用いて空洞部を実現した回路基板が提供できる。従って、少なくとも２枚の基板のみで空洞部を形成でき、回路基板の小型化を可能にできる。そして、両基板の外側に面する導電箔にはそれぞれ回路パターンが形成され、回路素子の両面実装が行える。   According to the present invention, it is possible to provide a circuit board in which a hollow portion is realized by using a conductive foil sandwiched between an upper substrate and a lower substrate. Therefore, the cavity can be formed with only at least two substrates, and the circuit board can be miniaturized. A circuit pattern is formed on each of the conductive foils facing the outside of both substrates, and circuit elements can be mounted on both sides.

また、本発明では、空洞部を下基板の導電箔の空洞パターンを選ぶことで任意の形状の空洞部が形成でき、任意の位置に形成でき、そのサイズは導電箔の厚みで選択できる。   In the present invention, the cavity can be formed in any shape by selecting the cavity pattern of the conductive foil of the lower substrate, can be formed in any position, and the size can be selected by the thickness of the conductive foil.

更に、本発明では、空洞部は導電箔のエッチングで加工ができ、機械加工を必要としない。   Furthermore, in the present invention, the cavity can be processed by etching the conductive foil, and no machining is required.

更に、本発明では、上基板の表面の導電箔および下基板の表面の導電箔に第１の回路パターンおよび第２の回路パターンを設けるので、上基板と下基板を貼り合わせた回路基板は両面基板と同様に回路素子などの実装が行える。   Furthermore, in the present invention, the first circuit pattern and the second circuit pattern are provided on the conductive foil on the surface of the upper substrate and the conductive foil on the surface of the lower substrate. Circuit elements can be mounted in the same way as a substrate.

更に、本発明では、従来のＭＥＭＳ回路素子の実装では必ず必要とされた音孔を形成するケースは完全に不要となり、著しく実装密度を向上できる。   Furthermore, in the present invention, the case of forming a sound hole that is absolutely necessary for mounting conventional MEMS circuit elements is completely unnecessary, and the mounting density can be remarkably improved.

本発明の製造方法に依れば、両面に導電箔を有する上基板と下基板を用いることで導電箔のエッチングにより空洞部を両基板の間に形成できる。これにより回路基板は２枚の基板で空洞部を実現できるのである。   According to the manufacturing method of the present invention, by using an upper substrate and a lower substrate having conductive foils on both sides, a cavity can be formed between both substrates by etching the conductive foil. As a result, the circuit board can realize the hollow portion with two substrates.

また、本発明の製造方法に依れば、空洞部は下基板の裏面の導電箔のエッチングで形成されるので、ルーター等の機械的な研削が不要になり、エッチングという化学的処理なのでその形状も任意に形成され、大きさも下基板の裏面の導電箔の厚みに依存する。   Further, according to the manufacturing method of the present invention, since the cavity is formed by etching the conductive foil on the back surface of the lower substrate, mechanical grinding of a router or the like is unnecessary, and the shape thereof is a chemical treatment called etching. Are arbitrarily formed, and the size also depends on the thickness of the conductive foil on the back surface of the lower substrate.

更に、本発明の製造方法に依れば、上基板と下基板とは接着層で強固に貼り付けられるために、回路基板は上基板の表面の導電箔と下基板の表面の導電箔とで両面基板としての処理が行え、その処理の際に空洞部への処理液等の侵入は完全に排除できる。   Furthermore, according to the manufacturing method of the present invention, since the upper substrate and the lower substrate are firmly bonded with an adhesive layer, the circuit board is composed of a conductive foil on the surface of the upper substrate and a conductive foil on the surface of the lower substrate. Processing as a double-sided substrate can be performed, and intrusion of processing liquid or the like into the cavity can be completely eliminated during the processing.

更に、本発明の製造方法に依れば、空洞部は完全に上基板と下基板の間に挟まれて形成できるために、最終の工程で初めて貫通孔を設けて空洞部と外気とを連絡でき、空洞部を最終工程まで異物の侵入から保護できる。   Furthermore, according to the manufacturing method of the present invention, since the cavity can be formed by being completely sandwiched between the upper substrate and the lower substrate, a through hole is provided for the first time in the final process to communicate the cavity with the outside air. And the cavity can be protected from entry of foreign matter until the final process.

以下に、本発明における実施の形態について、図１を参照にして詳細に説明する。   Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.

まず、図１は本発明の空洞部を有する回路基板の断面図を示す。   First, FIG. 1 shows a sectional view of a circuit board having a cavity of the present invention.

空洞部を有する回路基板１０は、上基板１１、下基板１２、接着層１３、空洞部１４、スルーホール電極１５ａ、１５ｂ、および貫通孔１６ａ、１６ｂから構成される。   The circuit board 10 having a cavity portion includes an upper substrate 11, a lower substrate 12, an adhesive layer 13, a cavity portion 14, through-hole electrodes 15a and 15b, and through holes 16a and 16b.

上基板１１は、両表面に導電箔２０ａ、２０ｂを貼り付けたガラスエポキシ基板である。裏面の導電箔２０ｂの任意の位置には、空洞部と同じ形状の空洞パターンの導電箔２０ｂをエッチングして形成する。空洞パターンの導電箔２０ｂの周囲は接着層１３となるボンディングシート等で囲まれる。   The upper substrate 11 is a glass epoxy substrate having conductive foils 20a and 20b attached to both surfaces. The conductive foil 20b having a cavity pattern having the same shape as the cavity is formed by etching at an arbitrary position of the conductive foil 20b on the back surface. The periphery of the conductive foil 20b having the hollow pattern is surrounded by a bonding sheet or the like serving as the adhesive layer 13.

表面の導電箔２０ａは、第１の回路パターン１７を有し、第１の回路パターン１７は露光現像、エッチングにより形成される。   The conductive foil 20a on the surface has a first circuit pattern 17, and the first circuit pattern 17 is formed by exposure development and etching.

下基板１２は、両表面に導電箔２１ａ、２１ｂを貼り付けたガラスエポキシ基板である。裏面の導電箔２１ｂは、まず、空洞部と同じ形状の空洞パターンの導電箔２１ｂをエッチングして形成し、その周囲を絶縁物であるアンダーコート樹脂３４などで埋めて、それから空洞パターンの導電箔２１ｂをエッチング除去して空洞部１４を形成している。   The lower substrate 12 is a glass epoxy substrate having conductive foils 21a and 21b attached to both surfaces. The conductive foil 21b on the back surface is formed by first etching the conductive foil 21b having the same shape as the cavity, and filling the periphery with an undercoat resin 34 or the like that is an insulator, and then the conductive foil having the hollow pattern. The cavity 14 is formed by etching away 21b.

表面の導電箔２１ａは、第２の回路パターン１９を有し、第２の回路パターン１９は露光現像、エッチングにより形成される。   The conductive foil 21a on the surface has a second circuit pattern 19, and the second circuit pattern 19 is formed by exposure development and etching.

接着層１３は、ガラスクロスにエポキシ系樹脂を半硬化させたスーパーボンディングシート(商品名)を用いて、両基板１１，１２の裏面同士を貼り合わせて１つの回路基板となる。   The adhesive layer 13 uses a super bonding sheet (trade name) obtained by semi-curing an epoxy resin on a glass cloth, and the back surfaces of both the substrates 11 and 12 are bonded together to form one circuit board.

空洞部１４は、下基板１２の裏面に形成された空洞パターンの導電箔２１ｂをエッチング除去してできた空洞とそれを囲むアンダーコート樹脂３４と上基板１１の裏面の空洞部と同じ形状の空洞パターンの導電箔２０ｂとで囲まれた空間で形成される。なお、空洞パターンの導電箔２０ｂは除去されて上基板１１の表面が露出する場合もある。   The cavity 14 has the same shape as the cavity formed by etching away the conductive foil 21b having a cavity pattern formed on the back surface of the lower substrate 12, the surrounding undercoat resin 34, and the cavity on the back surface of the upper substrate 11. It is formed in a space surrounded by the conductive foil 20b of the pattern. The conductive foil 20b having the hollow pattern may be removed to expose the surface of the upper substrate 11.

スルーホール電極１５ａ、１５ｂは、上基板１１、下基板１２および接着層１３を貫通するスルーホール１８ａ、１８ｂを形成し、スルーホールメッキ処理を行った電極である。ここでは、図示したごとく、回路基板１０の両端に２つ形成される。スルーホール電極１５ａ、１５ｂは第１の回路パターン１７、第２の回路パターン１９の所望個所を電気的に接続する。   The through-hole electrodes 15a and 15b are electrodes in which through-holes 18a and 18b penetrating the upper substrate 11, the lower substrate 12, and the adhesive layer 13 are formed and through-hole plating is performed. Here, two are formed at both ends of the circuit board 10 as illustrated. Through-hole electrodes 15 a and 15 b electrically connect desired portions of the first circuit pattern 17 and the second circuit pattern 19.

貫通孔１６ａ、１６ｂは、上基板１１あるいは下基板１２の表面から空洞部１４の両端に対してＮＣ工作機で形成された穴である。貫通孔１６ａ、１６ｂは上基板１１あるいは下基板１２のみ形成されてもいいし、上基板１１と下基板１２にそれぞれ分けて設けても良い。   The through holes 16 a and 16 b are holes formed by an NC machine tool from the surface of the upper substrate 11 or the lower substrate 12 to both ends of the cavity portion 14. The through holes 16a and 16b may be formed only on the upper substrate 11 or the lower substrate 12, or may be provided separately on the upper substrate 11 and the lower substrate 12, respectively.

なお、空洞部１４はＭＥＭＳマイクロフォンの音孔としての利用が考えられるが、ＭＥＭＳ非接触温度センサなどの検出孔としての利用も可能である。   The cavity 14 can be used as a sound hole for a MEMS microphone, but can also be used as a detection hole for a MEMS non-contact temperature sensor or the like.

次に、図２を具体化された回路基板を説明する底面図および上面図である。   Next, FIG. 2 is a bottom view and a top view for explaining a circuit board embodying FIG.

図２（Ａ）は、下基板１２の表面の導電箔２１ａで形成した第２の回路パターン１９を示している。４隅に貴金属メッキ層からなるＡ、Ｂ、Ｃ、Ｄの外付電極を有し、中央に斜め方向に示した点線が本発明の空洞部１４である。黒く塗られた４つの丸はスルーホール電極１５ａ、１５ｂ(残りの２つは符号なし)である。   FIG. 2A shows a second circuit pattern 19 formed by the conductive foil 21 a on the surface of the lower substrate 12. A hollow portion 14 of the present invention is a dotted line having A, B, C, and D external electrodes made of a noble metal plating layer at the four corners and shown obliquely at the center. The four circles painted black are through-hole electrodes 15a and 15b (the remaining two are unsigned).

図２（Ｂ）は、上基板１１の表面の導電箔２０ａで形成した第１の回路パターン１７を示している。黒く塗られた４つの丸はスルーホール電極１５ａ、１５ｂ(残りの２つは符号なし)である。黒く塗られた４つの丸はスルーホール電極１５ａ、１５ｂ(残りの２つは符号なし)であり、Ａ、Ｂ、Ｃ、Ｄの外付電極に接続されている。中央に斜め方向に示した点線が本発明の空洞部１４である。反対の面から見るために図２（Ａ）と直交方向に傾斜して見える。   FIG. 2B shows the first circuit pattern 17 formed of the conductive foil 20 a on the surface of the upper substrate 11. The four circles painted black are through-hole electrodes 15a and 15b (the remaining two are unsigned). The four circles painted in black are through-hole electrodes 15a and 15b (the remaining two are unsigned) and are connected to A, B, C, and D external electrodes. The dotted line shown in the oblique direction at the center is the cavity 14 of the present invention. Since it is viewed from the opposite side, it appears to be inclined in the direction orthogonal to FIG.

また、中央部の貫通孔１６ａ上にはダイアフラムを有するＭＥＭＳ等の回路素子２３がダイアフラムを貫通孔１６ａに対向させて固着され、回路素子２３の各ボンディングパッド２４と第１の回路パターン１７に設けた各接続電極２５とをボンディングワイヤーで接続する。   Further, a circuit element 23 such as a MEMS having a diaphragm is fixed on the through hole 16a in the central portion so that the diaphragm faces the through hole 16a, and is provided in each bonding pad 24 and the first circuit pattern 17 of the circuit element 23. Each connection electrode 25 is connected with a bonding wire.

このような構造では回路基板１０の周辺に設けた貫通孔１６ｂから集音して、空洞部１４を伝播して貫通孔１６ａから回路素子２３のダイアフラムに伝達される。なお、ダイアフラムについては図８で説明するものと同じである。   In such a structure, sound is collected from the through hole 16 b provided around the circuit board 10, propagates through the cavity portion 14, and is transmitted from the through hole 16 a to the diaphragm of the circuit element 23. The diaphragm is the same as that described in FIG.

次に、本発明による空洞部を有する回路基板の製造方法について、図３〜図５を参照して説明する。   Next, a method for manufacturing a circuit board having a cavity according to the present invention will be described with reference to FIGS.

本発明の製造方法は、両面に導電箔を設けた上基板を準備する工程と、前記上基板の一方の前記導電箔をエッチングして予定の空洞パターンを形成する工程と、両面に導電箔を設けた下基板を準備する工程と、前記下基板の一方の前記導電箔をエッチングして予定の空洞部となる部分を残す工程と、前記下基板の前記予定の空洞部となる部分の前記導電箔の周囲を絶縁層で埋め、前記予定の空洞部となる部分の前記導電箔をエッチングして前記空洞部を形成する工程と、前記上基板の前記予定の空洞パターンの周囲に接着層を付着する工程と、前記上基板と下基板とを前記接着層で貼り合わせて前記空洞部を形成する工程とから構成される。   The manufacturing method of the present invention includes a step of preparing an upper substrate provided with conductive foil on both sides, a step of etching one conductive foil on the upper substrate to form a predetermined cavity pattern, and a conductive foil on both sides. A step of preparing the provided lower substrate, a step of etching one of the conductive foils of the lower substrate to leave a portion to be a predetermined cavity, and the conductivity of the portion to be the predetermined cavity of the lower substrate Filling the periphery of the foil with an insulating layer, etching the conductive foil in the portion that becomes the predetermined cavity, and forming the cavity, and attaching an adhesive layer around the predetermined cavity pattern on the upper substrate And a step of bonding the upper substrate and the lower substrate with the adhesive layer to form the cavity.

まず、図３を参照して、上基板１１の製造方法を説明する。   First, a method for manufacturing the upper substrate 11 will be described with reference to FIG.

図３（Ａ）では、上基板１１の両表面に銅などの導電箔２０ａ、２０ｂを貼り付けたガラスエポキシ基板を用意する。導電箔２０ａ、２０ｂは１２μｍの銅箔を用い、上基板１１は０．０６ｍｍの板厚のものを用いる。表面の導電箔２０ａは回路素子を載置する第１の回路パターンを形成するために用いられる。裏面の導電箔２０ｂは空洞パターンを形成し、後述するボンディングシートの加工を行う。なお、上基板１１はガラスエポキシ樹脂以外でも、ＢＴレジン、コンポジット、ガラスポリイミド樹脂あるいは紙フェノール樹脂等のプリント基板材料の中から選択される。ＢＴレジンはＴ成分（トリアジン樹脂）を主成分とし、Ｂ成分（多官能マレイミド化合物）または他の改質用化合物より構成された高耐熱付加重合型熱硬化性樹脂の総称を言う。コンポジットは複数の基板材料を積層したものである。なお、上基板１１にはコーナーに製造工程中の位置出しをするガイド孔３１が設けられる。   3A, a glass epoxy substrate in which conductive foils 20a and 20b such as copper are attached to both surfaces of the upper substrate 11 is prepared. The conductive foils 20a and 20b are made of 12 μm copper foil, and the upper substrate 11 is 0.06 mm thick. The surface conductive foil 20a is used to form a first circuit pattern on which circuit elements are placed. The conductive foil 20b on the back surface forms a cavity pattern and processes the bonding sheet described later. The upper substrate 11 is selected from printed circuit board materials such as BT resin, composite, glass polyimide resin, paper phenol resin, etc., other than glass epoxy resin. BT resin is a general term for a high heat-resistant addition polymerization type thermosetting resin composed mainly of a T component (triazine resin) and composed of a B component (polyfunctional maleimide compound) or another modifying compound. A composite is a laminate of a plurality of substrate materials. The upper substrate 11 is provided with a guide hole 31 at the corner for positioning during the manufacturing process.

図３（Ｂ）では、上基板１１の裏面の導電箔２０ｂは空洞パターンとなる部分をレジスト層３２で選択的に覆い、空洞パターンのパターン形成をする。   In FIG. 3B, the conductive foil 20b on the back surface of the upper substrate 11 selectively covers a portion that becomes a hollow pattern with a resist layer 32, and forms a pattern of the hollow pattern.

図３（Ｃ）では、レジスト層３２をマスクとして裏面の導電箔２０ｂをエッチングして空洞パターンの導電箔２０ｂを残す。空洞パターンの導電箔２０ｂはスルーホール電極の一部となる導電箔２０ｂとともに残される。空洞パターンの導電箔２０ｂの役割は空洞部１４の上面を導電箔２０ｂを残すことで平坦性等により音などの振動を伝播し易くすることと空洞部１４の補強をするためである。   In FIG. 3C, the conductive foil 20b on the back surface is etched using the resist layer 32 as a mask to leave the conductive foil 20b having a cavity pattern. The hollow-pattern conductive foil 20b is left together with the conductive foil 20b which becomes a part of the through-hole electrode. The role of the conductive foil 20b of the cavity pattern is to leave the conductive foil 20b on the upper surface of the cavity portion 14 so that vibration such as sound can be easily propagated due to flatness or the like, and the cavity portion 14 is reinforced.

図３（Ｄ）では、上基板１１の裏面の導電箔２０ｂ側に全面をボンディングシートで覆う。このボンディングシートは接着層１３を作るものである。   In FIG. 3D, the entire surface of the back surface of the upper substrate 11 on the conductive foil 20b side is covered with a bonding sheet. This bonding sheet forms the adhesive layer 13.

図３（Ｅ）では、レーザー加工により空洞パターンの裏面の導電箔２０ｂ上のボンディングシートを選択的に除去し、空洞パターンの導電箔２０ｂの周りの上基板１１を埋める。
なお、本工程ではＣＯ２レーザーを用いて空洞パターンの裏面の導電箔２０ｂ上のボンディングシートを除去するので、導電箔２０ｂの表面が露出される。これによりボンディングシートが空洞部に垂れ下がり空洞部１４を塞いだり、変形することを防止する。 In FIG. 3E, the bonding sheet on the conductive foil 20b on the back surface of the cavity pattern is selectively removed by laser processing to fill the upper substrate 11 around the conductive foil 20b of the cavity pattern.
In this step, since the bonding sheet on the conductive foil 20b on the back surface of the cavity pattern is removed using a CO2 laser, the surface of the conductive foil 20b is exposed. As a result, the bonding sheet hangs down into the cavity and prevents the cavity 14 from being blocked or deformed.

続いて、図４を参照して、下基板１２の製造方法を説明する。   Next, a method for manufacturing the lower substrate 12 will be described with reference to FIG.

図４（Ａ）では、下基板１２の両表面に銅などの導電箔２１ａ、２１ｂを貼り付けたガラスエポキシ基板を用意する。導電箔２１ａ、２１ｂは１８μｍの銅箔を用い、下基板１２は０．１ｍｍの板厚のものを用いる。表面の導電箔２１ａは回路素子等を載置する第２の回路パターンを形成するために用いられる。裏面の導電箔２１ｂは空洞部を形成するために用いられる。なお、下基板１２はガラスエポキシ樹脂以外でも、ＢＴレジン、コンポジット、ガラスポリイミド樹脂あるいは紙フェノール樹脂等のプリント基板材料の中から選択される。ＢＴレジンはＴ成分（トリアジン樹脂）を主成分とし、Ｂ成分（多官能マレイミド化合物）または他の改質用化合物より構成された高耐熱付加重合型熱硬化性樹脂の総称を言う。コンポジットは複数の基板材料を積層したものである。なお、下基板１２も上基板１１と同様にコーナーに製造工程中の位置出しをするガイド孔３１が設けられる。   4A, a glass epoxy substrate in which conductive foils 21a and 21b such as copper are attached to both surfaces of the lower substrate 12 is prepared. The conductive foils 21a and 21b are 18 μm copper foil, and the lower substrate 12 is 0.1 mm thick. The conductive foil 21a on the surface is used to form a second circuit pattern on which circuit elements and the like are placed. The backside conductive foil 21b is used to form a cavity. The lower substrate 12 is selected from printed circuit board materials such as BT resin, composite, glass polyimide resin, paper phenol resin, etc., other than glass epoxy resin. BT resin is a general term for a high heat-resistant addition polymerization type thermosetting resin composed mainly of a T component (triazine resin) and composed of a B component (polyfunctional maleimide compound) or another modifying compound. A composite is a laminate of a plurality of substrate materials. As with the upper substrate 11, the lower substrate 12 is also provided with guide holes 31 at the corners for positioning during the manufacturing process.

図４（Ｂ）では、下基板１２の裏面の導電箔２１ｂは空洞パターンとなる部分をレジスト層 で選択的に覆い、空洞パターンのパターン形成をする。   In FIG. 4B, the conductive foil 21b on the back surface of the lower substrate 12 selectively covers a portion that becomes a cavity pattern with a resist layer, and forms a pattern of the cavity pattern.

図４（Ｃ）では、レジスト層３３をマスクとして裏面の導電箔２１ｂをエッチングして空洞パターンの導電箔２１ｂを残す。   In FIG. 4C, the conductive foil 21b on the back surface is etched using the resist layer 33 as a mask to leave the conductive foil 21b having a cavity pattern.

図４（Ｄ）では、下基板１２の裏面全体にアンダーコート樹脂３４等を厚く塗布し、空洞パターンの導電箔２１ｂを埋める。アンダーコート樹脂３４としてはポリイミド樹脂が最適であり、液状のポリイミド樹脂を滴下してスピンナーで一様に広げて加熱硬化させる。   In FIG. 4D, the undercoat resin 34 or the like is applied thickly on the entire back surface of the lower substrate 12 to fill the conductive foil 21b having the cavity pattern. As the undercoat resin 34, a polyimide resin is optimal, and a liquid polyimide resin is dropped and spread uniformly with a spinner and cured by heating.

図４（Ｅ）では、アンダーコート樹脂３４を裏面の導電箔２１ｂの厚みまで研磨して、裏面の導電箔２１ｂの表面を露出させる。   In FIG. 4E, the undercoat resin 34 is polished to the thickness of the backside conductive foil 21b to expose the surface of the backside conductive foil 21b.

図４（Ｆ）では、露出された裏面の導電箔２１ｂをエッチングして除去し、アンダーコート樹脂で周囲を囲まれた空洞部１４を形成する。すなわち、空洞パターンの裏面の導電箔２１ｂが取り除かれて、そっくり空洞部１４を形成する。   In FIG. 4F, the exposed conductive foil 21b on the back surface is removed by etching, and the cavity 14 surrounded by the undercoat resin is formed. That is, the conductive foil 21b on the back surface of the cavity pattern is removed, and the cavity portion 14 is formed.

従って、空洞部１４は裏面の導電箔２１ｂの空洞パターンにより任意の形状に作れ、たとえば渦巻状、ホーン形状、蛇行形状等が実現できる。また、空洞部１４の厚みは裏面の導電箔２１ｂの厚みに依存するので、この厚みを選択することで任意の厚みに形成できる。   Accordingly, the cavity portion 14 can be formed in an arbitrary shape by the cavity pattern of the conductive foil 21b on the back surface, and for example, a spiral shape, a horn shape, a meandering shape, or the like can be realized. Moreover, since the thickness of the cavity part 14 depends on the thickness of the conductive foil 21b on the back surface, it can be formed to an arbitrary thickness by selecting this thickness.

更に、図５を参照して両基板の貼り合わせ工程を説明する。   Furthermore, the bonding process of both substrates will be described with reference to FIG.

図５（Ａ）では、上基板１１の裏面と下基板１２の裏面とを対向させてガイド孔３１を用いて位置合わせする。   In FIG. 5A, the back surface of the upper substrate 11 and the back surface of the lower substrate 12 are opposed to each other and are aligned using the guide holes 31.

図５（Ｂ）では、上基板１１と下基板１２とを接着層１３により貼り合わせて空洞部１４を形成する。上基板１１と下基板１２とを重ねて油圧プレス機で３〜５ＭＰａで加圧しながら、１６０〜１７０℃で１時間ほどアニールして接着層１３を本硬化させて上基板１１と下基板１２と接着層１３で一体に接着して空洞部１４を有する回路基板を完成させる。   In FIG. 5B, the upper substrate 11 and the lower substrate 12 are bonded together by the adhesive layer 13 to form the cavity portion 14. While the upper substrate 11 and the lower substrate 12 are overlapped and pressed at 3 to 5 MPa with a hydraulic press, annealing is performed at 160 to 170 ° C. for about 1 hour to fully cure the adhesive layer 13, and the upper substrate 11 and the lower substrate 12. The circuit board having the cavity 14 is completed by bonding together with the adhesive layer 13.

図５（Ｃ）では、スルーホール電極１５ａ、１５ｂを形成するためのスルーホール１５がＮＣ工作機を用いてドリル等で上基板１１および下基板１２および接着層１３を貫通して開けられる。   In FIG. 5C, the through hole 15 for forming the through hole electrodes 15a and 15b is opened through the upper substrate 11, the lower substrate 12 and the adhesive layer 13 with a drill or the like using an NC machine tool.

図５（Ｄ）では、スルーホールにスルーホールメッキを用いてスルーホール電極１５ａ、１５ｂを形成する。貼り合わせた上基板１１および下基板１２をパラジウム溶液に浸漬させ、両導電箔２０ａ、２１ａを電極としてスルーホールの内壁に銅の電解メッキし、銅ペーストを充填してスルーホール電極１５ａ、１５ｂを形成する。   In FIG. 5D, through-hole electrodes 15a and 15b are formed using through-hole plating on the through-holes. The bonded upper substrate 11 and lower substrate 12 are immersed in a palladium solution, the inner walls of the through holes are electroplated with the conductive foils 20a and 21a as electrodes, and the copper paste is filled to form the through hole electrodes 15a and 15b. Form.

図５（Ｅ）では、上基板１１および下基板１２の外側に面する導電箔２０ａ、２１ａをレジスト層で被覆し、上基板１１の導電箔２０ａには第１の回路パターン１７のレジスト層を、下基板１２の導電箔２１ａには第２の回路パターン１９のレジスト層を露光現像し、残ったレジスト層をマスクとして導電箔２０ａ、２１ａを同時にエッチングする。この際に、空洞部１４は上基板１１と下基板１２とを接着層１３により密閉されているので、エッチング溶液が空洞部１４に侵入することはない。導電箔２０ａ、２１ａが銅のときはエッチング溶液として塩化第２鉄を用いる。具体的な第１の回路パターン１７および第２の回路パターン１９は図２に示している。   In FIG. 5E, the conductive foils 20a and 21a facing the outside of the upper substrate 11 and the lower substrate 12 are covered with a resist layer, and the resist layer of the first circuit pattern 17 is coated on the conductive foil 20a of the upper substrate 11. Then, the resist layer of the second circuit pattern 19 is exposed and developed on the conductive foil 21a of the lower substrate 12, and the conductive foils 20a and 21a are simultaneously etched using the remaining resist layer as a mask. At this time, since the cavity portion 14 seals the upper substrate 11 and the lower substrate 12 with the adhesive layer 13, the etching solution does not enter the cavity portion 14. When the conductive foils 20a and 21a are copper, ferric chloride is used as an etching solution. Specific first circuit pattern 17 and second circuit pattern 19 are shown in FIG.

最後に、図６を参照して回路基板の最終加工を説明する。   Finally, the final processing of the circuit board will be described with reference to FIG.

図６（Ａ）では、第１の回路パターン１７および第２の回路パターン１９の形成に用いたレジスト層を剥離除去し、新たなレジスト層を被覆して外付電極や回路素子のボンディング電極等の表面処理を行う第１の回路パターン１７および第２の回路パターン１９を露出させる。   In FIG. 6A, the resist layer used to form the first circuit pattern 17 and the second circuit pattern 19 is peeled and removed, and a new resist layer is coated to provide external electrodes, bonding electrodes for circuit elements, and the like. The first circuit pattern 17 and the second circuit pattern 19 that perform the surface treatment are exposed.

図６（Ｂ）では、露出された第１の回路パターン１７と第２の回路パターン１９の表面に３μｍのニッケル層と０．３μｍの金層を設けて、外付電極３５や回路素子のボンディング電極の表面処理を行う。このニッケル層と金層により回路素子の固着、金属細線のボンディングあるいは半田付けが可能となる。   In FIG. 6B, a 3 μm nickel layer and a 0.3 μm gold layer are provided on the exposed surfaces of the first circuit pattern 17 and the second circuit pattern 19 to bond the external electrodes 35 and circuit elements. Surface treatment of the electrode is performed. The nickel layer and the gold layer can fix the circuit element, bond a metal thin wire, or solder.

図６（Ｃ）では、空洞部１４まで貫通する貫通孔１６ａ、１６ｂが、ＮＣ工作機を用いてルーターで上基板１１の表面から形成される。貫通孔１６ａ、１６ｂはそれぞれ半径０．６ｍｍおよび半径１．７ｍｍである。なお、貫通孔の穴加工は、空洞部１４上端で寸止めされる。貫通孔１６ａ、１６ｂにより空洞部１４は、外気と連絡される。   In FIG. 6C, through holes 16a and 16b penetrating to the cavity 14 are formed from the surface of the upper substrate 11 by a router using an NC machine tool. The through holes 16a and 16b have a radius of 0.6 mm and a radius of 1.7 mm, respectively. In addition, the drilling of the through hole is stopped at the upper end of the cavity portion 14. The cavity 14 communicates with the outside air through the through holes 16a and 16b.

その後、上基板１１の第１の回路パターン１７には図２に示すように回路素子が予定の位置に固着され、ボンディングワイヤーなどで接続される。下基板１２の第２の回路パターン１９は主に外付電極３５(図２ではＡ、Ｂ、Ｃ、Ｄで示す)として用いられ、プリント基板などに表面実装されるときに用いる。   Thereafter, as shown in FIG. 2, circuit elements are fixed to the first circuit pattern 17 of the upper substrate 11 at a predetermined position, and are connected by a bonding wire or the like. The second circuit pattern 19 of the lower substrate 12 is mainly used as an external electrode 35 (indicated by A, B, C, and D in FIG. 2) and used when being surface-mounted on a printed circuit board or the like.

本発明の空洞部を有する回路基板の断面図である。It is sectional drawing of the circuit board which has a cavity part of this invention. 本発明の空洞部を有する回路基板の（Ａ）底面図および（Ｂ）上面図である。It is the (A) bottom view and (B) top view of the circuit board which has a cavity part of this invention. 本発明の製造方法で完成した空洞部を有する回路基板の上基板の製造工程を説明する断面図（Ａ）〜（Ｅ）である。It is sectional drawing (A)-(E) explaining the manufacturing process of the upper board | substrate of the circuit board which has the cavity part completed with the manufacturing method of this invention. 本発明の製造方法で完成した空洞部を有する回路基板の下基板の製造工程を説明する断面図（Ａ）〜（Ｆ）である。It is sectional drawing (A)-(F) explaining the manufacturing process of the lower board | substrate of the circuit board which has the cavity part completed with the manufacturing method of this invention. 本発明の製造方法で完成した空洞部を有する回路基板の上基板と下基板の貼り合わせ工程を説明する断面図（Ａ）〜（Ｅ）である。It is sectional drawing (A)-(E) explaining the bonding process of the upper board | substrate and lower board | substrate of a circuit board which has the cavity part completed with the manufacturing method of this invention. 本発明の製造方法で完成した空洞部を有する回路基板の最終の製造工程を説明する断面図（Ａ）〜（Ｃ）である。It is sectional drawing (A)-(C) explaining the last manufacturing process of the circuit board which has the cavity part completed with the manufacturing method of this invention. 従来の回路基板を説明する断面図である。It is sectional drawing explaining the conventional circuit board. ＭＥＭＳ回路素子を説明する断面図である。It is sectional drawing explaining a MEMS circuit element. ＭＥＭＳ回路素子を実装した従来の実装構造を説明する断面図である。It is sectional drawing explaining the conventional mounting structure which mounted the MEMS circuit element.

符号の説明Explanation of symbols

１０ 回路基板
１１ 上基板
１２ 下基板
１３ 接着層
１４ 空洞部
１５ａ、１５ｂ スルーホール電極
１６ａ、１６ｂ 貫通孔
１７ 第１の回路パターン
１８ａ、１８ｂ スルーホール
１９ 第２の回路パターン
２０ａ、２０ｂ 導電箔
２１ａ、２１ｂ 導電箔
３１ ガイド孔
３２、３３ レジスト層
３４ アンダーコート樹脂
３５ 外付電極 DESCRIPTION OF SYMBOLS 10 Circuit board 11 Upper board 12 Lower board 13 Adhesive layer 14 Cavity part 15a, 15b Through-hole electrode 16a, 16b Through-hole 17 1st circuit pattern 18a, 18b Through-hole 19 2nd circuit pattern 20a, 20b Conductive foil 21a, 21b Conductive foil 31 Guide hole 32, 33 Resist layer 34 Undercoat resin 35 External electrode

Claims (7)

上基板と、
前記上基板の表面の前記導電箔から形成した任意の第１の回路パターンと、前記上基板の裏面に設けた接着シートと、
下基板と、
前記下基板の表面の前記導電箔から形成した任意の第２の回路パターンと、前記下基板の裏面の前記導電箔を除去して形成した空洞とその周囲に設けた絶縁層と、
前記上基板の裏面の前記接着シートと前記下基板の裏面の前記絶縁層とを接着して、前記上基板、前記下基板および前記絶縁層とで囲まれる空洞部と、
前記上基板の前記第1の回路パターンと前記下基板の前記第２の回路パターンとを接続するスルーホール電極とを具備することを特徴とする空洞部を有する回路基板。 An upper substrate;
An arbitrary first circuit pattern formed from the conductive foil on the surface of the upper substrate; and an adhesive sheet provided on the back surface of the upper substrate;
A lower substrate,
An arbitrary second circuit pattern formed from the conductive foil on the surface of the lower substrate, a cavity formed by removing the conductive foil on the back surface of the lower substrate, and an insulating layer provided around the cavity,
A cavity surrounded by the upper substrate, the lower substrate, and the insulating layer by bonding the adhesive sheet on the back surface of the upper substrate and the insulating layer on the back surface of the lower substrate;
A circuit board having a cavity, comprising a through-hole electrode that connects the first circuit pattern of the upper board and the second circuit pattern of the lower board. 前記空洞部に前記上基板あるいは前記下基板を貫通する貫通孔を設けたことを特徴とする請求項１に記載の空洞部を有する回路基板。   The circuit board having a cavity portion according to claim 1, wherein a through-hole penetrating the upper substrate or the lower substrate is provided in the cavity portion. 前記貫通孔上に回路素子のダイアフラムを配置することを特徴とする請求項２に記載の空洞部を有する回路基板。   The circuit board having a hollow portion according to claim 2, wherein a diaphragm of a circuit element is disposed on the through hole. 両面に導電箔を設けた上基板を準備する工程と、
前記上基板の一方の前記導電箔をエッチングして予定の空洞パターンを形成する工程と、
両面に導電箔を設けた下基板を準備する工程と、
前記下基板の一方の前記導電箔をエッチングして予定の空洞部となる部分を残す工程と、
前記下基板の前記予定の空洞部となる部分の前記導電箔の周囲を絶縁層で埋め、前記予定の空洞部となる部分の前記導電箔をエッチングして前記空洞部を形成する工程と、
前記上基板の前記予定の空洞パターンの周囲に接着層を付着する工程と、
前記上基板と下基板とを前記接着層で貼り合わせて前記空洞部を形成する工程とを具備することを特徴とする空洞部を有する回路基板の製造方法。 Preparing an upper substrate provided with conductive foil on both sides;
Etching one of the conductive foils on the upper substrate to form a predetermined cavity pattern;
Preparing a lower substrate provided with conductive foil on both sides;
Etching the conductive foil on one side of the lower substrate to leave a portion that becomes a predetermined cavity,
Filling the periphery of the conductive foil in the part of the lower substrate with the predetermined cavity with an insulating layer, etching the conductive foil in the part of the predetermined cavity to form the cavity;
Depositing an adhesive layer around the predetermined cavity pattern of the upper substrate;
And a step of forming the cavity by bonding the upper substrate and the lower substrate together with the adhesive layer. 両面に導電箔を設けた上基板を準備する工程と、
前記上基板の一方の前記導電箔をエッチングして予定の空洞パターンを形成する工程と、
両面に導電箔を設けた下基板を準備する工程と、
前記下基板の一方の前記導電箔をエッチングして予定の空洞部となる部分を残す工程と、
前記下基板の前記予定の空洞部となる部分の前記導電箔の周囲を絶縁層で埋め、前記予定の空洞部となる部分の前記導電箔をエッチングして前記空洞部を形成する工程と、
前記上基板の前記予定の空洞パターンの前記導電箔の周囲に接着層を付着する工程と、
前記上基板と下基板とを前記接着層で貼り合わせて前記空洞部を形成する工程と、
前記上基板および下基板を貫通するスルーホールを形成し、スルホール電極を形成する工程と、
前記上基板および下基板の外部に面する他方の導電箔をエッチングして前記上基板に第１の回路パターンを前記下基板に第２の回路パターンを形成する工程と、
前記上基板あるいは下基板より前記空洞部まで到達する貫通孔を形成する工程とを具備することを特徴とする空洞部を有する回路基板の製造方法。 Preparing an upper substrate provided with conductive foil on both sides;
Etching one of the conductive foils on the upper substrate to form a predetermined cavity pattern;
Preparing a lower substrate provided with conductive foil on both sides;
Etching the conductive foil on one side of the lower substrate to leave a portion that becomes a predetermined cavity,
Filling the periphery of the conductive foil in the part of the lower substrate with the predetermined cavity with an insulating layer, etching the conductive foil in the part of the predetermined cavity to form the cavity;
Attaching an adhesive layer around the conductive foil of the predetermined cavity pattern of the upper substrate;
Bonding the upper substrate and the lower substrate with the adhesive layer to form the cavity,
Forming a through hole penetrating the upper substrate and the lower substrate, and forming a through hole electrode;
Etching the other conductive foil facing the outside of the upper substrate and the lower substrate to form a first circuit pattern on the upper substrate and a second circuit pattern on the lower substrate;
Forming a through hole reaching the cavity from the upper substrate or the lower substrate. A method of manufacturing a circuit board having a cavity. 前述した工程に続き、前記第１の回路パターンに回路素子を配置する工程を具備することを特徴とする請求項５に記載の空洞部を有する回路基板を用いた回路装置の製造方法。   6. The method of manufacturing a circuit device using a circuit board having a cavity according to claim 5, further comprising a step of arranging a circuit element in the first circuit pattern following the step described above. 前記回路素子としてダイアフラムを有する半導体素子を前記空洞部まで到達する貫通孔の上に組み込むことを特徴とする請求項６に記載の空洞部を有する回路基板を用いた回路装置の製造方法。   7. The method of manufacturing a circuit device using a circuit board having a cavity part according to claim 6, wherein a semiconductor element having a diaphragm as the circuit element is incorporated in a through hole reaching the cavity part.
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Publication number Priority date Publication date Assignee Title
EP2582155A2 (en) 2011-10-12 2013-04-17 Funai Electric Co., Ltd. Microphone unit and method of manufacturing microphone unit
JP2016048768A (en) * 2014-08-28 2016-04-07 日立化成株式会社 Wiring board and manufacturing method of semiconductor device

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