TW201026171A - Circuit substrate with hole and method of preparing the same - Google Patents

Circuit substrate with hole and method of preparing the same Download PDF

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Publication number
TW201026171A
TW201026171A TW098107827A TW98107827A TW201026171A TW 201026171 A TW201026171 A TW 201026171A TW 098107827 A TW098107827 A TW 098107827A TW 98107827 A TW98107827 A TW 98107827A TW 201026171 A TW201026171 A TW 201026171A
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TW
Taiwan
Prior art keywords
hole
substrate
hole portion
upper substrate
lower substrate
Prior art date
Application number
TW098107827A
Other languages
Chinese (zh)
Other versions
TWI371993B (en
Inventor
Goro Narita
Original Assignee
Element Denshi Co Ltd
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Publication of TW201026171A publication Critical patent/TW201026171A/en
Application granted granted Critical
Publication of TWI371993B publication Critical patent/TWI371993B/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A circuit substrate with a hole is provided, which utilizes two substrates with the hole formed therebetween. Also provided is a method to realize the preparation of the same. The circuit substrate of the present invention comprises a first circuit pattern 17 formed of an electrically conductive foil 20a on the front surface of an upper substrate 11, an adhesive layer 13 provided to the back surface of the upper substrate 11, a second circuit pattern 19 formed of an electrically conductive foil on the front surface of a lower substrate 12, a hole 14 formed by removing a part of the electrically conductive foil 21b on the back surface of the lower substrate 12, and an insulation layer 34 provided around the hole 14, wherein the adhesive layer 13 on the back surface of the upper substrate 11 and the adhesive layer 34 on the back surface of the lower substrate 12 are adhered to each other, and the hole 14 surrounded by the upper substrate 11, lower substrate 12 and adhesive layer 34 is formed between the two substrates.

Description

201026171 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種具有孔洞部之電路基板及其製造方 法’尤有關於-種使用2個基板而在其間構成孔洞部之具 有孔洞部之電路基板及其製造方法。 【先前技術】 第7圖係顯不將Ic晶片埋入於基板中之高密度安裝基 板。 此女裝基板係由第1基板100、第2基板綱、第3基 板300、K曰曰片400、導電性連接構件500及密封構件600 所構成° f 1基板1GG、第2基板_及第3基板綱係 為印刷基板’形成有所希望之配線圖案。帛1基板⑽及 第2,板20G係她合,在_方基板之外表面係形成具有 可收:IC^a曰片40G之底面積及深度之凹部。1(:晶片4〇〇 :、H w it凹^ ’且藉由由焊鍚等金屬凸塊(b卿)所开) 成之導電性連接構件5⑽來與凹部之底面連接。再者 二保持機械性強度,且保護Ic晶片彻,乃藉由環氧樹月旨 等密封構件_來密封。之後,第3基板300係疊層在前 =凹補,形成將前述凹部密封之多層印刷基板(參照第7 L)所亦即、,在由第1基板_、第2基板⑽及第3基板 ㈣之3層結構之黏貼(疊層)多層印刷基板中,僅 中層之第2基板2GG形成衝切部·,且在此衝 入有iC晶片400。 至 此外’最近,在被稱為石夕⑽MS)麥克風之石夕基板組入 323098 4 201026171 有作為振動板之隔膜(diaphragm)之小型麥克風已漸為普 及。MEMS 係為 Micro Electro Mechanical System(微機電 系統)之簡稱。 第8圖係顯示矽(MEMS)麥克風之一例。設有:矽基板 51 ’保留周圍;隔膜52,由貼在矽基板51之圓形貫通孔 之金屬膜所構成;背板(backplate)55,與隔膜52相對向 而隔以空氣間隙(air gap)53將背板電極54設於表面;焊 Ο φ 墊(bonding pad)56,在矽基板51上與隔膜52連接;及焊 墊57,與背板電極54連接。 隔臈52之振動係以隔膜52與背板電極54所形成之電 容器之電容之變化來檢測,且以CM〇SIC予以再生。 第9圖係說明安裝結構。在印刷基板61上組入石夕(藝' 麥克風62與cm〇SIC63,且以箱型之箱體(_)64收納其> 整體。於碎簡S)麥克風之隔膜52附近,在箱體料必定 設有音孔65 ’用以將來自外部之聲音傳遞至隔 CM0SIC63㈣⑽MS)麥克風雜㈣切式 板61之配線來連接。 WP刷丞 專利文獻1:日本特開平G9_321438 【發明内容】 [發明欲解決之問題] 然而,在上述之習知安裝基板中, 裝基板且在其間形成孔洞,係有在其使用多層4 成衝切部之作法為㈣單之方法欲的中間基相 有3片基板,因此會有難 欢I成衝切部必潘 谓具有⑼之衫基板予以 321098 201026171 型化之問題。 此外’在將上述之石夕⑽MS)麥克風等組入時雖需有 用以取入$音之音孔,惟由於使用箱發 會有無法提 升安裝密度之問題。 [解決問題之方案] 本發明係有上述問題而研創者,其目的在提供- 種具有孔洞部之電路基板,其特徵為具傷:上基板;任意 之第1電路圖案,由前述上基杯矣 Θ M 之導電猪所形成;黏 ^層’汉在刚述上基板之背面;下基板;任意之第2電路 ^案,由前述下基板表面之導電落所形成;孔洞,將前述 =基板背面之導電箱予以去除所形成;絕緣層,設在該孔 I;之周圍;孔洞部,將前述上基板背面之前述黏接層與前 ^下基板背面之前述絕緣層予以.黏接,而由前述上基板、 ^返下基板及前述絕緣層所包圍;及貫穿孔(thrQughh〇le) 將前述上基板之前述第i電路圖案與前述下基板之 J ^^第2電路圖案予以連接。[Technical Field] The present invention relates to a circuit board having a hole portion and a method of manufacturing the same, and more particularly to a circuit having a hole portion in which a hole portion is formed using two substrates Substrate and method of manufacturing the same. [Prior Art] Fig. 7 shows a high-density mounting substrate in which an Ic wafer is not buried in a substrate. The women's substrate is composed of a first substrate 100, a second substrate, a third substrate 300, a K-plate 400, a conductive connecting member 500, and a sealing member 600. The f 1 substrate 1GG, the second substrate _ The 3 substrate system is a printed circuit board 'forming a desired wiring pattern. The 帛1 substrate (10) and the second plate 20G are joined together, and a concave portion having a bottom area and a depth of the IC 曰 曰 40G is formed on the outer surface of the _ square substrate. 1 (: wafer 4 〇〇 :, H w it concave ^ ′ and connected to the bottom surface of the concave portion by a conductive connecting member 5 (10) made of a metal bump such as a solder bump. Further, the mechanical strength is maintained, and the Ic wafer is protected, and sealed by a sealing member such as an epoxy resin. After that, the third substrate 300 is laminated on the front side = the concave portion, and the multilayer printed circuit board (see the seventh L) that seals the concave portion is formed, that is, the first substrate _, the second substrate (10), and the third substrate. (4) In the three-layer structure of the adhesive (laminated) multilayer printed circuit board, only the second substrate 2GG of the middle layer forms a punched portion, and the iC wafer 400 is punched therein. In addition, recently, the Shih-Hsin substrate, which is called the Shi Xi (10) MS) microphone, was incorporated into 323098 4 201026171. A small microphone with a diaphragm as a diaphragm has become popular. MEMS is an abbreviation for Micro Electro Mechanical System. Fig. 8 shows an example of a MEMS microphone. It is provided that the ruthenium substrate 51' retains the periphery; the diaphragm 52 is composed of a metal film attached to the circular through hole of the 矽 substrate 51; and the back plate 55 is opposed to the diaphragm 52 with an air gap (air gap) 53 is provided on the surface of the back plate electrode 54; a bonding pad 56 is connected to the separator 52 on the substrate 51; and a pad 57 is connected to the back plate electrode 54. The vibration of the diaphragm 52 is detected by a change in the capacitance of the capacitor formed by the diaphragm 52 and the back plate electrode 54, and is regenerated by CM 〇 SIC. Figure 9 illustrates the mounting structure. On the printed circuit board 61, Shi Xi (Yi's microphone 62 and cm〇SIC 63 are housed, and the box-shaped box (_) 64 is housed in the whole body. In the vicinity of the diaphragm 52 of the microphone, in the cabinet It is necessary to provide a sound hole 65' for connecting the sound from the outside to the wiring of the CM0SIC 63 (4) (10) MS) microphone miscellaneous (four) cutting board 61. WP 丞 丞 丞 日本 日本 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 The method of cutting the part is that the intermediate phase of the method of (4) has three substrates, so there will be a problem that the board of the shirt of the (9) is 321098 201026171. In addition, when the above-mentioned Shi Xi (10) MS) microphone is incorporated, it is necessary to take in the sound hole of the $ sound, but the use of the box may not increase the mounting density. [Solution to Problem] The present invention has been made in view of the above problems, and an object thereof is to provide a circuit board having a hole portion, which is characterized in that it has an injury: an upper substrate; any first circuit pattern, which is formed by the aforementioned base cup导电M is formed by a conductive pig; the adhesive layer is placed on the back side of the substrate; the lower substrate; any second circuit is formed by the conductive falling of the surface of the lower substrate; the hole, the aforementioned = substrate The conductive box on the back surface is removed; the insulating layer is disposed around the hole I; and the hole portion is used for bonding the adhesive layer on the back surface of the upper substrate to the insulating layer on the back surface of the front substrate. The first substrate, the return substrate, and the insulating layer are surrounded by the through substrate, and the through hole (thrQ) is connected to the ith circuit pattern of the upper substrate and the second circuit pattern of the lower substrate.

Q 每或^,依據本發明,在前述孔洞部設有貫通前述上基 '见下基板之貫通孔。 1¾骐 再者,依據本發明,在前述貫通孔上配置電路元件之 被之制,本發明之製造方法,係—種具有孔洞部之電路基 上A如方法,其特徵為具備:準備在兩面設有導電箔之 驟’將刚述上基板—方之前述導電羯進行敍刻 "預定孔洞圖案之步驟;準備在兩面設有導電箔之下 321098 6 201026171 ❹ 基板之步驟;將前述下基板一方之前述導電笛進行 保留作為預定孔洞部之部分之步驟;將前述下基板之 前述預定孔洞部之部分之前述導電猪之周圍以絕緣声= 填埋,且將作為前述預定孔洞部之部分之前述導電二二 蝕刻而形成前述孔洞部之步輝;在前述上基板之前述: 孔洞圖案之周圍附著黏接層之步驟;及將前述上基= 基板以前述黏接層予以黏合而形成前述孔洞部之步驟:、 此外,依據本發明之製造方法,係一種具有孔 電路基板之製造方法,其特徵為具備:準備在兩面設有導 電簿之上基板之步驟;將前述上基板一方之前述導 $侧而形成預定孔洞圖案之步驟;準備在兩面設有導電 >白之下基板之步驟;將前述下基板一方之前述導電落進行 = ί預定孔洞部之部分之步驟;將前述下基板 屉予:Γ &孔洞部之部分之前述導電箱之周圍以絕緣 U,且將作為前述預定孔洞部之部分之前述導電 =二㈣而形成前述孔洞部之步驟;在前述上基板之前 將案之前述導電箔之周圍附著黏接層之步驟; 將=上基板與下基板以前述黏According to the invention, in the hole portion, a through hole penetrating the upper substrate 'see the lower substrate is provided in the hole portion. Further, according to the present invention, a circuit component is disposed on the through hole, and the manufacturing method of the present invention is a circuit on the circuit substrate having a hole portion, such as a method, characterized in that it is provided on both sides. a step of providing a conductive foil with a step of "predicting a predetermined pattern of holes" of the above-mentioned conductive substrate; preparing a step of providing a substrate with a conductive foil on both sides of the 321098 6 201026171 ❹ substrate; a step of retaining the conductive flute of the one side as a part of the predetermined hole portion; filling the periphery of the conductive pig of the portion of the predetermined hole portion of the lower substrate with an insulating sound = and as a part of the predetermined hole portion The step of forming the hole portion by the conductive etching; the step of attaching the adhesive layer around the hole pattern of the upper substrate; and bonding the upper substrate = the substrate with the adhesive layer to form the hole Step of: In addition, the manufacturing method according to the present invention is a manufacturing method of a circuit board having a hole, characterized in that it is provided in two a step of providing a substrate on the conductive book; a step of forming a predetermined hole pattern on the side of the upper substrate; and a step of providing a conductive substrate on both sides; and forming the lower substrate The step of conducting the conductive layer = ί a portion of the hole portion; and the foregoing substrate holder is provided with an insulating U around the portion of the conductive case of the portion of the hole portion, and the conductive portion as a part of the predetermined hole portion is Step (2) of forming the hole portion; attaching the adhesive layer to the periphery of the conductive foil before the upper substrate; and pressing the upper substrate and the lower substrate

孔洞部之步驟; ❿風月丨J^L 且形成貫穿孔電極::基板及下基板之貫穿孔, 外部之另-方暮^ 將前述上基板及下基板之面對 路圖案、在前、十&進打银刻而在前述上基板形成第1電 成從前述上基被成第2電路圖案之步驟;以及形 驟。 莰或下基板到達前述空洞部之貫通孔之步 321098 7 201026171 再者,依據本發明之製造方法,係具備:繼前述之步 驟,、而在前述第1電路圖案配置電路元件之步驟。 再者,依據本發明之製造方法,係❹具有隔膜之半 導體元件作為前述電路元件。 [發明之功效] =本發明,可提供—種電路基板,使用夾在上基相 ;、下基板之間之導電荡而實現孔洞部。因 2片基板形成孔_,且可使電路基板小型化。^至^ ❹ =板之面對外側之導衫可分卿成電 仃電路元件之兩面安裴。 斧而了4 此外’在本發明中,藉由 !案而可將孔洞部形成任意形狀之孔洞部,且可 =位置’而其大小係可以導電羯之厚度來選擇二、 在本發明中,孔洞部係可藉由導電箱之 工,而不需機械加工。 j進仃加 ❹ 基拓Γ者’在本發明中,由於在上基板表面之導電箱及下 :將==設置第1電路圖案及第2電路圖案,因 樣地進行電路元件路基板’可以與兩面基板同 之安^=本發财,完μ需要如f知職s電路元件 度顯著提:不<或缺之音孔的箱體’而可使安裝密 依據本㈣之㈣方法,係藉由使用在兩面具有導電 基板與下基板而町藉由導電箔之韻刻在兩基板之間 32]098 8 201026171 2片基板而實現孔 形成孔洞部。藉此,電路基板即可藉由 洞部。 此外 板背面 由於制部係以下基 =肖導電_之㈣而形成’因此不需要絲等之機械 ::大生處理,因此其形狀亦任= 成,、大小亦視下基板旁面之導電落之厚度而定。 再者,依據本發明之製造方法, 係以黏,牢固地黏貼,因此電路基板可 與ί基板表面之導電落而進行兩面基板:處理, =處理之際,可將處理液等對於孔_之侵人予以完全 再者’依縣發明之製造方法,•⑽部係可完 =上基板與下基板之間而形成’因此可在最終步驟心 ,貝通孔而將孔洞部與外氣連通,而可賴㈣部不受; 異物之侵入直到最終步驟。 〇 【實施方式】 以下參照第1圖詳細說明本發明之實施形態。 首先’第1圖係顯示本發明之具有孔洞部之電路基板 之剖面圖。 具有孔洞部之電路基板10係由上基板u、下基板12、 黏接層13、孔洞部14、貫穿孔電極15a、15b、及貫通孔 16a、16b所構成》 上基板11係為在兩表面黏貼有導電箔2〇a、2〇b之玻 璃環氧基板。在背面之導電2Gb之任意之位置,係蚀刻 321098 9 201026171 而形成與孔洞部相同形狀之孔洞圖案之導電箔20b。孔洞 圖案之導電鴒20b之周圍,係由作為黏接層13之接合板 (bonding sheet)等所包圍。 表面之導電箔20a係具有第1電路圖案π,而第1電 路圖案17係由曝光顯影、蝕刻所形成。 下基板12係為在兩表面黏貼有導電箔21a、21b之玻 璃環氧基板。背面之導電箔21b係首先钱刻而形成與孔洞 部相同形狀之孔洞圖案之導電箔21b,且將其周圍以屬於 絕緣物之底塗(undercoat)樹脂34等進行填埋,且從該處 © 將孔洞圖案之導電箔21b進行蝕刻予以去除而形成孔洞部 Η 〇 表面之導電箔21a係具有第2電路圖案19,而第2電 路圖案19係藉由曝光顯影、蝕刻而形成。 黏接層13係使用令環氧系樹脂半硬化在玻璃布 (glass cloth)之超級接合板(3叩61· bonding sheet(商品 名稱)),將兩基板11、12之背面彼此黏合而成為丨個電路 基板。 ❹ 孔洞部14係由:將形成在下基板a背面之孔洞圖案 之導電箔21b進行蝕刻去除所形成之孔洞、包圍該孔洞之 底塗树知34及形狀相同於上基板丨丨背面之孔洞部之孔洞 圖案之導電羯20b所包圍之空間所形成。另外,孔洞圖案 之導電箔20b亦有被去除而使上基板u之表面露出之情 形。 貫穿孔電極15a、15b係為形成貫通上基板n、下基 10 321098 201026171 板12及黏接層13之貫穿孔18a、18b,且進行貫穿孔鍍覆 處理之電極。在此,如圖所示,係在電路基板10之兩端形 成2個。貫穿孔電極15a、15b係將第1電路圖案π、第2 電路圖案19之所希望部位予以電性連接。 貫通孔16a、16b係為從上基板11或下基板12之表面 對於孔洞部14之兩端以NC工作機所形成之孔。貫通孔 16a、16b係可僅形成於上基板n或下基板12,亦可分別 設在上基板11與下基板12。 ❹ 另外,孔洞部14雖係可考慮作為MEMS麥克風之音孔 來利用,惟亦可作為MEMS非接觸溫度感測器等之檢測孔來 利用。 接著’ f 2圖係說明具體化之電路基板之底面圖及 視圖。 第2圖(A)係顯示在下基板12表面之導電箔21&所形 成之第2電路圖案19。在4個角落具有由貴金屬鑛覆層所 參構成之A、B、C、D之外接電極,且在中央斜方向所示之虚 線係為本發明之孔洞部i 4。被塗黑之4個圓圈係為貫穿= 電極15a、15b(其餘2個無符號)。 第2圖(B)係顯示在上基板u表面之導電箔2〇a所形 成之第1電路圖案17。被塗黑之4個圓圈係為貫穿孔雷 -、^(其餘⑽無符號卜且與人^^之外接電極 連接。中央斜方向所示之虛線係為本發明之孔洞部Η。由 於疋從相反面觀看,所以看起來是朝與第2圖(々)正交 向傾斜。 321098 11 201026171 此外,在中央部之貫通孔l6a上,係固接具有隔膜之 MEMS等電路元件23,且將隔膜與貫通孔恤相對向,且藉 由接合線(bondingwire)將電路元件23之各焊塾⑽涵叩 padm及設在第1電路圖案17之各連接電極25予以連接。 在此種結構中’係從設在電路基板10週邊之貫通孔 肌進行集音,經孔洞部14傳播而從貫通孔16a傳遞至電 路兀件23之隔膜。另外’關於隔媒係與第8圖所說明者相 同。Step of the hole portion; ❿风月丨 J^L and forming a through-hole electrode:: a through hole of the substrate and the lower substrate, the outer side of the other side 暮 ^ the facing pattern of the upper substrate and the lower substrate, in front, ten & a step of forming a first electric circuit on the upper substrate to form a second circuit pattern from the upper substrate; and forming a step. The step of the boring or the lower substrate reaching the through hole of the cavity portion 321098 7 201026171 Further, the manufacturing method according to the present invention includes the step of arranging the circuit element in the first circuit pattern in accordance with the above steps. Further, according to the manufacturing method of the present invention, a semiconductor element having a diaphragm is used as the circuit element. [Effect of the Invention] According to the present invention, a circuit board can be provided, and a hole portion can be realized by using a conductive sway between the upper substrate and the lower substrate. The hole _ is formed in two substrates, and the circuit board can be miniaturized. ^至^ ❹ = The outer side of the board can be divided into two sides of the circuit components. In addition, in the present invention, the hole portion can be formed into a hole portion of any shape by the case, and can be selected as the position and can be selected by the thickness of the conductive wire. In the present invention, The hole section can be machined by a conductive box without machining. In the present invention, since the conductive box on the surface of the upper substrate and the lower side: == the first circuit pattern and the second circuit pattern are set, With the two-sided substrate, the same ^ ^ this is a fortune, the end of the μ needs to be as good as the circuit component of the f s s: not < or lack of the sound hole of the box 'and can be installed according to the (four) (4) method, The hole forming hole portion is realized by using two substrates having a conductive substrate and a lower substrate on both sides and engraved between the two substrates by the rhombic of the conductive foil 32]098 8 201026171. Thereby, the circuit board can be made by the hole portion. In addition, since the back surface of the board is formed by the following base = 导电 ( ( ( ( ( ( ( ( ( ( ( ( 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Depending on the thickness. Moreover, according to the manufacturing method of the present invention, the bonding method is adhered firmly and firmly, so that the circuit substrate can be electrically separated from the surface of the substrate to perform the two-sided substrate: processing, and the processing liquid can be used for the hole. The invading person is completely re-contained by the manufacturing method of the invention according to the county. (10) The department can be completed between the upper substrate and the lower substrate. Therefore, in the final step, the hole can be communicated with the outside air. And the (4) part is not subject to; the invasion of foreign objects until the final step. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to Fig. 1. First, Fig. 1 is a cross-sectional view showing a circuit board having a hole portion of the present invention. The circuit board 10 having the hole portion is composed of the upper substrate u, the lower substrate 12, the adhesive layer 13, the hole portion 14, the through hole electrodes 15a and 15b, and the through holes 16a and 16b. The upper substrate 11 is formed on both surfaces. A glass epoxy substrate with conductive foils 2〇a and 2〇b adhered thereto. At any position of the conductive 2Gb on the back surface, 321098 9 201026171 is etched to form a conductive foil 20b having a hole pattern of the same shape as the hole portion. The periphery of the conductive crucible 20b of the hole pattern is surrounded by a bonding sheet or the like as the adhesive layer 13. The surface conductive foil 20a has a first circuit pattern π, and the first circuit pattern 17 is formed by exposure development and etching. The lower substrate 12 is a glass epoxy substrate on which conductive foils 21a and 21b are adhered to both surfaces. The conductive foil 21b on the back side is a conductive foil 21b which is first formed into a hole pattern having the same shape as that of the hole portion, and is filled with an undercoat resin 34 or the like which is an insulator, and from which it is left. The conductive foil 21b of the hole pattern is etched and removed to form a hole portion, and the conductive foil 21a having the surface of the hole has a second circuit pattern 19, and the second circuit pattern 19 is formed by exposure development and etching. In the adhesive layer 13, a super-bonding plate (3叩61·bonding sheet (trade name)) in which an epoxy resin is semi-cured to a glass cloth is used, and the back surfaces of the two substrates 11 and 12 are bonded to each other to form a crucible. Circuit board. The hole portion 14 is a hole formed by etching and removing the conductive foil 21b formed in the hole pattern on the back surface of the lower substrate a, a primer layer 34 surrounding the hole, and a hole portion having the same shape as the back surface of the upper substrate The space surrounded by the conductive turns 20b of the hole pattern is formed. Further, the conductive foil 20b of the hole pattern is also removed to expose the surface of the upper substrate u. The through-hole electrodes 15a and 15b are electrodes for forming through-holes 18a and 18b penetrating the upper substrate n, the lower substrate 10 321098 201026171, and the adhesion layer 13 and performing through-hole plating treatment. Here, as shown in the figure, two are formed at both ends of the circuit board 10. The through hole electrodes 15a and 15b electrically connect the first circuit pattern π and the desired portion of the second circuit pattern 19. The through holes 16a and 16b are holes formed from the upper surface of the upper substrate 11 or the lower substrate 12 by the NC working machine at both ends of the hole portion 14. The through holes 16a and 16b may be formed only on the upper substrate n or the lower substrate 12, or may be provided on the upper substrate 11 and the lower substrate 12, respectively. Further, the hole portion 14 can be used as a sound hole of a MEMS microphone, but can be used as a detection hole of a MEMS non-contact temperature sensor or the like. Next, the 'f 2 diagram shows the bottom view and the view of the embodied circuit board. Fig. 2(A) shows the second circuit pattern 19 formed by the conductive foil 21& on the surface of the lower substrate 12. In the four corners, there are electrodes A, B, C, and D which are composed of the precious metal ore coating, and the dotted line shown in the center oblique direction is the hole portion i 4 of the present invention. The four circles that are blacked out are through the electrodes 15a, 15b (the remaining two are unsigned). Fig. 2(B) shows the first circuit pattern 17 formed on the conductive foil 2A of the surface of the upper substrate u. The four circles that are blacked out are through-hole Ray-, ^ (the rest (10) is unsigned and connected to the external electrode of the human ^^. The dotted line shown in the center oblique direction is the hole portion of the present invention. Viewed from the opposite side, it appears to be inclined orthogonally to the second figure (々). 321098 11 201026171 In addition, a circuit element 23 such as a MEMS having a diaphragm is fixed to the through hole 16a of the center portion, and the diaphragm is Opposite the through-hole shirt, and each of the solder fillets (10) of the circuit component 23 and the connection electrodes 25 provided in the first circuit pattern 17 are connected by a bonding wire. The sound is collected from the through-hole muscles provided around the periphery of the circuit board 10, and propagates through the hole portion 14 to the diaphragm of the circuit element 23 from the through-holes 16a. The same applies to the spacer system as described in Fig. 8.

Q 接著參照第3至第5圖說明本發明之具有孔洞部之電 路基板之製造方法。 本發明之製造方法係由以下步驟所構成:準備在兩面 設有導電荡之上基板之步驟;將前述上基板一方之前述導 電,蚀刻而形成預定孔洞圖案之步驟;準備在兩面設 有¥電ϋ之下基板之步驟;將前迷下基板—方之前述導電 而保留作為預定孔洞部之部分之步驟;將前述 下基板之作為前述預定孔洞部之部分之前述導電箱之周圍 以絕緣層予以填埋,且將作為前述狀孔洞部之部分之前 述導電落進行副而形成前述孔洞部之步驟;在前述上基 板之前迷預定孔_案之周_著黏接層之步驟;及將^ =上^與下基板以前述黏接層Μ黏合而形成前述孔洞 部之步驟。 首先,參照第3圖說明上基板u之製造方法 2 3圖⑴中’係、準備在上基板丨丨之兩表面黏貼有 銅等導電fl 20a、2Gb之玻璃環氧基板。導電落I、· 321098 12 201026171 係使用12 "m之鋼箔,而上基板11係使用〇.⑽咖之板厚 者。表面之導電箔2〇a係為了形成載置電路元件之第1電 路圖案而使用者。背面之導電箔20b係形成孔洞圖案,且 進行後述之接合板之加工。另外,上基板11除玻璃環氧樹 脂以外,亦可選自BT樹脂、複合材(composite)、玻璃聚 醯亞胺(polyimide)樹脂或酚醛紙樹脂等印刷基板材料。耵 樹脂係指以T成分(三氮雜苯(triazine)樹脂)為主成分, 且由B成分(多官能馬來醯亞胺(Maleimide)化合物)或其 ❺ 他改質用化合物所構成之高耐熱附加聚合型熱硬化性樹脂 之總稱。複合材係為將複數個基板材料予以疊層者。另外, 在上基板11係於角落設有在製造步驟中用以定位之引導 孔31 〇 在第3圖(B)中,上基板11背面之導電箔2〇b係將作 為孔洞圖案之部分以阻劑(resist)層32予以選擇性地覆 蓋,以形成孔洞圖案之圖案。Q Next, a method of manufacturing a circuit board having a hole portion according to the present invention will be described with reference to Figs. 3 to 5 . The manufacturing method of the present invention comprises the steps of: preparing a substrate having a conductive upper surface on both sides; and electrically etching the one of the upper substrate to form a predetermined hole pattern; preparing to be provided with electricity on both sides a step of lowering the substrate; a step of retaining the front substrate-side conductive portion as a portion of the predetermined hole portion; and insulating the periphery of the conductive case of the lower substrate as a portion of the predetermined hole portion by an insulating layer a step of forming a hole portion by forming the hole portion as a part of the aforementioned hole portion; forming a predetermined hole in the periphery of the upper substrate _ the step of bonding the layer; and The step of forming the hole portion by bonding the upper and lower substrates to the adhesive layer Μ. First, a method of manufacturing the upper substrate u will be described with reference to Fig. 3. Fig. 3 is a view showing a glass epoxy substrate on which conductive fus 20a and 2Gb such as copper are adhered to both surfaces of the upper substrate. Conductive drop I, · 321098 12 201026171 The use of 12 " m steel foil, and the upper substrate 11 is used 〇. (10) thick plate. The surface conductive foil 2A is intended to form a first circuit pattern on which the circuit component is placed. The conductive foil 20b on the back surface is formed into a hole pattern, and processing of a bonding plate to be described later is performed. Further, the upper substrate 11 may be selected from a printed substrate material such as a BT resin, a composite, a polyimide resin, or a phenolic paper resin, in addition to the glass epoxy resin. Anthracene resin refers to a component which is mainly composed of a T component (triazine resin) and which is composed of a component B (a polyfunctional maleimide compound) or a compound thereof. A general term for heat-resistant addition polymerization type thermosetting resins. The composite material is a laminate of a plurality of substrate materials. In addition, the upper substrate 11 is provided at the corner with a guiding hole 31 for positioning in the manufacturing step. In FIG. 3(B), the conductive foil 2〇b on the back surface of the upper substrate 11 is used as a part of the hole pattern. A resist layer 32 is selectively covered to form a pattern of hole patterns.

在第3圖(C)中,係以阻劑層32為遮罩而將背面之導 電落2Gb進行侧而保留孔洞圖案之導電落施。孔洞圖 案之導電fl 2Gb係與作為貫穿孔電極之_部分之導電箱 20b —起保留。孔洞圖案之導電落2牝之作 麥 =,〇b而利用其平坦性等使聲音等振動娜^ 孔洞W4上面傳播,且用以進行孔洞部^補強。 在第3圖(D)中,係在上某板n 以接人㈣入基板1 #面之導電箱20b侧 覆盍。此接合板係為作為黏接声13者。 在第3圖(E)中,俏疏丄考按層13者 ’、由由射加工將孔洞圖案之背面導 321098 13 201026171 電4 20b上之接合板予以選擇性地去除,而將孔洞圖案之 導電箔20b之周圍之上基板Η予以填埋。 另外’由於在本步驟中,係使用C02雷射將孔洞圖案 之背面導電箔20b上之接合板予以去除,因此導電箔2〇b 之表面露出。藉此,即可防止接合板垂落於孔洞部而塞住 孔洞部14、及變形。 接下來參照第4圖說明下基板12之製造方法。 々在第4圖(A)中,係準備在下基板12之兩表面黏貼有 銅等導電箔21&、2113之玻璃環氧基板。導電箔21&、211) 係使用18 _之銅羯’而下基板12係使用〇1咖之板厚 者表面之導電箔21a係為了形成用以載置電路元件等之 路圖案所使用。f面導電箱灿係為了形成孔洞部 βτ t。另外,下基板12除玻璃環氧樹脂以外,亦可選自 某板=、、複合材、玻璃聚醯亞胺樹脂或酚醛紙樹脂等印刷 二,且料。BT樹脂係指以T成分(三氮雜笨樹脂)為主成 化合物=B成分(多官能馬來醯亞胺化合物)或其他改質用 潘入^構成之高耐熱附加聚合型熱硬化性樹脂之總稱。 :材係為將複數個基板材 板12亦鱼1_甘1 宜日百力外在下基 之引導孔3^基板U同樣在角落設有製造步驟中用以定位 為孔洞圖L圖,’下基板η背面之導電簿將作 孔洞圖案^圖案W以阻劑層33予以選擇性地覆蓋,且形成 圖(C)中,係以阻劑層33為遮罩而將背面之導 321098 14 201026171 電笛21b進行蝕刻而保留孔洞圖案之導電落2lb。 在第4圖(D)中,係將底塗樹脂34等^厚地塗佈在下 基板12之整體背面,且將孔洞圖案之導電落21b予以填 .埋。以底塗樹脂34而言,係以聚酿亞胺衔脂為最佳,且將 液狀之聚醢亞胺樹脂滴下且藉由旋塗機(邮耐)均勾地 擴散使之加熱硬化。 ❹ 在第4圖⑻中,係將底塗樹脂34崎磨至f面導電落 lb之厚度,而使背面導電箔21b之表面露出。 二第4圖⑺中,係將所露出之背面導㈣仙進行姓 』而去除,而形成由底塗樹腊包圍周圍之孔洞部Μ。亦即, 將孔洞圖案背面之導電箔21b予以去除, 的孔洞部Η。 ㈣成-模-樣 ,此,孔洞㈣係可藉由背面導電箱抓之孔洞圖案 =作二任意之:狀,而可實現例如旋渦狀、,八(h〇rn)形 ο =二ΓΓ 外,孔洞部14之厚度係視背面賴 度。厚度而疋,因此藉由選擇此厚度而可形成任意之厚 再者’參照第5圖說明兩基板之黏合步驟。 在第5圖⑴中,係使上基板u之背面 背面相對向並使用引導孔31進行對位。〃 在第5圖⑻中,係藉由黏接層13將上 =予以黏合而形成孔洞部14。將上基板u愈下美板二 機…進行加壓二面以 订 時左右退火而使黏接層13正式硬 321098 15 201026171 化,而藉由黏接層13將上基板π與下基板12 —體黏接而 完成具有孔洞部14之電路基板。 在第5圖(C)中,係使用NC工作機以鑽頭(drill)等將 上基板11及下基板12及黏接層13貫通而開設用以形成貫 穿孔電極15a、15b之貫穿孔15。 在第5圖(D)中,係使用貫穿孔鍍覆而在貫穿孔形成貫 穿孔電極15a、15b。將所黏合之上基板11及下基板12浸 潰在鈀(palladium)溶液,且以兩導電箔20a、21a作為電 極在貫穿孔内壁進行銅之電錢,並充填銅膏料(paste)而形 成貫穿孔電極15a、15b。 在第5圖(E)中,係將與上基板11及下基板12之面對 外侧之導電箔20a、21 a以阻劑層予以覆蓋,而對上基板 11之導電箔20a係將第1電路圖案π之阻劑層予以曝光 顯影’對下基板12之導電箔2ia係將第2電路圖案19之 阻劑層予以曝光顯影,且以其餘之阻劑層作為遮罩將導電 箔20a、21a同時進行蝕刻。此時,由於孔洞部14係藉由 黏接層13將上基板11與下基板密閉,因此蝕刻溶液不 會侵入孔洞部14。導電箔2〇a、21a為銅時’係使用氣化 鐵作為蝕刻溶液。具體之第1電路圖案17及第2電路圖案 19係顯示於第2圖。 最後參照第6圖說明電路基板之最終加工。 在第6圖(A)中’係將形成第1電路圖案17及第2電 路圖案19所使用之阻劑層予以剝離去除,且覆蓋新的阻劑 層而進行外接電極及電路元件之接合電極等之表面處理以 16 321098 201026171 使第1電路圖案17及第2電路圖案19露出。 在第6圖(Β)中,係在所露出之第1電路圖案17與第 2電路圖帛19之表面設置3 /zm之鎳層與G. 3 //m之金層, 並進行外接電極35及電路元件之接合電極之表面處理。藉 由此錄層與金層’即可進行電路元件之ϋ接、金屬細線之 接合或焊接。In Fig. 3(C), the resist layer 32 is used as a mask, and the conduction of the back surface is 2Gb side to maintain the conductive pattern of the hole pattern. The conductive fl 2Gb of the hole pattern is retained together with the conductive case 20b which is the portion of the through hole electrode. The hole pattern of the hole is made of =b, and the flatness or the like is used to make the sound and the like vibrate on the hole W4, and is used to reinforce the hole portion. In Fig. 3(D), the upper plate n is placed on the side of the conductive box 20b on the side of the substrate 1 by the person (4). This joint plate is used as the adhesive sound 13 . In Fig. 3(E), the layer of the layer 13 is 'selected', and the bonding plate on the back surface of the hole pattern 321098 13 201026171 is electrically removed by the laser processing, and the hole pattern is removed. The substrate 之上 on the periphery of the conductive foil 20b is filled. Further, since in this step, the bonding plate on the back surface conductive foil 20b of the hole pattern is removed by using the C02 laser, the surface of the conductive foil 2b is exposed. Thereby, it is possible to prevent the joint plate from falling down on the hole portion, plugging the hole portion 14, and deforming. Next, a method of manufacturing the lower substrate 12 will be described with reference to FIG. In Fig. 4(A), a glass epoxy substrate in which conductive foils 21 & 2113 of copper or the like are adhered to both surfaces of the lower substrate 12 is prepared. The conductive foils 21 & 211) are made of 18 羯 copper 羯 ', and the lower substrate 12 is made of a conductive foil 21a having a thickness of 〇 1 咖 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The f-side conductive box can form a hole portion βτ t. Further, the lower substrate 12 may be selected from the group consisting of a plate =, a composite material, a glass polyimide resin, or a phenolic paper resin, in addition to the glass epoxy resin. The BT resin is a high heat-resistant addition polymerization type thermosetting resin composed of a T component (triazole heteropoly resin) as a main compound = a B component (a polyfunctional maleimide compound) or other modification. The general name. The material is a plurality of base plate plates 12 and the fish is also 1_gan1. The guide hole 3^ of the outer base of the outer layer is also provided in the corner in the manufacturing step for positioning as a hole map L, 'under The conductive book on the back surface of the substrate η will be selectively covered by the resist pattern 33, and formed in the pattern (C), with the resist layer 33 as a mask and the back side of the guide 321098 14 201026171 The flute 21b is etched while leaving the conductive pattern of the hole pattern 2 lb. In Fig. 4(D), the undercoat resin 34 and the like are applied to the entire back surface of the lower substrate 12, and the conductive fall 21b of the hole pattern is filled. In the case of the primer resin 34, the polyamidamine resin is preferred, and the liquid polyimine resin is dropped and heat-hardened by diffusion by a spin coater.第 In Fig. 4 (8), the undercoat resin 34 is smeared to the thickness of the f-plane conductive pad lb, and the surface of the back surface conductive foil 21b is exposed. In Fig. 4 (7), the exposed back side guide (4) is removed and the hole portion surrounded by the base coat wax is formed. That is, the hole portion of the conductive foil 21b on the back surface of the hole pattern is removed. (4) Form-mode-like, here, the hole (4) can be obtained by the pattern of the hole in the back conductive box = two arbitrary shapes: for example, a spiral shape, an eight (h〇rn) shape ο = two The thickness of the hole portion 14 depends on the back surface. Since the thickness is 疋, an arbitrary thickness can be formed by selecting this thickness. Further, the bonding step of the two substrates will be described with reference to Fig. 5. In Fig. 5 (1), the back surface and the back surface of the upper substrate u are opposed to each other and aligned by using the guide holes 31.第 In Fig. 5 (8), the hole portion 14 is formed by bonding the upper layer by the adhesive layer 13. After the upper substrate u is finished, the upper surface of the upper substrate π is compared with the lower substrate 12 by the adhesive layer 13 by performing annealing on both sides to anneal left and right at the time of ordering, and the adhesive layer 13 is officially hardened 321098 15 201026171. The circuit substrate having the hole portion 14 is completed by the body bonding. In Fig. 5(C), the upper substrate 11, the lower substrate 12, and the adhesive layer 13 are penetrated by a drill or the like using a NC machine to form a through hole 15 for forming the through-hole electrodes 15a and 15b. In Fig. 5(D), through-hole plating is used to form through-hole electrodes 15a and 15b in the through holes. The bonded upper substrate 11 and the lower substrate 12 are immersed in a palladium solution, and the two conductive foils 20a and 21a are used as electrodes to carry out copper electricity on the inner wall of the through hole, and are filled with a copper paste to form a paste. Through hole electrodes 15a, 15b. In Fig. 5(E), the conductive foils 20a and 21a facing the outside of the upper substrate 11 and the lower substrate 12 are covered with a resist layer, and the conductive foil 20a of the upper substrate 11 is first. The resist layer of the circuit pattern π is exposed and developed. The conductive foil 2ia of the lower substrate 12 exposes the resist layer of the second circuit pattern 19, and the remaining resist layer is used as a mask to expose the conductive foil 20a, 21a. Etching is performed simultaneously. At this time, since the hole portion 14 seals the upper substrate 11 and the lower substrate by the adhesive layer 13, the etching solution does not intrude into the hole portion 14. When the conductive foils 2a and 21a are copper, the gasified iron is used as an etching solution. Specifically, the first circuit pattern 17 and the second circuit pattern 19 are shown in Fig. 2. Finally, the final processing of the circuit substrate will be described with reference to FIG. In the sixth diagram (A), the resist layer used to form the first circuit pattern 17 and the second circuit pattern 19 is peeled off, and a new resist layer is covered to bond electrodes of the external electrodes and the circuit elements. The surface treatment such as 16 321 098 201026171 exposes the first circuit pattern 17 and the second circuit pattern 19. In Fig. 6 (Β), a nickel layer of 3 / zm and a gold layer of G. 3 / m are provided on the surface of the exposed first circuit pattern 17 and the second circuit pattern 19, and the external electrode 35 is performed. And surface treatment of the bonding electrodes of the circuit components. By means of the recording layer and the gold layer, the connection of the circuit elements, the bonding of the thin metal wires or the soldering can be performed.

Ο 在第6圖(C)中,係使用NC工作機以銑床從上基板η 之表面形成貫通至孔洞部14之貫通孔l6a、l6b。貫通孔 16a 16b係釦別為半徑〇 6随及半徑7咖。另外,貫通 孔之孔加工係停止在孔洞部14上端。孔洞部14係藉由貫 通孔16a、16b而與外氣連通。 _之後,在上基板11之第1電路圖案17,係如第2圖 所示地將電路元件固接於預定之位置且以接合線等予以 連接。下基板12之第2電路圖案19主要係作料接電極 35(在第2圖中係以n _ 丁货'从A、B、C、D表不)來使用,且在表面安 裝於印刷基板等時所使用。 【圖式簡單說明】 之電路基板之剖面圖。 之電路基板之底面圖(A) 第1圖係為本發明具有孔洞部 第2圖係為本發明具有孔洞部 及俯視圖(B)。 第3圖係為說明以本發明之製造方法所 且有 洞部之電路基板之上基板之製造步驟之剖面圖⑴至⑻ 第4圖係為說明以本發明之製造方 洞部之電路純之下基板之製造㈣之至⑺ 321098 17 201026171 . 第5圖係為說明以本發明之製造方法所完成之具有孔 洞部之電路基板之上基板與下基板之黏合步驟之剖面圖(A) 至(E)。 第6圖係為說明以本發明之製造方法所完成之具有孔 洞部之電路基板之最終製造步驟之剖面圖(A)至(C)。 第7圖係為說明習知電路基板之剖面圖。 第8圖係為說明MEMS電路元件之剖面圖。 第9圖係為說明安裝有MEMS電路元件之習知安裝結構 之剖面圖。 【主要元件符號說明】 10 電路基板 11 上基板 12 下基板 13 黏接層 14 孔洞部 15a 、 15b 貫穿孔電極 16a、16b 貫通孔 17 第1電路圖案 18a、18b 貫穿孔 19 第2電路圖案 20a 、 20b 導電箔 21a ' 21b 導電箔 23 電路元件 24 焊墊 25 連接電極 31 引導孔 32、33 阻劑層 34 底塗樹脂 35 外接電極 51 碎基板 52 隔膜 53 空氣間隙 54 背板電極 55 背板 56 焊墊 57 焊墊 60 密封構件 61 印刷基板 18 321098 201026171 62 矽(MEMS)麥克風 63 CMOS1C 64 箱體 65 音孔 70 衝切部 100 第1基板 200 第2基板 300 第3基板 400 1C晶片 500 導電性連接構件 600 密封構件 700 衝切部 ❿ ❿ 19 321098第 In Fig. 6(C), the through holes l6a, 16b penetrating through the hole portion 14 are formed from the surface of the upper substrate η by a milling machine using an NC machine. The through holes 16a to 16b are buckled to a radius 〇 6 and a radius of 7 coffee. Further, the hole processing of the through hole is stopped at the upper end of the hole portion 14. The hole portion 14 communicates with the outside air through the through holes 16a and 16b. After that, the first circuit pattern 17 of the upper substrate 11 is fixed to a predetermined position as shown in Fig. 2, and is connected by a bonding wire or the like. The second circuit pattern 19 of the lower substrate 12 is mainly used as a material contact electrode 35 (in the second drawing, n _ _ goods are not shown from A, B, C, and D), and is mounted on a printed circuit board or the like. Used at the time. [Simplified illustration of the drawing] A cross-sectional view of the circuit board. The bottom view of the circuit board (A) Fig. 1 is a hole portion of the present invention. Fig. 2 is a view showing a hole portion and a plan view (B) of the present invention. 3 is a cross-sectional view (1) to (8) illustrating a manufacturing step of a substrate on a circuit board having a hole portion according to the manufacturing method of the present invention. FIG. 4 is a view showing the circuit of the square hole portion of the present invention. Manufacture of the lower substrate (4) to (7) 321098 17 201026171 . Fig. 5 is a cross-sectional view (A) to (Fig. 5) showing the bonding step of the upper substrate and the lower substrate of the circuit substrate having the hole portion completed by the manufacturing method of the present invention E). Fig. 6 is a cross-sectional view (A) to (C) showing the final manufacturing steps of the circuit board having the hole portion completed by the manufacturing method of the present invention. Figure 7 is a cross-sectional view showing a conventional circuit substrate. Figure 8 is a cross-sectional view showing the MEMS circuit components. Figure 9 is a cross-sectional view showing a conventional mounting structure in which MEMS circuit components are mounted. [Description of main components] 10 circuit board 11 upper substrate 12 lower substrate 13 adhesive layer 14 holes 15a, 15b through-hole electrodes 16a, 16b through-holes 17 first circuit patterns 18a, 18b through-holes 19 second circuit patterns 20a, 20b Conductive foil 21a ' 21b Conductive foil 23 Circuit component 24 Pad 25 Connecting electrode 31 Leading hole 32, 33 Resistive layer 34 Primer resin 35 External electrode 51 Broken substrate 52 Separator 53 Air gap 54 Back plate electrode 55 Back plate 56 Solder Pad 57 Pad 60 Sealing member 61 Printed substrate 18 321098 201026171 62 MEMS microphone 63 CMOS1C 64 Case 65 Sound hole 70 Punching unit 100 First substrate 200 Second substrate 300 Third substrate 400 1C wafer 500 Conductive connection Member 600 Sealing member 700 Punching section ❿ 19 321098

Claims (1)

201026171 七、申請專利範圍: 1. 一種具有孔洞部之電路基板,其特徵為具備: 上基板; 任意之第1電路圖案,由前述上基板表面之導電箔 所形成; 黏接層,設在前述上基板之背面; 下基板; 任意之第2電路圖案,由前述下基板表面之導電箔 所形成; 孔洞,將前述下基板背面之導電箔予以去除所形 成; 絕緣層,設在該孔洞之周圍; 孔洞部,將前述上基板背面之前述黏接層與前述下 基板背面之前述絕緣層予以黏接,而由前述上基板、前 述下基板及前述絕緣層所包圍;及 貫穿孔(through hole)電極,將前述上基板之前述 第1電路圖案與前述下基板之前述第2電路圖案予以連 接。 2. 如申請專利範圍第1項之具有孔洞部之電路基板,其 中,在前述孔洞部設有貫通前述上基板或前述下基板之 貫通孔。 3. 如申請專利範圍第2項之具有孔洞部之電路基板,其 中,在前述貫通孔上配置電路元件之隔膜。 4. 一種具有孔洞部之電路基板之製造方法,其特徵為具 20 321098 201026171 備: 準備在兩面設有導電箔之上基板之步驟; 將前述上基板一方之前述導電箔進行#刻而形成 預定孔洞圖案之步驟; 準備在兩面設有導電箔之下基板之步驟; 將前述下基板一方之前述導電箔進行#刻而保留 作為預定孔洞部之部分之步驟; 將前述下基板之作為前述預定孔洞部之部分之前 述導電箔之周圍以絕緣層予以填埋,且將作為前述預定 孔洞部之部分之前述導電箔進行蝕刻而形成前述孔洞 部之步驟; 在前述上基板之前述預定孔洞圖案之周圍附著黏 接層之步驟;及 將前述上基板與下基板以前述黏接層予以黏合而 形成前述孔洞部之步驟。 5. —種具有孔洞部之電路基板之製造方法,其特徵為具 備: 準備在兩面設有導電箔之上基板之步驟; 將前述上基板一方之前述導電II進行餘刻而形成 預定孔洞圖案之步驟; 準備在兩面設有導電箔之下基板之步驟; 將前述下基板一方之前述導電箔進行蝕刻而保留 作為預定孔洞部之部分之步驟; 將前述下基板之作為前述預定孔洞部之部分之前 21 321098 201026171 述導電H之·以絕緣層料填埋,縣作為前述預定 孔洞部之部分之前述導電錢行關而形成前述孔洞 都士也碰· 在前述上基板之前述預定孔洞圖案之前述導電 之周圍附著黏接層之步驟; f前述上基板與下基板以前述黏接層予以黏合而 形成前述孔洞部之步驟; ,且形成貫201026171 VII. Patent application scope: 1. A circuit board having a hole portion, comprising: an upper substrate; an arbitrary first circuit pattern formed by a conductive foil on a surface of the upper substrate; an adhesive layer disposed on the foregoing a back surface of the upper substrate; a second substrate; any second circuit pattern formed by the conductive foil on the surface of the lower substrate; a hole formed by removing the conductive foil on the back surface of the lower substrate; and an insulating layer disposed around the hole The hole portion is formed by bonding the adhesive layer on the back surface of the upper substrate to the insulating layer on the back surface of the lower substrate, and is surrounded by the upper substrate, the lower substrate, and the insulating layer; and a through hole The electrode connects the first circuit pattern of the upper substrate and the second circuit pattern of the lower substrate. 2. The circuit board having a hole portion according to the first aspect of the invention, wherein the hole portion is provided with a through hole penetrating the upper substrate or the lower substrate. 3. The circuit board having a hole portion according to the second aspect of the patent application, wherein the separator of the circuit element is disposed on the through hole. 4. A method of manufacturing a circuit board having a hole portion, characterized in that it has a step of preparing a substrate on which conductive foil is provided on both sides; and forming the conductive foil on one side of the upper substrate to form a predetermined a step of forming a hole pattern; a step of providing a substrate under the conductive foil on both sides; a step of engraving the conductive foil on one side of the lower substrate as a portion of the predetermined hole portion; and forming the lower substrate as the predetermined hole a portion of the portion of the conductive foil surrounded by an insulating layer, and etching the conductive foil as a part of the predetermined hole portion to form the hole portion; surrounding the predetermined hole pattern of the upper substrate a step of attaching the adhesive layer; and a step of bonding the upper substrate and the lower substrate by the adhesive layer to form the hole portion. 5. A method of manufacturing a circuit board having a hole portion, comprising: preparing a substrate having a conductive foil on both surfaces; and forming a predetermined hole pattern by engraving the conductive layer on one of the upper substrates a step of preparing a substrate under the conductive foil on both sides; a step of etching the conductive foil on one side of the lower substrate to retain a portion as a predetermined hole portion; and forming the lower substrate as a portion of the predetermined hole portion 21 321098 201026171 The conductive H is filled with an insulating layer material, and the pre-existing money of the pre-determined hole portion of the prefecture is formed to form the hole and the aforementioned conductive pattern of the predetermined hole pattern in the upper substrate. a step of attaching an adhesive layer around the periphery; f: the step of bonding the upper substrate and the lower substrate by the adhesive layer to form the hole portion; 开少成貝通别述上基板及下基板之貫穿孔 穿孔電極之步驟; ^將前述上基板及下基板之面對外部之另一方導電 ^進行蝕刻而在前述上基板形成第丨電路圖案、在前述 基板形成第2電路圖案之步驟;及 之貫 、 形成從前述上基板或下基板到達前述空洞部 通孔之步驟。 。 =申請專利範圍第5項之具有孔洞部之電路基板之製a step of inserting a through-hole via electrode of the substrate and the lower substrate; and etching the other conductive layer facing the outside of the upper substrate and the lower substrate to form a second circuit pattern on the upper substrate; a step of forming a second circuit pattern on the substrate; and forming a step of reaching the hole through hole from the upper substrate or the lower substrate. . = The system for manufacturing a circuit board having a hole portion in the fifth application of the patent scope =方法,其中,具備繼前述之步驟而在前述第!電路 ―、配置電路元件之步驟。 ^申請專利範圍第6項之具有孔洞部之電路基板之製 =方法,其中,將具有隔膜之半導體元件作為前述電路 凡件,而組入於到達前述孔洞部之貫通孔之上。 321098 22= method, in which the above steps are followed by the above steps! Circuit - The steps to configure circuit components. The method of manufacturing a circuit board having a hole portion according to the sixth aspect of the invention, wherein the semiconductor element having the diaphragm is formed as a member of the circuit and is formed on the through hole that reaches the hole portion. 321098 22
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