CN114466512B - MEMS (micro-electromechanical systems) buried-capacitor buried-resistor packaging loading plate and manufacturing process thereof - Google Patents
MEMS (micro-electromechanical systems) buried-capacitor buried-resistor packaging loading plate and manufacturing process thereof Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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Abstract
The application relates to a MEMS (micro-electromechanical systems) embedded capacitor and resistor packaging loading plate and a manufacturing process thereof, comprising the following steps: preparing three core plates, namely a first core plate, a second core plate and a third core plate; an inner layer circuit of the first core board; pressing the first core plate; etching and film pressing of the second core plate; slotting of the film plate; an inner layer circuit of the third core board; pressing the third core plate; laminating the multi-layer plates; uncapping: drilling copper plating, outer layer circuit, welding prevention and surface treatment are carried out on the semi-finished product plate, and then laser uncovering treatment is carried out on the third core plate to form sound holes, so that the finished product packaging loading plate is obtained. The package carrier plate obtained by the application not only realizes the functions of buried capacitor and buried resistor, but also increases the volume of the back cavity without increasing the volume of the device, improves the sensitivity and the signal-to-noise ratio of the product, and accords with the development trend of miniaturization of the device.
Description
Technical Field
The application relates to an MEMS (micro-electromechanical systems) packaging loading plate, in particular to an MEMS embedded capacity and resistance packaging loading plate and a manufacturing process thereof.
Background
The development of MEMS (Microelectromechanical Systems) technology and technology, particularly silicon-based MEMS technology, has achieved miniaturization and low cost of many sensors (e.g., pressure sensors, accelerometers, gyroscopes, etc.). At present, a part of MEMS carrier plates are manufactured by adopting a mode of overlapping three layers of PCB plates, the three layers of PCB plates are laminated to form a cavity, a metal surface is plated on the second layer of PCB plate to form a shielding cavity, the packaging shielding effect is poor, the size of the back cavity is small, and the signal to noise ratio of a product is low.
Disclosure of Invention
In order to overcome the defects, the application provides a manufacturing process of the MEMS buried capacitance buried resistance packaging loading plate, and the packaging loading plate manufactured by the manufacturing process not only realizes functions of buried capacitance and buried resistance, but also increases the volume of a back cavity under the condition of not increasing the volume of a device, improves the sensitivity and the signal to noise ratio of a product, and accords with the development trend of miniaturization of the device.
The technical scheme adopted by the application for solving the technical problems is as follows:
a manufacturing process of a MEMS buried capacitor and resistor packaging loading plate comprises the following steps:
step 1: preparing three core plates, namely a first core plate, a second core plate and a third core plate, wherein the first core plate comprises a capacitance layer, a first copper foil layer and a second copper foil layer which are respectively arranged on the front side and the back side of the capacitance layer, the second core plate comprises a second insulation layer, a fourth copper foil layer and a fifth copper foil layer which are respectively arranged on the front side and the back side of the second insulation layer, and the third core plate comprises a third insulation layer, a sixth copper foil layer and a seventh copper foil layer which are respectively arranged on the front side and the back side of the third insulation layer;
step 2: inner layer circuit of first core: respectively performing dry film pressing, exposure, development, etching and film stripping treatment on the first copper foil layer and the second copper foil layer of the first core plate to obtain a first core plate with an inner layer circuit;
step 3: laminating the first core plate: sequentially overlapping a first core plate, a first insulating layer and a third copper foil layer, pressing the first core plate, the first insulating layer and the third copper foil layer into a first multilayer plate by a pressing machine, and respectively attaching two sides of the first insulating layer between the second copper foil layer and the third copper foil layer;
step 4: etching and film pressing of the second core plate: etching the fourth copper foil layer and the fifth copper foil layer on the second core plate, and attaching pure film layers on two sides of the second insulating layer to obtain a film plate;
step 5: grooving of the film plate: UV laser slotting is carried out on the film plate, and a back cavity is formed on the film plate;
step 6: inner layer circuit of the third core board: respectively performing dry film pressing, exposure, development, etching and film stripping treatment on a sixth copper foil layer and a seventh copper foil layer of the third core plate to obtain a third core plate with an inner layer circuit;
step 7: laminating a third core plate: sequentially overlapping a third core plate, a fourth insulating layer and a buried resistance copper foil layer, pressing into a second multilayer plate by using a press, and respectively attaching two sides of the fourth insulating layer between the sixth copper foil layer and the buried resistance copper foil layer;
step 8: laminating a multi-layer board: sequentially superposing a first multilayer board, a film board and a second multilayer board and pressing the first multilayer board, the film board and the second multilayer board into a semi-finished board by a press, and respectively attaching a seventh copper foil layer and a first copper foil layer to two sides of the film board;
step 9: uncapping: and (3) drilling copper plating, outer-layer circuit, welding prevention and surface treatment are carried out on the semi-finished product plate, and then laser uncovering treatment is carried out on the third core plate to form sound holes, so that the finished product packaging loading plate is obtained, and the sound holes are communicated with the back cavity.
Preferably, the inner layer circuit in the step 2 and the step 6 specifically includes the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines.
Preferably, the specific process parameters of the dry film pressing are as follows: the temperature is 110+/-2 ℃, the linear speed is 1.8+/-0.2 m/min, and the pressure is 6+/-0.2 kg/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the The energy grid during exposure is 6+/-1; the specific technological parameters during development are as follows: the linear velocity is 3.0+/-0.1 m/min, and the pressure is 1.3+/-0.3 kg/cm 2 The temperature was 30.+ -. 2 ℃.
Preferably, the laminating of the steps 3, 7 and 8 specifically includes the following steps:
(1) Pretreatment: acid washing: removing oxide on the surface of the copper foil layer by utilizing sulfuric acid; cleaning: hydrolyzing the grease into small molecular substances which are easy to dissolve in water by using a cleaning agent; presoaking: pre-soaking the inner layer plate by using brown liquid;
(2) Brown chemical: the surface of the copper foil layer is subjected to brown treatment by using brown liquid, so that the surface of the copper layer forms an uneven surface shape, and the contact area of the copper surface and resin is increased;
(3) Overlapping: sequentially stacking plates to be pressed together;
(4) Pressing: fusing and bonding the plates to be pressed into a multi-layer plate at high temperature and high pressure of a press;
(5) Post-treatment: drilling: imaging a plate target by utilizing X-rays, and drilling a positioning hole and a fool-proof hole required by a subsequent process on the target by using a drill bit; edge milling: and cutting and removing redundant rim charge by using a milling machine.
Preferably, the specific process parameters of the browning are as follows: the microetching rate is 1.2-1.6 mu m, H in the browning tank 2 O 2 The mass percentage concentration of (2) is 4.2-4.8%; the specific technological parameters of the lamination are as follows: the ice water pressure is 0.2+/-0.1 MPa, the vacuum degree is less than or equal to 40MPa, the oil outlet pressure is 0.2+/-0.1 MPa, and the oil inlet pressure is 0.5+/-0.1 MPa.
Preferably, in the step 4, the second core plate film pressing is performed by adopting a vacuum film sticking machine to stick a pure film layer, and the technological parameters during film pressing are as follows: the film pressing temperature is 70+/-5 ℃, the film pressing pressure is 0.6-0.7Mpa, and the vacuum reaching time is less than 20S.
Preferably, the specific process parameters of the film plate slotting in step 5 are: a laser: the purple crust second power is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, the processing times are 3 times, and the back cavity size error is controlled to be +/-0.02 mm; and baking the film plate after the back cavity is processed for 30+/-5 min in an environment with the temperature of 120+/-10 ℃, wherein the glue overflow amount of the film plate is less than 0.05mm.
Preferably, the specific process parameters of the uncovering in step 9 are: the laser power of the purple crust second laser is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, and the processing times are 2-3 times.
Preferably, the embedded resistance copper foil layer is a nickel-phosphorus alloy embedded resistance copper foil layer, and the square resistance of the embedded resistance copper foil is 25 omega, 40 omega, 50 omega or 100 omega.
The application also provides a buried-capacitor buried-resistor packaging carrier plate which is prepared by adopting the manufacturing process of the MEMS buried-capacitor buried-resistor packaging carrier plate.
The beneficial effects of the application are as follows:
1) In the application, the back cavity is formed by slotting on the substrate, namely the insulating layer, so that the volume of the back cavity is increased; the hollow structure is processed by adopting UV laser, so that the dimensional error of the hollow back cavity can be controlled to be +/-0.02 mm; firstly, attaching a pure film on a substrate, and then carrying out laser grooving, so that the alignment degree of the film and the hollow substrate is improved; the pure film has low fluidity, and after UV processing, the film is baked, and the overflow amount can be controlled below 0.05 mm; the sound hole is formed through a laser uncovering process, so that the communication between the hollow structure, namely the back cavity, and the outside is realized;
2) The finished product package loading plate obtained by the application not only realizes the functions of buried capacitance and buried resistance, but also increases the volume of the back cavity under the condition of not increasing the volume of the device, improves the sensitivity and the signal-to-noise ratio of the product, and accords with the development trend of device miniaturization; the back cavity of the packaging loader can be opened inwards according to requirements, and the chip can be placed in the back cavity without occupying the volume of the back cavity right below the sound hole, so that the performances of sensitivity, signal-to-noise ratio and the like of the product are greatly improved.
Drawings
FIG. 1 is a schematic illustration of the structure of a finished package carrier in accordance with the present application;
FIG. 2 is a schematic view of a first core plate according to the present application;
FIG. 3 is a schematic view of the first core circuit of the present application;
FIG. 4 is a schematic structural view of a first multi-layer board according to the present application;
FIG. 5 is a schematic view of a second core plate according to the present application;
FIG. 6 is a schematic view of a film plate according to the present application;
FIG. 7 is a schematic view of the structure of the grooved film plate of the present application;
FIG. 8 is a schematic view of a third core plate according to the present application;
FIG. 9 is a schematic diagram of a third chip circuit according to the present application;
FIG. 10 is a schematic diagram of a second multi-layer board according to the present application;
FIG. 11 is a schematic view of the structure of a semifinished sheet according to the application;
in the figure: 10-a first core board, 11-a capacitor layer, 12-a first copper foil layer, 13-a second copper foil layer, 14-a first insulating layer, 15-a third copper foil layer and 16-a first multilayer board;
20-second core board, 21-second insulating layer, 22-fourth copper foil layer, 23-fifth copper foil layer, 24-pure film layer and 25-film board;
30-third core board, 31-third insulating layer, 32-sixth copper foil layer, 33-seventh copper foil layer, 34-fourth insulating layer, 35-buried resistance copper foil layer, 36-second multilayer board;
40-packaging carrier plate, 41-back cavity and 42-sound hole.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically shown or described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Examples: as shown in fig. 1-11, a process for manufacturing a MEMS buried capacitor and resistor package carrier includes the following steps:
step 1: preparing three core boards, namely a first core board 10, a second core board 20 and a third core board 30, wherein, as shown in fig. 2, the first core board 10 comprises a capacitor layer 11, a first copper foil layer 12 and a second copper foil layer 13 which are respectively arranged on the front side and the back side of the capacitor layer, as shown in fig. 5, the second core board 20 comprises a second insulating layer 21, a fourth copper foil layer 22 and a fifth copper foil layer 23 which are respectively arranged on the front side and the back side of the second insulating layer, as shown in fig. 8, the third core board 30 comprises a third insulating layer 31, a sixth copper foil layer 32 and a seventh copper foil layer 33 which are respectively arranged on the front side and the back side of the third insulating layer;
step 2: inner layer circuit of the first core board 10: as shown in fig. 3, the first copper foil layer 12 and the second copper foil layer 13 of the first core board are respectively subjected to dry film pressing, exposure, development, etching and film stripping treatment to obtain a first core board 10 having an inner layer circuit;
step 3: lamination of the first core board 10: as shown in fig. 4, the first core board 10, the first insulating layer 14 and the third copper foil layer 15 are sequentially laminated and pressed into a first multilayer board 16 by a press, and two sides of the first insulating layer 14 are respectively attached between the second copper foil layer 13 and the third copper foil layer 15; the first multilayer board 16 is a three-layer board, and sequentially comprises a first copper foil layer 12, a capacitor layer 11, a second copper foil layer 13, a first insulating layer 14 and a third copper foil layer 15;
step 4: etching and laminating of the second core plate 20: as shown in fig. 6, the fourth copper foil layer 22 and the fifth copper foil layer 23 on the second core board are etched away, and a pure film layer 24 is attached to both sides of the second insulating layer 21 to obtain a film board 25;
step 5: grooving of the film plate: as shown in fig. 7, UV laser grooving is performed on the film plate, and a back cavity 41 is formed on the film plate; etching the double-sided copper foil in the second core plate, attaching pure film layers with low fluidity on two sides of the second insulating layer to form film plates, and laser-forming a hollow structure on the film plates to form a back cavity with larger volume;
step 6: inner layer line of the third core board 30: as shown in fig. 9, the sixth copper foil layer 32 and the seventh copper foil layer 33 of the third core board are respectively subjected to dry film pressing, exposure, development, etching, and film stripping treatment to obtain a third core board 30 having an inner layer wiring;
step 7: lamination of the third core plate 30: as shown in fig. 10, the third core board 30, the fourth insulating layer 34 and the copper foil layer 35 with embedded resistance are sequentially laminated and pressed into a second multilayer board 36 by a press, and two sides of the fourth insulating layer 34 are respectively attached between the sixth copper foil layer 32 and the copper foil layer 35 with embedded resistance; the second multilayer board 36 is a three-layer board, and is sequentially a buried resistive copper foil layer 35, a fourth insulating layer 34, a sixth copper foil layer 32, a third insulating layer 31 and a seventh copper foil layer 33;
step 8: laminating a multi-layer board: as shown in fig. 11, the first multilayer board 16, the film board 25 and the second multilayer board 36 are sequentially laminated and pressed into a semi-finished board by a press, and the seventh copper foil layer 33 and the first copper foil layer 12 are respectively attached to both sides of the film board 25;
step 9: uncapping: after the semi-finished board is subjected to drilling copper plating, outer layer circuit, welding prevention and surface treatment, the third core board 30 is subjected to laser uncovering treatment to form sound holes 42, and the finished package carrier board 40 is obtained, wherein the sound holes 42 are communicated with the back cavity 41. The semi-finished board is drilled with copper to form via holes for inter-layer conduction, the buried copper foil layer 35 and the third copper foil layer 15 are subjected to outer layer circuit treatment, the solder resist surface treatment is performed, and then the cover is opened to obtain the finished package carrier board 40, as shown in fig. 1, the finished package carrier board 40 is sequentially the buried copper foil layer 35, the fourth insulating layer 34, the sixth copper foil layer 32, the third insulating layer 31, the seventh copper foil layer 33, the film board 25, the first copper foil layer 12, the capacitor layer 11, the second copper foil layer 13, the first insulating layer 14 and the third copper foil layer 15. Therefore, the finished product packaging loading plate not only realizes the functions of buried capacitor and buried resistor, but also increases the volume of the back cavity under the condition of not increasing the volume of the device, improves the sensitivity and the signal-to-noise ratio of the product, and accords with the development trend of device miniaturization.
The inner layer circuit in the step 2 and the step 6 specifically comprises the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution; cleaning the plate surface to remove attachments such as stains, oxides and the like; the copper surface can be roughened by microetching with sulfuric acid solution, the adhesive force with the dry film is increased, and the main chemical reaction is as follows: cu+H 2 O 2 →CuO+H 2 O；CuO+H 2 SO 4 →CuSO 4 +H 2 O; the copper foil layer can be an inner copper foil layer, a secondary outer copper foil layer and an outer copper foil layer, which are the same as below;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode; a photosensitive dry film is pressed on the copper surface layer and used for subsequent image transfer, and after the dry film is heated, the dry film has fluidity and a certain filling property, and is attached to the surface of the board in a hot pressing mode by utilizing the characteristic;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film; an LDI exposure machine (Laser Direcl Imaging laser direct imaging) utilizes Ultraviolet (UV) energy to complete pattern transfer;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film; the exposed dry film does not react with the developer, and the development main chemical reaction: R-COOH+Na 2 CO 3 →R-COO-Na + +2NaHCO 3 ；
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit; the main chemical reaction: 3Cu+NaClO 3 +6HCl→3CuCl 2 +3H 2 O+NaCl；
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines. AOI is Automatic Optical Inspection automated optical inspection), the Genesis system processes the CAM data of the original design line into reference data for inspection and outputs to the AOI system. The AOI system uses the optical principle to judge defects such as short circuit, circuit break, notch and the like by comparing the difference between the etched circuit and the designed circuit.
The specific process parameters of the dry film pressing are as follows: the temperature is 110+/-2 ℃, the linear speed is 1.8+/-0.2 m/min, and the pressure is 6+/-0.2 kg/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the The energy grid during exposure is 6+/-1; the specific technological parameters during development are as follows: the linear velocity is 3.0+/-0.1 m/min, and the pressure is 1.3+/-0.3 kg/cm 2 The temperature was 30.+ -. 2 ℃.
The pressing steps 3, 7 and 8 specifically comprise the following steps:
(1) Pretreatment: acid washing: removing oxide on the surface of the copper foil layer by utilizing sulfuric acid; cleaning: hydrolysis of oils and fats to small water-soluble molecules using detergentsA substance; presoaking: pre-soaking the inner layer plate by using brown liquid; the pretreatment is for preparing the browning process; acid washing: the chemical reaction of sulfuric acid and CuO is utilized to remove oxides on the copper surface, and the main chemical reaction is as follows: cuO+H 2 SO 4 →CuSO 4 +H 2 O; cleaning by reaction of cleaning agent with oil and fat, and main chemical reaction is KOH+R 1 COOH→RNHCOR 1 +H 2 O; the prepreg enables the board surface to have a similar composition to the browning liquid and prevents water from damaging the browning liquid, wherein the mass percentage content of the prepreg tank BR616 is 1.2-2.8%;
(2) Brown chemical: the surface of the copper foil layer is subjected to brown treatment by using brown liquid, so that the surface of the copper layer forms an uneven surface shape, and the contact area of the copper surface and resin is increased; the brown oxide liquid is sulfuric acid and hydrogen peroxide, the sulfuric acid and the hydrogen peroxide are utilized to microetch the copper surface, and a layer of extremely thin, uniform and consistent organic metal conversion film is generated at the same time of microetching, and the main purpose of brown oxide is as follows: coarsening copper surface, increasing surface area contacted with PP sheet (pre preg prepreg is sheet material impregnated with resin and solidified to intermediate degree), improving adhesion with PP sheet, preventing delamination; the wettability of the copper surface and the flowing resin is increased; passivating the copper surface, and blocking the action of ammonia substances generated by polymerization and hardening of epoxy resin on the copper surface in the pressing plate process, wherein the ammonia substances attack the copper surface to generate water vapor, so that the explosion plate is caused; wherein the insulating layer is a PP sheet;
(3) Overlapping: sequentially stacking plates to be pressed together;
(4) Pressing: fusing and bonding the plates to be pressed into a multi-layer plate at high temperature and high pressure of a press;
(5) Post-treatment: drilling: imaging a plate target by utilizing X-rays, and drilling a positioning hole and a fool-proof hole required by a subsequent process on the target by using a drill bit; edge milling: and cutting and removing redundant rim charge by using a milling machine.
The specific process parameters of the browning are as follows: the microetching rate is 1.2-1.6 mu m, H in the browning tank 2 O 2 The mass percentage concentration of (2) is 4.2-4.8%; the specific technological parameters of the lamination are as follows: the ice water pressure is 0.2 plus or minus 0.1MPa, the vacuum degree is less than or equal to 40mPa, and the oil outlet pressure is 0.2 plus or minus 0.1The MPa and the oil inlet pressure are 0.5+/-0.1 MPa.
In step 4, the second core plate 20 is laminated with the pure film layer 24 by a vacuum laminator, and the technological parameters during lamination are as follows: the film pressing temperature is 70+/-5 ℃, the film pressing pressure is 0.6-0.7Mpa, and the vacuum reaching time is less than 20S. The pure film layer is prepared by adopting low-fluidity colloid.
The specific technological parameters of the slotting of the film plate in the step 5 are as follows: a laser: the purple crust second power is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, the processing times are 3 times, and the back cavity size error is controlled to be +/-0.02 mm; and baking the film plate 25 after the back cavity is processed for 30+/-5 min at the temperature of 120+/-10 ℃, wherein the glue overflow amount of the film plate is less than 0.05mm. Forming a back cavity on a film plate in a UV laser mode, wherein the size of the back cavity can be determined according to actual requirements; preferably, the baking temperature of the film plate is 120 ℃ and the baking time is 30min, because the pure film adopts low-fluidity colloid, and the film plate is further baked, the glue overflow amount can be controlled below 0.05mm, and the stability of the back cavity is ensured.
The specific technological parameters of uncovering in the step 9 are as follows: the laser power of the purple crust second laser is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, and the processing times are 2-3 times. In the step 9, the process flow of the outer layer circuit and the inner layer circuit is the same, and the discussion is not repeated here; the drilling copper plating mainly comprises desmear, chemical copper and electroplated copper, the anti-welding mainly comprises pretreatment, screen printing and pre-baking, exposure, development, post-curing and UV curing, and the surface treatment, namely electroplated nickel-gold, is a common technology in the field and is not described in detail herein.
The embedded resistance copper foil layer 35 is a nickel-phosphorus alloy embedded resistance copper foil layer, and the square resistance of the embedded resistance copper foil is 25 omega, 40 omega, 50 omega or 100 omega.
The embedded capacitor and resistor packaging carrier plate is manufactured by adopting the manufacturing process of the MEMS embedded capacitor and resistor packaging carrier plate. As shown in fig. 1, the finished package carrier 40 is sequentially a buried resistive copper foil layer 35, a fourth insulating layer 34, a sixth copper foil layer 32, a third insulating layer 31, a seventh copper foil layer 33, a film board 25, a first copper foil layer 12, a capacitor layer 11, a second copper foil layer 13, a first insulating layer 14 and a third copper foil layer 15, a back cavity 41 is arranged on the film board 25, an acoustic hole 42 is formed above the back cavity, the back cavity is communicated with the outside through the acoustic hole, and compared with a traditional three-layer board, the back cavity of the traditional three-layer board is located under the acoustic hole, a chip must be arranged in the back cavity under the acoustic hole, so that the size of the back cavity is affected, the performance of the product is affected, the back cavity of the package carrier can be opened inwards according to requirements, the chip can be placed in the internal back cavity, the size of the back cavity is not occupied under the acoustic hole, and the sensitivity, the signal to noise ratio and other performances of the product are greatly improved.
It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A manufacturing process of a MEMS buried capacitor and resistor packaging loading plate is characterized by comprising the following steps of: the method comprises the following steps:
step 1: preparing three core boards, namely a first core board (10), a second core board (20) and a third core board (30), wherein the first core board (10) comprises a capacitor layer (11), a first copper foil layer (12) and a second copper foil layer (13) which are respectively arranged on the front side and the back side of the capacitor layer, the second core board (20) comprises a second insulating layer (21), a fourth copper foil layer (22) and a fifth copper foil layer (23) which are respectively arranged on the front side and the back side of the second insulating layer, the third core board (30) comprises a third insulating layer (31), and a sixth copper foil layer (32) and a seventh copper foil layer (33) which are respectively arranged on the front side and the back side of the third insulating layer;
step 2: inner layer circuit of first core board (10): respectively performing dry film pressing, exposure, development, etching and film stripping treatment on the first copper foil layer (12) and the second copper foil layer (13) of the first core plate to obtain a first core plate (10) with an inner layer circuit;
step 3: laminating the first core board (10): sequentially superposing a first core plate (10), a first insulating layer (14) and a third copper foil layer (15) and pressing the first core plate, the first insulating layer (14) and the third copper foil layer (15) into a first multilayer plate (16) by a press, and respectively attaching two sides of the first insulating layer (14) between the second copper foil layer (13) and the third copper foil layer (15);
step 4: etching and film pressing of the second core plate (20): etching the fourth copper foil layer (22) and the fifth copper foil layer (23) on the second core plate, and attaching pure film layers (24) on two sides of the second insulating layer (21) to obtain a film plate (25);
step 5: grooving of the film plate: UV laser grooving is carried out on the film plate, and a back cavity (41) is formed on the film plate;
step 6: inner layer circuit of the third core board (30): respectively performing dry film pressing, exposure, development, etching and film stripping treatment on a sixth copper foil layer (32) and a seventh copper foil layer (33) of the third core plate to obtain a third core plate (30) with an inner layer circuit;
step 7: pressing the third core plate (30): sequentially superposing a third core plate (30), a fourth insulating layer (34) and a buried resistance copper foil layer (35) and pressing the third core plate, the fourth insulating layer (34) and the buried resistance copper foil layer into a second multilayer plate (36) by a pressing machine, wherein two sides of the fourth insulating layer (34) are respectively attached between the sixth copper foil layer (32) and the buried resistance copper foil layer (35);
step 8: laminating a multi-layer board: sequentially superposing a first multilayer board (16), a film board (25) and a second multilayer board (36) and pressing the first multilayer board, the film board (25) is pressed into a semi-finished board by a press, and a seventh copper foil layer (33) and a first copper foil layer (12) are respectively attached to two sides of the film board (25);
step 9: uncapping: and (3) drilling copper plating, outer-layer circuit, welding prevention and surface treatment are carried out on the semi-finished product plate, and then laser uncovering treatment is carried out on the third core plate (30) to form sound holes (42), so that the finished product package loading plate (40) is obtained, and the sound holes (42) are communicated with the back cavity (41).
2. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: the inner layer circuit in the step 2 and the step 6 specifically comprises the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines.
3. The process for manufacturing the MEMS buried resistive package carrier according to claim 2, wherein: the specific process parameters of the dry film pressing are as follows: the temperature is 110+/-2 ℃, the linear speed is 1.8+/-0.2 m/min, and the pressure is 6+/-0.2 kg/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the The energy grid during exposure is 6+/-1; the specific technological parameters during development are as follows: the linear velocity is 3.0+/-0.1 m/min, and the pressure is 1.3+/-0.3 kg/cm 2 The temperature was 30.+ -. 2 ℃.
4. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: the pressing steps 3, 7 and 8 specifically comprise the following steps:
(1) Pretreatment: acid washing: removing oxide on the surface of the copper foil layer by utilizing sulfuric acid; cleaning: hydrolyzing the grease into small molecular substances which are easy to dissolve in water by using a cleaning agent; presoaking: pre-soaking the inner layer plate by using brown liquid;
(2) Brown chemical: the surface of the copper foil layer is subjected to brown treatment by using brown liquid, so that the surface of the copper layer forms an uneven surface shape, and the contact area of the copper surface and resin is increased;
(3) Overlapping: sequentially stacking plates to be pressed together;
(4) Pressing: fusing and bonding the plates to be pressed into a multi-layer plate at high temperature and high pressure of a press;
(5) Post-treatment: drilling: imaging a plate target by utilizing X-rays, and drilling a positioning hole and a fool-proof hole required by a subsequent process on the target by using a drill bit; edge milling: and cutting and removing redundant rim charge by using a milling machine.
5. The process for manufacturing the MEMS buried resistive package carrier according to claim 4, wherein: the specific process parameters of the browning are as follows: the microetching rate is 1.2-1.6 mu m, H in the browning tank 2 O 2 The mass percentage concentration of (2) is 4.2-4.8%; the specific technological parameters of the lamination are as follows: the ice water pressure is 0.2+/-0.1 MPa, the vacuum degree is less than or equal to 40MPa, the oil outlet pressure is 0.2+/-0.1 MPa, and the oil inlet pressure is 0.5+/-0.1 MPa.
6. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: in the step 4, the second core plate (20) is laminated with the pure film layer (24) by adopting a vacuum laminator, and the technological parameters during film lamination are as follows: the film pressing temperature is 70+/-5 ℃, the film pressing pressure is 0.6-0.7Mpa, and the vacuum reaching time is less than 20S.
7. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: the specific technological parameters of the slotting of the film plate in the step 5 are as follows: a laser: the purple crust second power is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, the processing times are 3 times, and the back cavity size error is controlled to be +/-0.02 mm; and baking the film plate (25) after the back cavity is processed for 30+/-5 min in an environment with the temperature of 120+/-10 ℃, wherein the glue overflow amount of the film plate is less than 0.05mm.
8. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: the specific technological parameters of uncovering in the step 9 are as follows: the laser power of the purple crust second laser is 10W, the frequency is 1000KHZ, the processing speed is 1500mm/s, and the processing times are 2-3 times.
9. The process for manufacturing the MEMS buried resistive package carrier according to claim 1, wherein: the embedded resistance copper foil layer (35) is a nickel-phosphorus alloy embedded resistance copper foil layer, and the square resistance of the embedded resistance copper foil is 25 omega, 40 omega, 50 omega or 100 omega.
10. The utility model provides a bury and hold encapsulation carrier plate that buries resistance which characterized in that: the MEMS buried resistive package carrier is fabricated by a process as recited in any one of claims 1-9.
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