CN114206001B - High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof - Google Patents
High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof Download PDFInfo
- Publication number
- CN114206001B CN114206001B CN202111447442.7A CN202111447442A CN114206001B CN 114206001 B CN114206001 B CN 114206001B CN 202111447442 A CN202111447442 A CN 202111447442A CN 114206001 B CN114206001 B CN 114206001B
- Authority
- CN
- China
- Prior art keywords
- layer
- copper foil
- foil layer
- copper
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000011068 loading method Methods 0.000 title abstract description 8
- 238000005553 drilling Methods 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000003825 pressing Methods 0.000 claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 238000011161 development Methods 0.000 claims abstract description 16
- 238000011049 filling Methods 0.000 claims abstract description 16
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 352
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 248
- 239000011889 copper foil Substances 0.000 claims description 171
- 229910052802 copper Inorganic materials 0.000 claims description 77
- 239000010949 copper Substances 0.000 claims description 77
- 239000000758 substrate Substances 0.000 claims description 68
- 239000007788 liquid Substances 0.000 claims description 33
- 239000000126 substance Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 27
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 26
- 239000003814 drug Substances 0.000 claims description 24
- 238000006243 chemical reaction Methods 0.000 claims description 23
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 18
- 238000004140 cleaning Methods 0.000 claims description 18
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 16
- 238000005507 spraying Methods 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 11
- 239000003292 glue Substances 0.000 claims description 9
- 238000007731 hot pressing Methods 0.000 claims description 8
- 239000003973 paint Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 claims description 6
- 230000000379 polymerizing effect Effects 0.000 claims description 6
- 238000007127 saponification reaction Methods 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- 239000012459 cleaning agent Substances 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 4
- 238000003848 UV Light-Curing Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000001723 curing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 239000004519 grease Substances 0.000 claims description 3
- 230000003301 hydrolyzing effect Effects 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000003801 milling Methods 0.000 claims description 3
- 238000005554 pickling Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 239000002893 slag Substances 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 3
- 238000012719 thermal polymerization Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000000465 moulding Methods 0.000 abstract 1
- 238000003475 lamination Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
Abstract
The application relates to a high-pressure-resistant MEMS packaging loading plate and a manufacturing process thereof, wherein the manufacturing process comprises the following steps: cutting and inner layer circuit: dry film pressing, exposure, development, etching and film removing treatment, pressing, mechanical drilling, laser drilling, hole filling and outer layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment, and performing solder resist and molding; the buried capacitor four-layer board obtained through the manufacturing process has the double-layer capacitor layers which are connected in series, so that the risk of breakdown short circuit caused by insufficient withstand voltage of a finished PCB (printed circuit board) due to the use of an ultra-high capacitor density material is solved, the high voltage resistance of the PCB is enhanced, and the credit resistance of the product is greatly enhanced.
Description
Technical Field
The application relates to a packaging loading plate, in particular to a high-voltage-resistant MEMS packaging loading plate and a manufacturing process thereof.
Background
With the development of electronic technology and the demands of people for miniaturization and high integration of electronic products, the capacitance of the MEMS product of the circuit board has great influence on the performance of the printed circuit board, and the dielectric layer of the material with high capacitance density is extremely thin, so that the capacitance voltage endurance becomes one of the important problems in the use and manufacturing process of the circuit board product. The conventional 4-layer MEMS package carrier is stacked as follows: the buried plate is firstly made into a single-sided inner layer circuit and then is pressed with a copper foil single side, at this time, the buried plate is 3 layers, then the other side circuit of the buried plate is made through an inner layer secondary circuit, at this time, the circuit surface is pressed with the copper foil single side, at this time, the buried plate is 4 layers, and finally, the finished plate is obtained through an outer layer circuit and subsequent procedures. The existing finished plate has the following problems: when the ultra-high capacitance density buried capacitor material is used, the thickness of the buried capacitor material is reduced along with the increase of capacitance density, and meanwhile, the voltage withstand born by the smaller thickness of the buried capacitor material is lower, so that the risk that voltage breakdown is easily caused by a PCB finished product exists.
Disclosure of Invention
In order to overcome the defects, the application provides a manufacturing process of a high-voltage-resistant high-capacitance MEMS packaging loading plate, wherein two buried capacitance substrates are directly pressed to form a buried capacitance four-layer plate in the manufacturing process, so that the high-voltage-resistant MEMS packaging loading plate with a buried capacitance material cross-layer symmetrical design is obtained, and the risk of product breakdown short circuit caused by insufficient voltage resistance under the condition of using an ultrahigh-capacitance density material is avoided.
The technical scheme adopted by the application for solving the technical problems is as follows:
a manufacturing process of a high-voltage-resistant MEMS packaging carrier plate comprises the following steps:
step 1: cutting: cutting the buried capacitor substrate into a certain size and forming two buried capacitor substrates, wherein the two buried capacitor substrates are respectively defined as a first buried capacitor substrate and a second buried capacitor substrate, the first buried capacitor substrate is provided with a first capacitor layer, a first copper foil layer and a second copper foil layer which are respectively arranged on the front side and the back side of the first capacitor layer, and the second buried capacitor substrate is provided with a second capacitor layer, a third copper foil layer and a fourth copper foil layer which are respectively arranged on the front side and the back side of the second capacitor layer;
step 2: inner layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment on the second copper foil layer of the first buried substrate and the third copper foil layer of the second buried substrate respectively to obtain a first buried substrate and a second buried substrate with inner-layer circuits;
step 3: pressing: sequentially overlapping the first embedded substrate, the PP layer and the second embedded substrate, pressing the overlapped first embedded substrate, the PP layer and the second embedded substrate by using a press to form an embedded four-layer board, and respectively attaching the second copper foil layer and the third copper foil layer to the front surface and the back surface of the PP layer;
step 4: mechanical drilling, laser drilling and hole filling:
mechanical drilling: drilling a plurality of positioning holes on the first copper foil layer by utilizing a drill bit according to the circuit layout requirement;
laser drilling: laser machine utilizing CO 2 Laser drilling holes with required size at the positioning holes by laser, namely performing laser drilling from the first copper foil layer by adopting single-sided laser drilling to form the holes, wherein the holes sequentially pass through the first copper foil layer, the first capacitor layer, the second copper foil layer and the PP layer without burning through the third copper foil layer;
hole filling: removing glue residues, chemical copper and electroplating copper in the slotted holes to form through holes, so as to obtain buried four-layer plates with inter-layer pattern lines mutually communicated;
step 5: an outer layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment on the first copper foil layer and the fourth copper foil layer of the buried four-layer board to obtain the buried four-layer board with the outer layer circuit, and etching the first copper foil layer corresponding to the through hole into an independent PAD, wherein the PAD does not participate in the conduction of other circuits;
step 6: and (3) resistance welding: forming a solder resist ink layer on the surface of the buried four-layer board through solder resist pretreatment, printing, pre-baking, exposure, development and post-baking to obtain a finished product carrier board, wherein an independent PAD (PAD) corresponding to the through hole and positioned on the first copper foil layer is covered under the solder resist ink layer;
step 7: and (3) forming: finally milling, electrically measuring, checking and packaging to obtain the finished product for shipment. .
Preferably, the step 2 of inner layer circuit specifically includes the following steps:
(1) Pretreatment: cleaning the substrate by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the second copper foil layer and the third copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film to the surfaces of the second copper foil layer and the third copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Leg mold: spraying NaOH or KOH liquid medicine on the board surface through a film stripping machine, removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of the inner-layer circuit to obtain a first buried substrate and a second buried substrate with the inner-layer circuit;
(7) AOI: the AOI system checks the inner layer line on the copper surface against the difference between the etched inner layer line and the original design line.
Preferably, the step 3 of pressing specifically includes the following steps:
(1) Pretreatment: acid washing: removing oxide on the surfaces of the second copper foil layer and the third copper foil layer by using sulfuric acid solution; cleaning: hydrolyzing the grease into small molecular substances which are easy to dissolve in water by using a cleaning agent; presoaking: pre-soaking the inner layer plate by using brown liquid;
(2) Brown chemical: the surface of the second copper foil layer and the surface of the third copper foil layer are subjected to brown treatment by using brown liquid, so that the surface of the copper is in an uneven surface shape, and the contact area of the copper surface and resin is increased;
(3) Overlapping: sequentially overlapping the first buried capacitor substrate, the PP layer and the second buried capacitor substrate, wherein the PP layer is positioned between the second copper foil layer and the third copper foil layer;
(4) Pressing: and fusing and bonding the first buried substrate, the PP layer and the second buried substrate at high temperature and high pressure of the press to form a buried four-layer plate.
Preferably, the hole filling in the step 4 specifically includes the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the slot hole through chemical action;
(3) Electroplating copper: plating a copper electroplating layer on the surface of the chemical copper layer in an electroplating manner to form the via hole.
Preferably, in the step 4, specific process parameters are as follows:
in mechanical drilling, a UC double-edge cutter with the diameter of 0.350mm is utilized to drill a cutter, the feeding speed is controlled below 1.2m/min, the cutter returning speed is controlled below 15m/min, and a hole with the diameter of 0.350mm is drilled under the condition that the rotating speed is 90-120 kprm/min;
in laser drilling, the pulse width is 5-12ms, the energy is 2-7mj, the number of the pulses is 3-4, the MASK is 1.5-2.5, and the aperture of the laser drilling is 75-120 mu m;
in the hole filling, the aspect ratio of the hole is controlled to be more than 0.8:1, the dishing degree is controlled to be less than 20 mu m, and the copper thickness tolerance is +/-20%.
Preferably, the outer layer circuit in the step 5 specifically includes the following steps:
(1) Pretreatment: cleaning the buried four-layer board by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the first copper foil layer and the fourth copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering photosensitive dry films to the surfaces of the first copper foil layer and the fourth copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) And (3) film removal: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of an outer layer circuit to obtain a buried four-layer board with the outer layer circuit;
(7) AOI: the AOI system checks the outer layer of lines on the copper surface against the difference between the etched outer layer of lines and the original design lines.
Preferably, the step 6 of solder resist specifically includes the following steps:
(1) Pretreatment: removing the oxide on the copper surface of the etched buried four-layer plate, pickling and drying after microetching;
(2) Screen printing and pre-baking: uniformly coating green oil on the surfaces of the first copper foil layer and the fourth copper foil layer through screen printing, and locally curing the green oil through pre-baking;
(3) Exposure: defining a green paint windowing part by an LDI exposure machine, and utilizing ultraviolet irradiation to polymerize and bond a photosensitive part and strengthen a structure;
(4) Developing: the unexposed photosensitive ink is dissolved and removed by a developing solution to achieve the aim of development;
(5) Post bake and UV cure: the green paint is fully reacted by utilizing heat baking and UV curing equipment to accelerate thermal polymerization reaction, and is further bonded and strengthened to form a stable reticular structure, so that the solder resist ink layer is thoroughly cured, and certain resistance and chemical resistance are achieved.
The application also provides a high-pressure-resistant MEMS packaging carrier plate, which is prepared by adopting the manufacturing process.
Preferably, the packaging carrier plate comprises a first copper foil layer, a first capacitor layer, a second copper foil layer, a PP layer, a third copper foil layer, a second capacitor layer and a fourth copper foil layer which are sequentially arranged, wherein the first copper foil layer and the fourth copper foil layer are covered with a solder resist ink layer, and a through hole is formed between the first copper foil layer and the third copper foil layer.
The beneficial effects of the application are as follows: according to the application, two buried substrates are directly pressed into the buried four-layer board through an inner layer circuit, pressing, mechanical drilling, laser drilling, hole filling, an outer layer circuit, solder resist and forming, compared with the traditional four-layer MEMS (micro-electromechanical system) package carrier board stacking structure, the packaging carrier board with the buried material in a cross-layer symmetrical design is obtained, and the first capacitance layer and the second capacitance layer in the packaging carrier board are mutually connected in series through the through holes, so that the risk of breakdown short circuit caused by insufficient withstand voltage of a finished PCB (printed circuit board) due to the use of an ultrahigh capacitance density material is solved, the high voltage resistance of the PCB is enhanced, and the product letter resistance is greatly enhanced; in addition, the double-sided symmetrical lamination design is adopted in the process, so that only one lamination operation is needed in the whole process, the complexity of the product flow is effectively reduced, and the production efficiency of the product is improved.
Drawings
FIG. 1 is a schematic view of a package carrier according to the present application;
FIG. 2 is a schematic diagram of the lamination process of the present application;
FIG. 3 is a schematic diagram of a structure of the buried four-layer board after drilling;
FIG. 4 is a schematic diagram of the structure of the circuit of the outer layer of the buried four-layer board in the application;
in the figure: 10-first buried substrate, 11-first capacitor layer, 12-first copper foil layer, 13-second copper foil layer, 20-second buried substrate, 21-second capacitor layer, 22-third copper foil layer, 23-fourth copper foil layer, 30-PP layer, 40-buried four-layer board, 41-via hole, 42-solder resist ink layer.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically shown or described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Examples: as shown in fig. 1-4, a process for manufacturing a high voltage MEMS package carrier includes the steps of:
step 1: cutting: cutting the buried substrate into a certain size and forming two buried substrates, namely a first buried substrate 10 and a second buried substrate 20, wherein the first buried substrate 10 is provided with a first capacitance layer 11, a first copper foil layer 12 and a second copper foil layer 13 which are respectively arranged on the front side and the back side of the first capacitance layer, and the second buried substrate 20 is provided with a second capacitance layer 21, a third copper foil layer 22 and a fourth copper foil layer 23 which are respectively arranged on the front side and the back side of the second capacitance layer;
step 2: inner layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment on the second copper foil layer 13 of the first buried substrate 10 and the third copper foil layer 22 of the second buried substrate 20 respectively to obtain a first buried substrate 10 and a second buried substrate 20 with inner-layer circuits;
step 3: pressing: as shown in fig. 2, the first buried substrate 10, the PP layer 30 and the second buried substrate 20 are sequentially stacked, the stacked first buried substrate 10, PP layer 30 and second buried substrate 20 are pressed together by a press to form a buried four-layer board 40, and the second copper foil layer 13 and the third copper foil layer 22 are respectively attached to the front and back sides of the PP layer 30;
step 4: mechanical drilling, laser drilling and hole filling:
mechanical drilling: drilling a plurality of positioning holes on the first copper foil layer 12 by using a drill bit according to the circuit layout requirement;
laser drilling:as shown in fig. 3, the laser machine utilizes CO 2 Laser drilling holes with required size at the positioning holes by adopting single-sided laser drilling, namely laser drilling is performed from the first copper foil layer 12 to form the holes, and the holes sequentially pass through the first copper foil layer 12, the first capacitor layer 11, the second copper foil layer 13 and the PP layer without burning through the third copper foil layer 22; the heat of the laser beam in infrared light and visible light acts on the plate, so that the plate is absorbed and then is molten, gasified, gas slurry and other decomposed matters are generated, laser hole burning is formed, and the depth groove size required by the cumulative sequencing processing is formed;
hole filling: removing glue residues, chemical copper and electroplating copper in the slotted holes to form through holes 41, so as to obtain buried four-layer plates 40 with inter-layer pattern lines mutually communicated; the first capacitance layer 11 and the second capacitance layer 21 are arranged in series by utilizing the through hole 41, so that the voltage resistance performance of the product is improved, and the risk of breakdown, disconnection and short circuit caused by insufficient voltage resistance of the final PCB using the ultra-high capacitance density material is solved;
step 5: an outer layer circuit: as shown in fig. 4, the first copper foil layer 12 and the fourth copper foil layer 23 of the buried four-layer board 40 are subjected to dry film pressing, exposure, development, etching and film stripping treatment to obtain the buried four-layer board 40 with an outer layer circuit, and the buried four-layer board 40 is etched into independent PADs at the first copper foil layer 12 corresponding to the through holes 41, wherein the PADs do not participate in the conduction of other circuits; the function of forming the independent bonding pads is: if the independent bonding pad is not designed, the first copper foil layer, the second copper foil layer and the third copper foil layer are in a conducting relation, the third copper foil layer and the fourth copper foil layer are capacitance layers, and finally only capacitance exists between the third copper foil layer and the fourth copper foil layer; after the independent bonding pads are designed, the first copper foil layer, the second copper foil layer and the third copper foil layer are in a conducting relation, but the independent bonding pads of the first copper foil layer do not participate in conducting, so that only the second copper foil layer and the third copper foil layer are in conducting; the first copper foil layer and the second copper foil layer are capacitance layers, the second copper foil layer and the third copper foil layer are in conducting relation, the third copper foil layer and the fourth copper foil layer are capacitance layers, and finally, the capacitance between the first copper foil layer and the second copper foil layer and the capacitance between the third copper foil layer and the fourth copper foil layer are connected in series through the second copper foil layer and the third copper foil layer;
step 6: and (3) resistance welding: forming a solder resist ink layer 42 on the surface of the buried four-layer board 40 through solder resist pretreatment, printing, pre-baking, exposure, development and post-baking to obtain a finished product carrier board, wherein independent PADs, corresponding to the through holes 41, on the first copper foil layer are covered under the solder resist ink layer 42; the purpose of the solder resist is to cover a layer of protective film on the surface of the buried four-layer plate 40, prevent the oxidation of the circuit and copper surface, prevent the damage of moisture, various electrolytes and mechanical external force to the circuit, and have the function of solder resist and limit the solder;
step 7: and (3) forming: finally milling, electrically measuring, checking and packaging to obtain the finished product for shipment. The final buried capacitor four-layer board 40 is sequentially provided with the first copper foil layer 12, the first capacitor layer 11, the second copper foil layer 13, the PP layer 30, the third copper foil layer 22, the second capacitor layer 21 and the fourth copper foil layer 23 from top to bottom, and a solder resist ink layer 42 is formed on the first copper foil layer and the fourth copper foil layer, the first copper foil layer and the fourth copper foil layer are provided with outer layer circuits, the second copper foil layer and the third copper foil layer are provided with inner layer circuits, and the via holes sequentially penetrate through the first copper foil layer 12, the first capacitor layer 11, the second copper foil layer 13 and the PP layer to be communicated with the third copper foil layer 22; in addition, the double-sided symmetrical lamination design is adopted in the process, so that only one lamination operation is needed in the whole process, the complexity of the product flow is effectively reduced, and the production efficiency of the product is improved.
The inner layer circuit in the step 2 specifically comprises the following steps:
(1) Pretreatment: cleaning the substrate by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the second copper foil layer 13 and the third copper foil layer 22 by using a sulfuric acid solution; cleaning the plate surface to remove the adhesion thereonSubstances such as stains, oxides, etc.; the copper surface can be roughened by microetching with sulfuric acid solution, the adhesive force with the dry film is increased, and the main chemical reaction is as follows: cu+H 2 O 2 →CuO+H 2 O；CuO+H 2 SO 4 →CuSO 4 +H 2 O；
(2) Pressing dry film: attaching photosensitive dry films to the surfaces of the second copper foil layer 13 and the third copper foil layer 22 in a hot pressing mode; a photosensitive dry film is pressed on the second copper foil layer 13 and the third copper foil layer 22 for subsequent image transfer, and after the dry film is heated, the dry film has fluidity and a certain filling property, and is attached to a board surface in a hot pressing mode by utilizing the characteristic;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film; an LDI exposure machine (Laser Direcl Imaging laser direct imaging) utilizes Ultraviolet (UV) energy to complete pattern transfer;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film; the exposed dry film does not react with the developer, and the development main chemical reaction: R-COOH+Na 2 CO 3 →R-COO-Na + +2NaHCO 3 ；
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit; the main chemical reaction: 3Cu+NaClO 3 +6HCl→3CuCl 2 +3H 2 O+NaCl；
(6) Leg mold: spraying NaOH or KOH liquid medicine on the board surface through a film stripping machine, removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of the inner-layer circuit to obtain a first buried capacitor substrate 10 and a second buried capacitor substrate 20 with the inner-layer circuit;
(7) AOI: the AOI system checks the inner layer line on the copper surface against the difference between the etched inner layer line and the original design line. AOI is Automatic Optical Inspection automated optical inspection), the Genesis system processes the CAM data of the original design line into reference data for inspection and outputs to the AOI system. The AOI system uses the optical principle to judge defects such as short circuit, circuit break, notch and the like by comparing the difference between the etched circuit and the designed circuit.
The step 3 of pressing specifically comprises the following steps:
(1) Pretreatment: acid washing: removing oxide on the surfaces of the second copper foil layer 13 and the third copper foil layer 22 by using sulfuric acid solution; cleaning: hydrolyzing the grease into small molecular substances which are easy to dissolve in water by using a cleaning agent; presoaking: pre-soaking the inner layer plate by using brown liquid; the pretreatment is for preparing the browning process; acid washing: the chemical reaction of sulfuric acid and CuO is utilized to remove oxides on the copper surface, and the main chemical reaction is as follows: cuO+H 2 SO 4 →CuSO 4 +H 2 O; cleaning by reaction of cleaning agent with oil and fat, and main chemical reaction is KOH+R 1 COOH→RNHCOR 1 +H 2 O; the presoaking makes the board have similar components to the browning liquid to prevent water from damaging the browning liquid;
(2) Brown chemical: the surface of the second copper foil layer 13 and the surface of the third copper foil layer 22 are subjected to brown treatment by brown treatment liquid, so that the surface of the copper is in an uneven surface shape, and the contact area of the copper surface and resin is increased; the brown oxide liquid is sulfuric acid and hydrogen peroxide, the sulfuric acid and the hydrogen peroxide are utilized to microetch the copper surface, and a layer of extremely thin, uniform and consistent organic metal conversion film is generated at the same time of microetching, and the main purpose of brown oxide is as follows: coarsening copper surface, increasing surface area contacted with PP layer (pre preg prepreg is sheet material impregnated with resin and solidified to intermediate degree), improving adhesion with PP layer, preventing delamination; the wettability of the copper surface and the flowing resin is increased; passivating the copper surface, and blocking the action of ammonia substances generated by polymerization and hardening of epoxy resin on the copper surface in the pressing plate process, wherein the ammonia substances attack the copper surface to generate water vapor, so that the explosion plate is caused;
(3) Overlapping: sequentially superposing the first buried capacitor substrate 10, the PP layer 30 and the second buried capacitor substrate 20, wherein the PP layer is positioned between the second copper foil layer 13 and the third copper foil layer 22;
(4) Pressing: the first buried substrate 10, the PP layer 30 and the second buried substrate 20 are fused and bonded to form a buried four-layer plate 40 at high temperature and high pressure of a press.
The hole filling in the step 4 specifically comprises the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method; in the high temperature of laser, when the temperature exceeds the Tg point of the resin, the resin is softened or even gasified, the formed fluid can be smeared on the hole wall, and after cooling, a glue residue paste (smooth) is formed, so that a gap is formed between copper walls of an inner copper hole ring which is subsequently made, and therefore, before chemical copper (PTH), the formed glue residue is required to be removed, so that the smooth adhesion of the chemical copper which is subsequently made Cheng Kongna is facilitated;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the slot hole through chemical action; namely, the original non-metallized hole wall is metallized, so that the subsequent smooth plating of electrochemical copper is facilitated;
(3) Electroplating copper: the surface of the electroless copper layer is plated with an electroplated copper layer by electroplating to form the via 41. In the electroplating bath, the copper ion components in the solution are uniformly reduced on the copper surface and in the holes by using a mode of applying alternating current (cathode to obtain electronic copper plating and anode to lose electronic dissolved copper), so that the thickness of the copper layer is required by specifications.
The specific process parameters in the step 4 are as follows:
in mechanical drilling, a UC double-edge cutter with the diameter of 0.350mm is utilized to drill a cutter, the feeding speed is controlled below 1.2m/min, the cutter returning speed is controlled below 15m/min, and a hole with the diameter of 0.350mm is drilled under the condition that the rotating speed is 90-120 kprm/min;
in laser drilling, the pulse width is 5-12ms, the energy is 2-7mj, the number of the pulses is 3-4, the MASK is 1.5-2.5, and the aperture of the laser drilling is 75-120 mu m;
in the hole filling, the aspect ratio of the hole is controlled to be more than 0.8:1, the dishing degree is controlled to be less than 20 mu m, and the copper thickness tolerance is +/-20%.
The outer layer circuit in the step 5 specifically comprises the following steps:
(1) Pretreatment: cleaning the buried four-layer board 40 by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the first copper foil layer 12 and the fourth copper foil layer 23 by using a sulfuric acid solution;
(2) Pressing dry film: attaching photosensitive dry films to the surfaces of the first copper foil layer 12 and the fourth copper foil layer 23 by using a hot pressing mode; a photosensitive dry film is pressed on the first copper foil layer 12 and the fourth copper foil layer 23 for subsequent image transfer, and after the dry film is heated, the dry film has fluidity and a certain filling property, and is attached to a board surface in a hot pressing mode by utilizing the characteristic;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) And (3) film removal: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, removing the dry film through the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of an outer layer circuit to obtain a buried four-layer board 40 with the outer layer circuit;
(7) AOI: the AOI system checks the outer layer of lines on the copper surface against the difference between the etched outer layer of lines and the original design lines.
The step 6 of solder resist specifically comprises the following steps:
(1) Pretreatment: removing the oxide on the copper surface of the etched buried four-layer plate 40, pickling and drying after microetching; the roughness of the copper surface is increased, so that the green paint can be more tightly combined after being coated, and the coated green paint is prevented from falling off;
(2) Screen printing and pre-baking: uniformly coating green oil on the surfaces of the first copper foil layer 12 and the fourth copper foil layer 23 through screen printing, and locally curing the green oil through pre-baking;
(3) Exposure: defining a green paint windowing part by an LDI exposure machine, and utilizing ultraviolet irradiation to polymerize and bond a photosensitive part and strengthen a structure; the non-photosensitive part is removed along with the cleaning of the developing solution;
(4) Developing: the unexposed photosensitive ink is dissolved and removed by a developing solution to achieve the aim of development; the process also has the function of removing residual glue;
(5) Post bake and UV cure: the green paint is fully reacted by accelerating the thermal polymerization reaction by combining the heat baking with the UV curing equipment, and is further bonded and strengthened to form a stable netlike structure, so that the solder mask ink layer 42 is thoroughly cured, and certain resistance and chemical resistance are achieved.
The high-pressure-resistant MEMS packaging loading plate is prepared by the manufacturing process. As shown in fig. 1, the high voltage MEMS package carrier comprises a first copper foil layer 12, a first capacitor layer 11, a second copper foil layer 13, a PP layer 30, a third copper foil layer 22, a second capacitor layer 21 and a fourth copper foil layer 23, which are sequentially arranged, wherein the first copper foil layer 12 and the fourth copper foil layer 23 are covered with a solder resist ink layer 43, and a via hole 41 is arranged between the first copper foil layer 12 and the third copper foil layer 22.
It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (9)
1. A manufacturing process of a high-pressure-resistant MEMS packaging carrier plate is characterized by comprising the following steps of: the method comprises the following steps:
step 1: cutting: cutting the buried substrate into a certain size and forming two buried substrates, namely a first buried substrate (10) and a second buried substrate (20), wherein the first buried substrate (10) is provided with a first capacitance layer (11), a first copper foil layer (12) and a second copper foil layer (13) which are respectively arranged on the front side and the back side of the first capacitance layer, and the second buried substrate (20) is provided with a second capacitance layer (21), a third copper foil layer (22) and a fourth copper foil layer (23) which are respectively arranged on the front side and the back side of the second capacitance layer;
step 2: inner layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment on a second copper foil layer (13) of the first buried substrate (10) and a third copper foil layer (22) of the second buried substrate (20) respectively to obtain the first buried substrate (10) and the second buried substrate (20) with inner-layer circuits;
step 3: pressing: sequentially overlapping the first embedded substrate (10), the PP layer (30) and the second embedded substrate (20), pressing the overlapped first embedded substrate (10), PP layer (30) and second embedded substrate (20) by using a press to form an embedded four-layer board (40), and respectively attaching the second copper foil layer (13) and the third copper foil layer (22) to the front side and the back side of the PP layer (30);
step 4: mechanical drilling, laser drilling and hole filling:
mechanical drilling: drilling a plurality of positioning holes on the first copper foil layer (12) by using a drill bit according to the circuit layout requirement;
laser drilling: laser machine utilizing CO 2 Laser is used for laser drilling holes with the required size at the positioning holes, namely laser drilling holes are formed from the first copper foil layer (12) by single-sided laser drilling, and the holes sequentially pass through the first copper foil layer (12), the first capacitor layer (11), the second copper foil layer (13) and the PP layer without burning through the third copper foil layer (22);
hole filling: removing glue residues, chemical copper and electroplating copper in the slotted holes to form through holes (41), so as to obtain buried four-layer plates (40) with inter-layer pattern circuits conducted with each other;
step 5: an outer layer circuit: performing dry film pressing, exposure, development, etching and film stripping treatment on the first copper foil layer (12) and the fourth copper foil layer (23) of the buried four-layer board (40) to obtain the buried four-layer board (40) with the outer layer circuit, and etching the first copper foil layer (12) corresponding to the through hole (41) into an independent PAD, wherein the PAD does not participate in the conduction of other circuits;
step 6: and (3) resistance welding: forming a solder mask ink layer (42) on the surface of the buried four-layer board (40) through solder mask pretreatment, printing, pre-baking, exposure, development and post-baking to obtain a finished product carrier board, wherein independent PADs which are positioned on the first copper foil layer and correspond to the through holes (41) are covered under the solder mask ink layer (42);
step 7: and (3) forming: finally milling, electrically measuring, checking and packaging to obtain the finished product for shipment.
2. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: the inner layer circuit in the step 2 specifically comprises the following steps:
(1) Pretreatment: cleaning the substrate by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the second copper foil layer (13) and the third copper foil layer (22) by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film to the surfaces of the second copper foil layer (13) and the third copper foil layer (22) in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) And (3) die stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of the inner layer circuit to obtain a first buried capacitor substrate (10) and a second buried capacitor substrate (20) with the inner layer circuit;
(7) AOI: the AOI system checks the inner layer line on the copper surface against the difference between the etched inner layer line and the original design line.
3. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: the step 3 of pressing specifically comprises the following steps:
(1) Pretreatment: acid washing: removing oxide on the surfaces of the second copper foil layer (13) and the third copper foil layer (22) by using sulfuric acid solution; cleaning: hydrolyzing the grease into small molecular substances which are easy to dissolve in water by using a cleaning agent; presoaking: pre-soaking the inner layer plate by using brown liquid;
(2) Brown chemical: the surface of the second copper foil layer (13) and the surface of the third copper foil layer (22) are subjected to brown treatment by brown treatment liquid, so that the surface of the copper is in an uneven surface shape, and the contact area of the copper surface and resin is increased;
(3) Overlapping: sequentially superposing a first buried capacitor substrate (10), a PP layer (30) and a second buried capacitor substrate (20) and positioning the PP layer between a second copper foil layer (13) and a third copper foil layer (22);
(4) Pressing: and fusing and bonding the first buried substrate (10), the PP layer (30) and the second buried substrate (20) into a buried four-layer plate (40) at high temperature and high pressure of a press.
4. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: the hole filling in the step 4 specifically comprises the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the slot hole through chemical action;
(3) Electroplating copper: a copper plating layer is plated on the surface of the electroless copper layer by electroplating to form a via hole (41).
5. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: the specific process parameters in the step 4 are as follows:
in mechanical drilling, a UC double-edge cutter with the diameter of 0.350mm is utilized to drill a cutter, the feeding speed is controlled below 1.2m/min, the cutter returning speed is controlled below 15m/min, and a hole with the diameter of 0.350mm is drilled under the condition that the rotating speed is 90-120 kprm/min;
in laser drilling, the pulse width is 5-12ms, the energy is 2-7mj, the number of the pulses is 3-4, the MASK is 1.5-2.5, and the aperture of the laser drilling is 75-120 mu m;
in the hole filling, the aspect ratio of the hole is controlled to be more than 0.8:1, the dishing degree is controlled to be less than 20 mu m, and the copper thickness tolerance is +/-20%.
6. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: in step 5, the outer layer circuit specifically comprises the following steps:
(1) Pretreatment: cleaning the buried four-layer board (40) by using a cleaning solution containing hydrogen peroxide, and coarsening the surfaces of the first copper foil layer (12) and the fourth copper foil layer (23) by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film to the surfaces of the first copper foil layer (12) and the fourth copper foil layer (23) in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, removing the dry film through the chemical reaction of the liquid medicine and the dry film, and completing the manufacture of an outer layer circuit to obtain a buried four-layer board (40) with the outer layer circuit;
(7) AOI: the AOI system checks the outer layer of lines on the copper surface against the difference between the etched outer layer of lines and the original design lines.
7. The process for fabricating a high voltage MEMS package carrier of claim 1, wherein: the step 6 of solder resist specifically comprises the following steps:
(1) Pretreatment: removing the oxide on the copper surface of the etched buried four-layer plate (40), and pickling and drying the etched copper surface after microetching;
(2) Screen printing and pre-baking: uniformly coating green oil on the surfaces of the first copper foil layer (12) and the fourth copper foil layer (23) through screen printing, and locally curing the green oil through pre-baking;
(3) Exposure: defining a green paint windowing part by an LDI exposure machine, and utilizing ultraviolet irradiation to polymerize and bond a photosensitive part and strengthen a structure;
(4) Developing: the unexposed photosensitive ink is dissolved and removed by a developing solution to achieve the aim of development;
(5) Post bake and UV cure: the green paint is fully reacted by accelerating the thermal polymerization reaction by combining the heat baking with the UV curing equipment, and is further bonded and strengthened to form a stable netlike structure, so that the solder mask ink layer (42) is thoroughly cured, and certain resistance and chemical resistance are achieved.
8. A high voltage MEMS package carrier, characterized by: the package carrier is prepared by the manufacturing process according to any one of claims 1-7.
9. The high withstand voltage MEMS package carrier of claim 8, wherein: including first copper foil layer (12), first electric capacity layer (11), second copper foil layer (13), PP layer (30), third copper foil layer (22), second electric capacity layer (21) and fourth copper foil layer (23) that set gradually, just cover one deck solder mask ink layer (42) on first copper foil layer (12) and fourth copper foil layer (23), be equipped with between first copper foil layer (12) and the third copper foil layer (22) via hole (41).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111447442.7A CN114206001B (en) | 2021-11-30 | 2021-11-30 | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111447442.7A CN114206001B (en) | 2021-11-30 | 2021-11-30 | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114206001A CN114206001A (en) | 2022-03-18 |
| CN114206001B true CN114206001B (en) | 2023-11-14 |
Family
ID=80650004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111447442.7A Active CN114206001B (en) | 2021-11-30 | 2021-11-30 | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114206001B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116709647B (en) * | 2023-05-29 | 2024-03-08 | 宁波科浩达电子有限公司 | Preparation process of printed circuit board |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000340955A (en) * | 1999-05-26 | 2000-12-08 | Matsushita Electric Ind Co Ltd | Passive component-incorporated composite multilayered wiring board and manufacture thereof |
| CN103298274A (en) * | 2012-02-24 | 2013-09-11 | 北大方正集团有限公司 | Manufacturing method for capacitor-buried printed-circuit board and capacitor-buried printed-circuit board |
| CN107889350A (en) * | 2017-12-22 | 2018-04-06 | 珠海快捷中祺电子科技有限公司 | Multilayer circuit board |
| CN108770236A (en) * | 2018-05-23 | 2018-11-06 | 高德（无锡）电子有限公司 | A kind of CO2Laser drilling replaces the processing technology of the blind fishing Rigid Flex of machinery |
| CN108966516A (en) * | 2018-08-27 | 2018-12-07 | 深圳崇达多层线路板有限公司 | A kind of one step press buried capacitor technique based on supporting substrate |
| CN110312366A (en) * | 2019-07-03 | 2019-10-08 | 安捷利电子科技（苏州）有限公司 | Buried capacitor material and its preparation process, buried capacitor circuit board and its manufacture craft |
| CN113133230A (en) * | 2021-04-20 | 2021-07-16 | 梅州市志浩电子科技有限公司 | Manufacturing method of stepped circuit board embedded with capacitor and resistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8059423B2 (en) * | 2007-02-06 | 2011-11-15 | Sanmina-Sci Corporation | Enhanced localized distributive capacitance for circuit boards |
| US10923443B2 (en) * | 2019-03-29 | 2021-02-16 | Intel Corporation | Electronic device package including a capacitor |
-
2021
- 2021-11-30 CN CN202111447442.7A patent/CN114206001B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000340955A (en) * | 1999-05-26 | 2000-12-08 | Matsushita Electric Ind Co Ltd | Passive component-incorporated composite multilayered wiring board and manufacture thereof |
| CN103298274A (en) * | 2012-02-24 | 2013-09-11 | 北大方正集团有限公司 | Manufacturing method for capacitor-buried printed-circuit board and capacitor-buried printed-circuit board |
| CN107889350A (en) * | 2017-12-22 | 2018-04-06 | 珠海快捷中祺电子科技有限公司 | Multilayer circuit board |
| CN108770236A (en) * | 2018-05-23 | 2018-11-06 | 高德（无锡）电子有限公司 | A kind of CO2Laser drilling replaces the processing technology of the blind fishing Rigid Flex of machinery |
| CN108966516A (en) * | 2018-08-27 | 2018-12-07 | 深圳崇达多层线路板有限公司 | A kind of one step press buried capacitor technique based on supporting substrate |
| CN110312366A (en) * | 2019-07-03 | 2019-10-08 | 安捷利电子科技（苏州）有限公司 | Buried capacitor material and its preparation process, buried capacitor circuit board and its manufacture craft |
| CN113133230A (en) * | 2021-04-20 | 2021-07-16 | 梅州市志浩电子科技有限公司 | Manufacturing method of stepped circuit board embedded with capacitor and resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114206001A (en) | 2022-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114340225B (en) | Multilayer packaging substrate alignment method suitable for laser blind holes | |
| CN114302561B (en) | Manufacturing method of multilayer board with ultralow copper residue and semi-through holes | |
| WO1998056220A1 (en) | Single-sided circuit board and method for manufacturing the same | |
| CN106961801A (en) | A kind of preparation method of constant line width tolerance printed substrate | |
| KR100601485B1 (en) | BGA package board and method for manufacturing thereof | |
| CN114222434B (en) | Manufacturing method of ladder circuit and circuit board | |
| CN114501855B (en) | Manufacturing process of double-sided buried wire ultrathin circuit board | |
| CN107347229A (en) | The process of wiring board selective resin consent | |
| CN114190011B (en) | High-heat-dissipation PCB and manufacturing process thereof | |
| CN114206001B (en) | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof | |
| CN114096080A (en) | Manufacturing process of thick-hole copper in printed circuit board | |
| CN116581032A (en) | Packaging loading plate with hollow structure and manufacturing process thereof | |
| CN114340223B (en) | Manufacturing method of high aspect ratio-based selective semi-conductive hole multilayer board | |
| CN114195090B (en) | Ultra-high capacitance MEMS packaging loading plate and manufacturing process thereof | |
| CN114368726A (en) | MEMS built-in chip packaging carrier plate and manufacturing process thereof | |
| CN105430925A (en) | Fabrication method of thick copper circuit board | |
| CN114190010B (en) | Processing technology of carrier plate with PAD at bottom of blind groove | |
| JP2004186354A (en) | Method of manufacturing multilayer wiring board | |
| CN114477073B (en) | Manufacturing method for improving edge chip drop of MEMS carrier plate | |
| CN114375097B (en) | Processing technology of packaging substrate for sensor | |
| CN114501805B (en) | Manufacturing process of integral metallized edge-sealed microphone carrier plate | |
| CN114466512B (en) | MEMS (micro-electromechanical systems) buried-capacitor buried-resistor packaging loading plate and manufacturing process thereof | |
| CN114195090A (en) | Ultra-high capacitance MEMS packaging support plate and manufacturing process thereof | |
| CN114206024B (en) | Manufacturing method of MEMS (micro-electromechanical systems) packaging carrier plate | |
| CN114364167B (en) | Double-layer packaging substrate alignment method suitable for laser through holes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |