CN110312366A - Buried capacitor material and its preparation process, buried capacitor circuit board and its manufacture craft - Google Patents
Buried capacitor material and its preparation process, buried capacitor circuit board and its manufacture craft Download PDFInfo
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- CN110312366A CN110312366A CN201910595804.3A CN201910595804A CN110312366A CN 110312366 A CN110312366 A CN 110312366A CN 201910595804 A CN201910595804 A CN 201910595804A CN 110312366 A CN110312366 A CN 110312366A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
The present invention provides a kind of buried capacitor material and its preparation processes, the buried capacitor circuit board and its manufacture craft using buried capacitor material production are additionally provided simultaneously, buried capacitor material has excellent high dielectric constant and low-loss, the buried capacitor circuit board made of the buried capacitor material, it neatly capacitance as needed can need to make capacitor, it is suitble to the capacitor production of large capacitance, buried capacitor material is by layers of copper, high dielectric layer, semi-solid preparation layer is formed by stacking, high dielectric layer is located in layers of copper, semi-solid preparation layer is located on high dielectric layer, substrate sawing sheet, capacitor layer pattern is made on substrate, it is pressed on substrate and above-mentioned buries resistance material, capacitor sandwich circuit is made in the layers of copper of buried capacitor material, increasing layer needed for pressing PCB on buried capacitor material；It drills at capacitor layers position, then carries out the via hole processing procedure and make the electrode conduction of capacitor layers to outermost layer, while making outer-layer circuit, form the electrode of capacitor.
Description
Technical field
The present invention relates to printed-board technology field, specially buried capacitor material and its preparation process, buried capacitor circuit board and
Its manufacture craft.
Background technique
Since current electronic product develops to short and small frivolous direction, for as component motherboard --- the density of PCB
It is required that also higher and higher.Passive device embedmentization technology can greatly reduce number of devices simultaneously, also improve electromagnetic performance.And
Buried capacitor is the one kind being most widely used in passive device.Buried capacitor capacity cell being built in inside substrate
Technology is the important solution of one kind of electronic system miniaturization.It is normally used for microphone and wearable electronic product
In, play the role of filtering, timing, decoupling and electric flux storage.Its major advantage is electronic system can be improved steady
Qualitative and reliability reduces the cost of product and reduces the physical size of product.
Capacitor ratio shared in all passive devices is up to 60%, and external You Duo company develops buried capacitor material
Material, such as 3M, DuPont, Ohmega, the country rarely have the Related product of independent development, and the exploitation of buried capacitor material has wide warp
Ji prospect.
Summary of the invention
In view of the above-mentioned problems, the present invention provides a kind of buried capacitor material and its preparation processes, while additionally providing to use and be somebody's turn to do
The buried capacitor circuit board and its manufacture craft of buried capacitor material production, buried capacitor material have excellent high dielectric constant and low-loss, adopt
The buried capacitor circuit board made of the buried capacitor material neatly capacitance as needed can need to make capacitor, be suitble to big
The capacitor of capacitance makes.
Its technical solution is such that a kind of buried capacitor material, it is characterised in that: it is by layers of copper, high dielectric layer, semi-solid preparation layer
It is formed by stacking, the high dielectric layer is located in layers of copper, and the semi-solid preparation layer is located on the high dielectric layer.
Further, the high dielectric layer includes high dielectric ceramic material and resin, the semi-solid preparation layer include resin and
Filler.
Further, the high dielectric ceramic material includes barium titanate, strontium titanates, barium strontium titanate, aluminium oxide, titanium dioxide
Silicon, titanium dioxide, in calcium barium titanate any one or at least two mixture；The resin of high dielectric layer includes asphalt mixtures modified by epoxy resin
Rouge, phenolic resin, BT resin, cyanate ester resin, polyphenylene oxide resin, benzoxazine resin, any one in acrylic resin
Or at least two mixture.
Further, the resin of the semi-solid preparation layer includes epoxy resin, phenolic resin, BT resin, cyanate ester resin, gathers
Phenylene ether resins, benzoxazine resin, in acrylic resin any one or at least two mixture, the filler includes silicon
Micro mist, aluminium hydroxide, in calcium carbonate any one or at least two mixture.
A kind of preparation process of above-mentioned buried capacitor material, which comprises the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 80 DEG C -140 DEG C, time 2min-15min；
Step 5: solidify high dielectric layer: by high dielectric layer glue curing, solidification temperature is at 150 DEG C -400 DEG C, time 2h
More than；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 80 DEG C -140 DEG C, time 2min-15min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
Further, between 2um-33um, the thickness control of the high dielectric layer exists the thickness control of the layers of copper
Between 2um-12um, the thickness control of the semi-solid preparation layer is between 5um-12um.
A kind of technique using above-mentioned buried capacitor material production buried capacitor circuit board, which comprises the following steps:
Step S1: substrate sawing sheet；
Step S2: capacitor layer pattern is made on substrate；
Step S3: resistance material is buried in pressing on substrate；
Step S4: capacitor sandwich circuit is made in the layers of copper of buried capacitor material；
Step S5: increasing layer needed for pressing PCB on buried capacitor material；
Step S6: drilling at the capacitor layers position that step S5 obtains intermediate products, then carries out the via hole processing procedure
So that the electrode conduction of capacitor layers is to outermost layer, while making outer-layer circuit, the electrode of capacitor is formed.
Further, it between step S4 and step S5, repeats to press buried capacitor material and production capacitor layer pattern makes electricity
Hold size meet demand.
Further, the material of increasing layer includes any one in FR4, FR5, BT, RCC.
Further, in step s 6, when making outer-layer circuit, by two adjacent capacitor serial or parallel connections, with full
Sufficient capacitance demand.
A kind of buried capacitor circuit board, it is characterised in that: be made using above-mentioned manufacture craft.
Buried capacitor material of the invention, with excellent high dielectric constant and low-loss, while intensity and shock resistance
It is excellent, the phenomenon that fragmentation will not occur in etching or drilling process；The preparation work of buried capacitor material through the invention
Skill obtains buried capacitor material, can be directly used for production buried capacitor circuit board, facilitates production buried capacitor circuit board；Use buried capacitor of the invention
Material makes the technique of buried capacitor circuit board, neatly capacitance as needed buried capacitor material can be laminated, facilitate processing,
Extension, is particularly suitable for the capacitor production of large capacitance, and prepared buried capacitor circuit board does not need attachment conventional capacitive, reduces people
Work, scolding tin, improve production efficiency, reduce costs, while decreasing circuit board surface parts density, enable a customer to be used for
The space of design is bigger；Simultaneously circuit board service life be improved, quality stability it is more preferable.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of buried capacitor material of the invention；
Fig. 2 is the flow diagram of the preparation process of buried capacitor material of the invention；
Fig. 3 is the flow diagram of the technique of the production buried capacitor circuit board in specific embodiment two.
Specific embodiment
See that Fig. 1, buried capacitor material of the invention are formed by stacking by layers of copper 101, high dielectric layer 102, semi-solid preparation layer 103, it is high
Dielectric layer 102 is located in layers of copper 101, and semi-solid preparation layer 103 is located on high dielectric layer 102.
High dielectric layer 102 includes high dielectric ceramic material and resin, and semi-solid preparation layer 103 includes resin and filler.
Specifically, high dielectric ceramic material includes barium titanate, strontium titanates, barium strontium titanate, aluminium oxide, silica, dioxy
Change titanium, in calcium barium titanate any one or at least two mixture；The resin of high dielectric layer includes epoxy resin, phenolic aldehyde tree
Rouge, BT resin, cyanate ester resin, polyphenylene oxide resin, benzoxazine resin, in acrylic resin any one or at least two
Mixture.
Specifically, the resin of semi-solid preparation layer includes epoxy resin, phenolic resin, BT resin, cyanate ester resin, polyphenylene oxide tree
Rouge, benzoxazine resin, in acrylic resin any one or at least two mixture, filler includes silicon powder, hydrogen-oxygen
Change aluminium, in calcium carbonate any one or at least two mixture.
Specific embodiment 1: the high dielectric ceramic material of buried capacitor material includes the mixture of barium titanate, strontium titanates, Gao Jie electricity
The resin of layer includes the mixture of epoxy resin, phenolic resin, BT resin；The resin of semi-solid preparation layer includes epoxy resin, phenolic aldehyde
The mixture of resin, BT resin；Filler includes silicon powder.
See Fig. 2, the preparation process of above-mentioned buried capacitor material, comprising the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 80 DEG C -100 DEG C, time 10min-15min；
Step 5: solidify high dielectric layer: by high dielectric layer glue curing, solidification temperature is at 350 DEG C -400 DEG C, time 2h-
4h；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 80 DEG C -100 DEG C, time 10min-15min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
In the present embodiment, the thickness control of layers of copper is between 2um-17um, and the thickness control of high dielectric layer is in 2um-
Between 10um, the thickness control of semi-solid preparation layer is between 5um-8um.
Specific embodiment 2: the high dielectric ceramic material of buried capacitor material includes aluminium oxide, silica, titanium dioxide mixing
Object；The resin of high dielectric layer includes cyanate ester resin, polyphenylene oxide resin, benzoxazine resin, the mixture in acrylic resin；
The resin of semi-solid preparation layer includes cyanate ester resin, polyphenylene oxide resin, benzoxazine resin, the mixture in acrylic resin, is filled out
Material includes the mixture in aluminium hydroxide, calcium carbonate.
See Fig. 2, the preparation process of above-mentioned buried capacitor material, comprising the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 110 DEG C -140 DEG C, time 2min-10min；
Step 5: solidification: by high dielectric layer glue curing, solidification temperature is at 150 DEG C -300 DEG C, time 4h-8h；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 110 DEG C -140 DEG C, time 2min-10min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
In the present embodiment, the thickness control of layers of copper is between 15um-33um, and the thickness control of high dielectric layer is in 5um-
Between 12um, the thickness control of semi-solid preparation layer is between 10um-12um.
Specific embodiment 3: the high dielectric ceramic material of buried capacitor material includes silica, titanium dioxide, in calcium barium titanate
Mixture；The resin of high dielectric layer includes epoxy resin；The resin of semi-solid preparation layer includes epoxy resin, and filler includes carbonic acid
Calcium is shown in Fig. 2, the preparation process of above-mentioned buried capacitor material, comprising the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 90 DEG C -120 DEG C, time 5min-12min；
Step 5: solidification: by high dielectric layer glue curing, solidification temperature is at 200 DEG C -350 DEG C, time 3h-8h；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 90 DEG C -120 DEG C, time 5min-12min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
In the present embodiment, the thickness control of layers of copper is between 5um-20um, and the thickness control of high dielectric layer is in 4um-8um
Between, the thickness control of semi-solid preparation layer is between 6um-8um.
Specific embodiment 4: the high dielectric ceramic material of buried capacitor material include barium titanate, silica, titanium dioxide it is mixed
Close object；The resin of high dielectric layer includes the mixture of phenolic resin, BT resin, and the resin of semi-solid preparation layer includes phenolic resin, BT
The mixture of resin, filler include the mixture of silicon powder, aluminium hydroxide.
See Fig. 2, the preparation process of above-mentioned buried capacitor material, comprising the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 110 DEG C -130 DEG C, time 5min-10min；
Step 5: solidification: by high dielectric layer glue curing, solidification temperature is at 180 DEG C -300 DEG C, time 6h-10h；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 110 DEG C -130 DEG C, time 5min-10min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
In the present embodiment, the thickness control of layers of copper is between 15um-30um, and the thickness control of high dielectric layer is in 4um-
Between 7um, the thickness control of semi-solid preparation layer is between 7um-11um.
Specific embodiment 5: the high dielectric ceramic material of buried capacitor material include barium titanate, silica, titanium dioxide it is mixed
Close object；The resin of high dielectric layer includes the mixture of phenolic resin, BT resin, and the resin of semi-solid preparation layer includes phenolic resin, BT
The mixture of resin, filler include the mixture of silicon powder, aluminium hydroxide.
See Fig. 2, the preparation process of above-mentioned buried capacitor material, comprising the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue
Water；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: prebake being carried out to the high dielectric layer glue being coated in step 3, removes solvent and volatilization
Ingredient, drying temperature control is at 100 DEG C -140 DEG C, time 5min-10min；
Step 5: solidification: by high dielectric layer glue curing, solidification temperature is at 200 DEG C -320 DEG C, time 3h-15h；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation
Layer glue forms semi-cured state, and drying temperature is control at 105 DEG C -125 DEG C, time 6min-11min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
In the present embodiment, the thickness control of layers of copper is between 12um-30um, and the thickness control of high dielectric layer is in 5um-
Between 7um, the thickness control of semi-solid preparation layer is between 5um-11um.
Using buried capacitor material production buried capacitor circuit board technique specific embodiment 1:
A kind of technique using buried capacitor material production buried capacitor circuit board, comprising the following steps:
Step S1: 2 sawing sheet of substrate；
Step S2: capacitor layer pattern is made on a substrate 2；
Step S3: what each one layer of pressing was above-mentioned under on a substrate 2 buries resistance material 1；
Step S4: capacitor sandwich circuit is made in the layers of copper of buried capacitor material 1；
Step S5: on buried capacitor material press PCB needed for increasing layer 3, specifically, the material of increasing layer include FR4, FR5,
Any one in BT, RCC；
Step S6: drilling at the capacitor layers position that step S5 obtains intermediate products, then carries out the via hole processing procedure
So that the electrode conduction of capacitor layers is to outermost layer, while making outer-layer circuit, the electrode of capacitor is formed, in step s 6, is being made
When making outer-layer circuit, by two adjacent capacitor serial or parallel connections, to meet capacitance demand
Using buried capacitor material production buried capacitor circuit board technique specific embodiment 2:
See Fig. 3, a kind of technique using buried capacitor material production buried capacitor circuit board, which comprises the following steps:
Step S1: substrate sawing sheet；
Step S2: capacitor layer pattern is made on substrate；
Step S3: respectively one layer is pressed up and down in substrate and buries resistance material；
Step S4: capacitor sandwich circuit is made in the layers of copper of buried capacitor material；
Between step S4 and step S5, again substrate respectively press up and down one layer it is above-mentioned bury resistance material, and make electricity
Hold layer pattern and makes capacitance size meet demand；
Step S5: increasing layer needed for pressing PCB on buried capacitor material, the material of increasing layer includes in FR4, FR5, BT, RCC
Any one；
Step S6: drilling at the capacitor layers position that step S5 obtains intermediate products, then carries out the via hole processing procedure
So that the electrode conduction of capacitor layers is to outermost layer, while making outer-layer circuit, the electrode of capacitor is formed.
In addition, when making outer-layer circuit, it can also be by two adjacent capacitor serial or parallel connections, to meet capacitance need
It asks.
The present invention also provides a kind of buried capacitor circuit boards, are made using above-mentioned manufacture craft, on buried capacitor circuit board
The capacitance of single capacitor indicated by following formula:
C=n ε S/ (d1+d2)
Wherein, C is capacitance size, and n is that buried capacitor material repeats the number of plies, and ε is the dielectric constant of buried capacitor material medium, and S is single
The capacitor layers graphics area of layer, capacitor layer pattern are random regular pattern or irregular figure, and d1+d2 is capacitor interlamellar spacing,
D1 is the thickness of the high dielectric layer of material, the thickness of semi-solid preparation layer of the d2 between capacitor layer pattern and high dielectric layer, after pressing
The high thickness of dielectric layers of material is unchanged, and semi-solid preparation layer repeats number of plies n and depend on because gummosis fill line gap thickness becomes smaller
Required capacitance size, the number of plies is more, and produced capacitor specification is bigger, neatly capacitance as needed can carry out layer
Folded buried capacitor material facilitates processing, extension.
Buried capacitor material of the invention, with excellent high dielectric constant and low-loss, while intensity and shock resistance
It is excellent, the phenomenon that fragmentation will not occur in etching or drilling process；The preparation work of buried capacitor material through the invention
Skill obtains buried capacitor material, can be directly used for production buried capacitor circuit board, facilitates production buried capacitor circuit board；Use buried capacitor of the invention
Material makes the technique of buried capacitor circuit board, neatly capacitance as needed buried capacitor material can be laminated, facilitate processing,
Extension, is particularly suitable for the capacitor production of large capacitance, and prepared buried capacitor circuit board does not need attachment conventional capacitive, reduces people
Work, scolding tin, improve production efficiency, reduce costs, while decreasing circuit board surface parts density, enable a customer to be used for
The space of design is bigger；Simultaneously circuit board service life be improved, quality stability it is more preferable.
The technique of buried capacitor material production buried capacitor circuit board of the invention, is cut into required Embedded capacitance figure in capacitor layers
Shape has the advantages that with high accuracy, while the wet line process such as also avoid pattern transfer, improves the good of printed circuit board
Product rate；Pressing increasing layer in step s 5, increasing layer is organic-based material needed for pressing PCB, such as FR4, FR5, BT, RCC, so that
Overall structure has certain toughness and machinability, improves the rigidity of capacitor layers, avoids high dielectric layer and fold, deformation occurs
Etc. bad phenomenons；And the integrality of power supply can be improved in buried capacitor circuit board；Reduce the influence of noise of power plane；It is flat to reduce power supply
The impedance in face；Reducing EMI influences；The frequency range that capacitor can act on is higher；Breakdown voltage value is higher；Reduce Surface Mount capacitor；Subtract
The area of small pcb plate；Reduce production cost；The technology of buried capacitor circuit board is applied to telecom carrier-class device veneer, can simplify the space of a whole page
Design, largely saves Surface Mount capacitor in BGA area；Applied to automotive electronics board industry, tradition decoupling is replaced using buried capacitor material
Close filter capacitor；Applied to handheld device, product new function can be increased, area is reduced, enhance product performance, EMI significantly changes
It is kind；Applied to microphone, the reduction of volume may be implemented, and obtain the improvement of signal to noise ratio.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
Claims (10)
1. a kind of buried capacitor material, it is characterised in that: it is formed by stacking by layers of copper, high dielectric layer, semi-solid preparation layer, the high dielectric layer
In layers of copper, the semi-solid preparation layer is located on the high dielectric layer.
2. a kind of buried capacitor material according to claim 1, it is characterised in that: the high dielectric layer includes high dielectric ceramic material
Material and resin, the semi-solid preparation layer includes resin and filler.
3. a kind of buried capacitor material according to claim 2, it is characterised in that: the high dielectric ceramic material includes metatitanic acid
Barium, strontium titanates, barium strontium titanate, aluminium oxide, silica, titanium dioxide, in calcium barium titanate any one or at least two
Mixture；The resin of high dielectric layer includes epoxy resin, phenolic resin, BT resin, cyanate ester resin, polyphenylene oxide resin, benzo
In oxazines resin, acrylic resin any one or at least two mixture；The resin of the semi-solid preparation layer includes epoxy
It is resin, phenolic resin, BT resin, cyanate ester resin, polyphenylene oxide resin, benzoxazine resin, any one in acrylic resin
Kind or at least two mixture, the filler include silicon powder, aluminium hydroxide, in calcium carbonate any one or at least two
Mixture.
4. a kind of preparation process of buried capacitor material described in claim 1, which comprises the following steps:
Step 1: preparing high dielectric layer glue；Mixing high dielectric ceramic material, resin and solvent obtain high dielectric layer glue；
Step 2: prepare semi-solid preparation layer glue: mixed fillers, resin, solvent obtain semi-solid preparation layer glue；
Step 3: being coated with high dielectric layer glue: being coated with high dielectric layer glue on the copper foil for constituting layers of copper；
Step 4: a prebake: carrying out prebake to the high dielectric layer glue being coated in step 3, removes solvent and is volatilized into
Point, drying temperature control is at 80 DEG C -140 DEG C, time 2min-15min；
Step 5: solidify high dielectric layer: by high dielectric layer glue curing, for solidification temperature at 150 DEG C -400 DEG C, the time is 2h or more；
Step 6: semi-solid preparation layer glue coating semi-solid preparation layer glue: is coated on cured high dielectric layer；
Step 7: secondary prebake: double of cured layer glue is dried, and solvent and volatile ingredient is removed, so that semi-solid preparation layer glue
Water forms semi-cured state, and drying temperature is control at 80 DEG C -140 DEG C, time 2min-15min；
Step 8: cutting: the buried capacitor material that step 7 is obtained is by required size cutting.
5. a kind of preparation process of buried capacitor material according to claim 4, it is characterised in that: the thickness control of the layers of copper
Between 2um-33um, between 2um-12um, the thickness control of the semi-solid preparation layer exists the thickness control of the high dielectric layer
Between 5um-12um.
6. a kind of technique using buried capacitor material described in claim 1 production buried capacitor circuit board, which is characterized in that including following
Step:
Step S1: substrate sawing sheet；
Step S2: capacitor layer pattern is made on substrate；
Step S3: resistance material is buried in pressing on substrate；
Step S4: capacitor sandwich circuit is made in the layers of copper of buried capacitor material；
Step S5: increasing layer needed for pressing PCB on buried capacitor material；
Step S6: drilling at the capacitor layers position that step S5 obtains intermediate products, then carries out the via hole processing procedure and makes
The electrode conduction of capacitor layers makes outer-layer circuit to outermost layer, forms the electrode of capacitor.
7. it is according to claim 6 production buried capacitor circuit board technique, it is characterised in that: step S4 and step S5 it
Between, it repeats to press buried capacitor material and production capacitor layer pattern makes capacitance size meet demand.
8. it is according to claim 6 production buried capacitor circuit board technique, it is characterised in that: the material of increasing layer include FR4,
Any one in FR5, BT, RCC.
9. the technique of production buried capacitor circuit board according to claim 6, it is characterised in that: in step s 6, outer in production
When sandwich circuit, by two adjacent capacitor serial or parallel connections, to meet capacitance demand.
10. a kind of buried capacitor circuit board, it is characterised in that: be made using manufacture craft as claimed in claim 6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114206001A (en) * | 2021-11-30 | 2022-03-18 | 江苏普诺威电子股份有限公司 | High-voltage-resistance MEMS packaging carrier plate and manufacturing process thereof |
| CN114195090A (en) * | 2021-11-30 | 2022-03-18 | 江苏普诺威电子股份有限公司 | Ultra-high capacitance MEMS packaging support plate and manufacturing process thereof |
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| CN114206001B (en) * | 2021-11-30 | 2023-11-14 | 江苏普诺威电子股份有限公司 | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof |
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Application publication date: 20191008 |