CN102024565B - Capacitor structure - Google Patents
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- CN102024565B CN102024565B CN 200910173551 CN200910173551A CN102024565B CN 102024565 B CN102024565 B CN 102024565B CN 200910173551 CN200910173551 CN 200910173551 CN 200910173551 A CN200910173551 A CN 200910173551A CN 102024565 B CN102024565 B CN 102024565B
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Abstract
The invention provides a capacitor structure. The capacitor structure comprises a first electrode layer, a first dielectric layer and a second electrode layer, wherein the first dielectric layer is arranged on the first electrode layer; the second electrode layer is arranged on the first dielectric layer; and at least one of the first electrode layer and the second electrode layer has a concave-convex structure, so that at least two different distance exists between the first electrode layer and the second electrode layer and parallel effect of at least two groups of capacitance values is achieved.
Description
Technical field
The present invention relates to a kind of capacitance structure, and be particularly related to the concavo-convex capacitance structure of combined type.
Background technology
The miniaturization of electronic building brick and high-effect demand be clear, thin, short along with electronic product, little application and by constantly requirement, therefore for the further requirement of capacitance component, except small size and large capacitance, increased again at high band and also will keep low-impedance usefulness (wideband Low ESR) requirement.Built-in large capacitance component with low impedance at high frequency will be with the effective technology that solves the power supply noise that the high speed commutation circuit produces.
Assembly capacitance (C) can represent by following equation:
Wherein, K is the dielectric coefficient of dielectric layer, and d is the distance between the conductor material, and A is the overlapping area of conductor material.Therefore, if will improve the capacitance of capacitance component, the dielectric coefficient (K) of dielectric layer or the overlapping area (A) of conductor material must be improved, or the distance (d) of conductor material is dwindled.Yet, because dielectric coefficient (K) is subjected to the restriction of dielectric layer material exploitation and related process cooperation and can't effectively improves, the distance of conductor material (d) then is subject to technique certain limiting value, moreover, the conductor material overlapping area (A) of classic flat-plate formula capacitance structure is subject to substrate area and can't increases too many, therefore, the lifting of capacitance can't have breakthrough development.
Because on conventional art, built-in electric capacity on encapsulation or the substrate can't reach the usefulness of low impedance at high frequency, therefore mostly be to adopt the electric capacity (on-chipcapacitor) on the chip to carry out the inhibition of noise in the inhibition of high band (GHz) noise, what but it was spent is the chip space of an inch of land is an inch of gold, and the design of some chip circuit does not allow unnecessary space to hold electric capacity on the chip.For in, the inhibition of low band frequency noise then mostly adopts surface mount assembly (surface mount device, SMD) capacitance component, its reason also is because the built-in electric capacity on encapsulation or substrate can't reach the cause of large capacitance.Hence one can see that is faced with two problems and demand at the built-in capacitance technology on encapsulation or the substrate: the required low impedance at high frequency usefulness of high band noise suppressed and in, low frequency range noise suppresses required large capacitance.
Therefore, how to increase the impedance frequency range of decoupling electric capacity, reach electronic circuit the controlling consumption of different frequency range noise, and make it have large capacitance, be the important topic of the art.
Summary of the invention
The invention provides a kind of capacitance structure, comprising: the first electrode layer; The first dielectric layer is located on this first electrode layer; And the second electrode lay, be located on the first dielectric layer, wherein the first electrode layer and the second electrode lay at least one have concaveconvex structure, make to have at least two kinds of different distance between the first electrode layer and the second electrode lay, form the effect in parallel of at least two group capacitances.
The present invention also provides a kind of capacitance structure, comprising: the first electrode layer; The first dielectric layer is located on the first electrode layer; The second electrode lay is located on the first dielectric layer; And the first guide hole passes the connection first of the first dielectric layer or the second electrode lay; Wherein the first electrode layer and the second electrode lay at least one have concaveconvex structure, make to have at least two kinds of different distance between the first electrode layer and the second electrode lay, form the effect in parallel of at least two group capacitances; Wherein first or the second electrode lay be connected to earth terminal or power end by the first guide hole.
Description of drawings
Fig. 1 a-1c is the profile of the capacitance structure of first embodiment of the invention.
Fig. 2 a-2c is the profile of the capacitance structure of second embodiment of the invention.
Fig. 3 a-3c is the profile of the capacitance structure of third embodiment of the invention.
Fig. 4 a-4b is the profile of the capacitance structure of fourth embodiment of the invention.
Fig. 5 a-5b is the profile of the capacitance structure of fifth embodiment of the invention.
Fig. 6 a-6c is the profile of the capacitance structure of sixth embodiment of the invention.
Fig. 7 a-7b is the profile of the capacitance structure of seventh embodiment of the invention.
Fig. 8 a-8b is the profile of the capacitance structure of eighth embodiment of the invention.
Fig. 9 a-9f shows the manufacture method of the capacitance structure of the embodiment of the invention.
Figure 10 a-10h shows the manufacture method of the capacitance structure of another embodiment of the present invention.
Figure 11 a-11f shows the manufacture method of the capacitance structure of further embodiment of this invention.
Figure 12 a-12f shows the Application Example of capacitance structure of the present invention.
Figure 13-16 shows other Application Example of capacitance structure of the present invention.
Figure 17 shows according to its frequency of capacitance structure of the embodiment of the invention and the graph of a relation of impedance.
Description of reference numerals
10: the first electrode layer 10a, 10b, 10c: recess;
20a, 20b, 20c: 25: the second dielectric layers of recess
30: 35: the three dielectric layer of third electrode layer
40: the four electrode layer d1, d2, d3: distance
H1, h2, h3: height 100: electrode layer
102: electrode layer 104: electrode layer
106: electrode layer 200: dielectric layer;
200 ': dielectric layer 202: dielectric layer
204: dielectric layer 300: recess
400: dielectric layer 402A: dielectric layer
402B: lower dielectric layer 404A: upper dielectric layer
404B: lower dielectric layer 500A: upper electrode layer
500A ': upper electrode layer 500A ": upper electrode layer
500B: lower electrode layer 500B ': lower electrode layer
500B ": lower electrode layer 502A: upper electrode layer
502B: lower electrode layer 504A: upper electrode layer
504B: lower electrode layer 600A: recess
600B: recess 700: electrode layer
700 ': electrode layer 702: electrode layer
702 ': electrode layer 704: electrode layer
704 ': electrode layer 705a, 705b: the first guide hole
706a, 706b: the second guide hole 800: dielectric layer
802: dielectric layer 900: recess
950: hole 3000: electrode layer
3002: electrode layer 3004: electrode layer
3006: electrode layer 3008: electrode layer
3010: electrode layer 3014: electrode layer
3016: electrode layer 4000: dielectric layer
4002: dielectric layer 4004: dielectric layer
4006: dielectric layer 7000: electrode layer
7002: electrode layer 7004: electrode layer
7006: electrode layer 7008: electrode layer
8000: dielectric layer 8002: dielectric layer
8006: dielectric layer 9001: upper electrode layer
9002: core layer 9002A: core layer
9003: lower electrode layer 9005: increase layer
9006: increase layer 9007: electrode layer
9011: surface mount assembly 9012,9012 ': capacitance structure
9010: chip (or having chip substrate thereon)
9051: conductive layer 9053: increase layer
9053A: increase layer 9054: increase layer
9054A: increase layer 9060: articulamentum
θ: angle
Embodiment
Embodiments of the invention provide a kind of combined type electric capacity structure, reach the effect in parallel of the different capacitances of many groups with concaveconvex structure (peak-valleywave structure), multi resonant vibration frequency point is provided, the impedance frequency range can be increased, reach controlling consumption of the wide-band noise of electronic circuit on decoupling capacitance.Combined type electric capacity structure of the present invention is except removing the noise of high band, reach beyond the effect that suppresses the high band noise, because concaveconvex structure is increased in the capacitance of the built-in electric capacity of substrate to increase the effective surface area mode, therefore also can form in the inhibition, the required large capacitance of low frequency range noise.
About the manufacture of each embodiment with occupation mode is following describes in detail, and follow diagram to be illustrated.Wherein, the identical identical or similar assembly of assembly numbering expression that uses in the drawing and description.And in the accompanying drawings, for the purpose of clear and convenient explanation, shape and the thickness of relevant embodiment or the situation that is not inconsistent reality is arranged.And the following description person of institute is illustrated for every assembly or its integration of device of the present invention especially, yet, it should be noted that, said modules is not particularly limited in shown or description person, but the various forms that can learn for persons skilled in the art, in addition, when the layer of material layer is when being positioned on another material layer or the substrate, it can be that to be located immediately at its surface upper or be inserted with in addition other intermediary layer.
Fig. 1 a is the profile of the capacitance structure of first embodiment of the invention, and it comprises the first electrode layer 10; The first dielectric layer 15 is located on the first electrode layer 10; And the second electrode lay 20, be located on the first dielectric layer 15.As shown in FIG., the first electrode layer 10 has concaveconvex structure in the present embodiment, and the second electrode lay 20 is plane electrode, therefore has two kinds of different vertical apart from d1, d2 between the first electrode layer 10 and the second electrode lay 20.
Because assembly capacitance (C) is to determine (K is the dielectric coefficient of dielectric layer, and d is the distance of electrode, and A is the overlapping area of electrode) by following equation:
Therefore, this capacitance structure has at least effect in parallel of C1, two kinds of basic electric capacity of C2, reaches the low-impedance characteristic of wideband, applicable to controlling consumption of different frequency bands noise.In addition, with respect to plate electrode, concaveconvex structure of the present invention has also increased the overlapping area between the electrode, therefore can improve capacitance, consist of the capacitance structure with large capacitance, also be applicable to low-frequency band, for example the application of large bulk capacitance (storage capacitor) (bulk capacitor).
Concaveconvex structure of the present invention can have various variations, and the protuberance of the recess of different depth and/or differing heights for example is so that have the different distance of two or more (〉=2 kinds) between the first electrode layer 10 and the second electrode lay 20.
Fig. 1 b shows the variation example of first embodiment of the invention, and wherein the concaveconvex structure of the first electrode layer 10 has recess 10b, the 10c of two kinds of different depths, so that produced three kinds of different vertical between the first electrode layer 10 and the second electrode lay 20 apart from d1, d2, d3.Therefore, this capacitance structure has at least effect in parallel of C1, C2, three kinds of basic electric capacity of C3, and the capacitance structure with similar multiple electrode distance can cause more groups basic capacitance, therefore increases the elasticity of capacitor combination.
Schematic diagram by frequency-impedance of Figure 17 can be found out, the result in parallel of C1, C2, three kinds of basic electric capacity of C3, has multiple resonance points wideband (Δ F) electric capacity in low target impedance (ZT), the low-impedance characteristic of its wideband is used applicable to the inhibition of basic, normal, high frequency band, and reaches controlling consumption of the different frequency range noise of electronic circuit on decoupling capacitance.
Fig. 1 c shows another variation example of first embodiment of the invention, wherein the concaveconvex structure of the first electrode layer 10 is except the recess with different depth, its protuberance also has three kinds of different height h1, h2, h3, so this capacitance structure has at least effect in parallel of five kinds of basic electric capacity of C1～C5.
By above explanation as can be known, the height of the degree of depth of each recess, protuberance all can independently be done various variations according to the actual demand on using in the concaveconvex structure of the present invention, to reach the effect in parallel of the basic electric capacity of various differences, produce the capacitance component that meets various different frequency range requirements.In addition, although about 90 degree of the recess angle θ that Fig. 1 a to Fig. 1 c illustrates, in other embodiment, angle theta can be greater than 90 degree or less than 90 degree.
Below further specify constituent material and the production method of capacitance structure.See also Fig. 1 a to Fig. 1 c, the first electrode layer 10 with concaveconvex structure is electric conducting material, such as copper (copper), gold (gold), aluminium (aluminum), palladium (palladium), nickel (nickel), silver metal materials such as (silver), but also can be conducting polymer, conductivity ceramics or aforesaid combination.
The first electrode layer 10 is except the main body (bulk) that supports and form the concaveconvex structure, also serve as and determine equivalent series inductance (effect serious inductance in the capacitance structure, ESL) one of key element sees through suitable design, can obtain quite low ESL.Recess 10a, 10b, 10c can utilize wet etching, dry ecthing or pressing mode to form.The degree of depth of each recess and width can be done suitable adjustment according to required integral capacitor value.In an embodiment, electrode layer 10 is tinsel, Copper Foil for example, and preferably utilize the mode of mould pressing to form recess 10a.Because the heat resistance limited of organic substrate, so the temperature of process for pressing is generally between 140 ℃-200 ℃, it must at the silicon substrate high-temperature technology more than 500 ℃ easily, therefore use process for pressing that the present invention be can be applicable on the organic substrate, and can reduce process costs far below general.But it should be noted that the present invention also non-application with organic substrate is limited, in fact all embodiment of the present invention all can be applicable to silicon substrate or other semiconductor substrate.
Be formed with the first dielectric layer 15 as capacitance dielectric layer at the first electrode layer 10.The first dielectric layer 15 is general insulating properties medium, comprise organic or inorganic material, for example epoxy resin, fibrous glass, pi (polyimide), ABF (Ajinomoto build-up film), BT (Bismaleimide Triacine), silicon dioxide (SiO
2), alundum (Al2O3) (Al
2O
3), silicon, glass or other material that is fit to.In addition, the first dielectric layer 15 can also be high dielectric coefficient medium, and this type of medium comprises organic or inorganic material.The first dielectric layer 15 can rubbing method, sputtering method or other method that is fit to form, but preferably forms with pressing or ink-jet method (inkjet printing).Use ink-jet method can avoid depositing the dead angle or deposit incomplete problem, and can form compliance (conformal) material layer of thinner (for example about 0.1 μ m is to about 10 μ m).Wherein ink-jet method is specially adapted to form the conforming materials layer above the recess of on-right angle formula.
Be formed with the second electrode lay 20 at the first dielectric layer 15.The material of the second electrode lay 20 can be identical or different with the first electrode layer 10.The second electrode lay 20 can adopt rubbing method, sputtering method, plating, pressing or ink-jet method (inject printing) or other mode that is fit to form.
Moreover the capacitance structure of Fig. 1 a can carry out processing technology on the thick metal of a slice, therefore has more multifarious processes.The structure of finishing can be used as the thick Copper Foil of a slice and uses, because therefore its built-in large electric capacity can be referred to as the condenser type conductor to (capacitive conductor pairs), has sizable expansionary for the application of decoupling capacitance.In addition, although do not show among the figure, can also comprise organic substrate, inorganic substrate, pre-impregnated sheet (prepreg) or the support plate that afterwards can Gong remove for 10 times at the first electrode layer.
Below will further specify other embodiments of the invention, and understand for convenient, similarly assembly will be with identical symbolic representation.Unless stated otherwise, otherwise the following stated and electrode layer and dielectric layer also can adopt foregoing material and manufacture method to form.
Fig. 2 a is the profile of the capacitance structure of second embodiment of the invention, and this capacitance structure also comprises the first electrode layer 10, the first dielectric layer 20, the second electrode lay 20.Opposite with the first embodiment, this embodiment first electrode layer 10 is plane electrode, and the second electrode lay 20 is concaveconvex structure.Shown in Fig. 2 a, this concaveconvex structure also can make the first electrode layer 10 and the second electrode lay 20 produce two kinds of different distances, so this capacitance structure has at least effect in parallel of C1, two kinds of basic electric capacity of C2.
Fig. 2 b shows the variation example of the second embodiment.Recess 20a compared to Fig. 2 a has same depth, the degree of depth of recess 20b, the 20c of Fig. 2 b is different, so that produced three kinds of different vertical distances between the first electrode layer 10 and the second electrode lay 20, cause at least effect in parallel of C1, C2, three kinds of basic electric capacity of difference of C3.
Fig. 2 c shows another variation example of the second embodiment.Compared to Fig. 2 b, the concaveconvex structure of the second electrode 20 also has the protuberance of three kinds of differing heights except the different depth recess is arranged, so this capacitance structure has at least effect in parallel of five kinds of basic electric capacity of C1～C5.
As mentioned before, by the height of each notch depth and/or protuberance in the adjustment concaveconvex structure, can cause basic capacitances of (〉=2) many groups more than 2 kinds, therefore increase the elasticity of capacitor combination.
Fig. 3 a is the profile of the capacitance structure of third embodiment of the invention.As shown in FIG., the first electrode layer 10 all has concaveconvex structure with the second electrode lay 20 in this embodiment, and the first electrode layer 10 only has two kinds of vertical ranges with the second electrode lay 20, so this capacitance structure has at least effect in parallel of C1, two kinds of basic electric capacity of C2.
In the variation example of Fig. 3 b, be the variation that the concaveconvex structure of the first electrode layer 10 is designed to have different depth and height, so this capacitance structure have at least effect in parallel of five kinds of basic electric capacity of C1～C5.And in the variation example of Fig. 3 c, be the variation that the concaveconvex structure of the second electrode lay 20 is designed to have different depth and height, so this capacitance structure also has at least effect in parallel of five kinds of basic electric capacity of C1～C5.Although show among the figure, also can be simultaneously two electrode layers 10,20 concaveconvex structure be formed the different degree of depth or height change simultaneously.
Capacitance structure of the present invention also can comprise two-layer above electrode layer.Fig. 4 a shows the fourth embodiment of the present invention, and it sequentially comprises the first electrode layer 10, the first dielectric layer 15, the second electrode lay 20, the second dielectric layer 25 and third electrode layer 30.In the present embodiment, the first electrode layer 10, third electrode layer 30 are plane electrode, and the second electrode lay 20 in the middle of being positioned at then has concaveconvex structure.As shown in FIG., this capacitance structure can produce four kinds of basic electric capacity of C1～C4 at least, and has effect in parallel.Fig. 4 b shows the variation example of the 4th embodiment.Similarly, by height and the change in depth of the second electrode lay 20 concaveconvex structures, can produce more groups basic capacitance.
Fig. 5 a shows the fifth embodiment of the present invention, and it also comprises triple electrode layer 10,20,30 and two dielectric layers 15,25 between electrode layer, but wherein the first electrode 10 and the second electrode 20 are all concaveconvex structure, and only having third electrode is the plane electrode layer.Have two kinds of capacitances of C2, C3 in the capacitance structure of Fig. 5 a between the second electrode 20 and the third electrode 30, the first dielectric layer 15 by thin thickness and homogeneous between the first electrode 10 and the second electrode lay 20 consists of large capacitance C1.Fig. 5 b shows the variation example of the 5th embodiment, by height and the change in depth of the second electrode lay 20 concaveconvex structures, produces more groups basic capacitance.
Fig. 6 a shows the sixth embodiment of the present invention, and wherein the first electrode layer 10 is plane electrode, and the second electrode lay 20 is all concaveconvex structure with the third electrode layer, and this capacitance structure has C1, C2, three kinds of capacitances of C3.Fig. 6 b shows the variation example of the 6th embodiment, wherein has five kinds of capacitances of C2～C6 between the first electrode layer 10 and the second electrode lay 20, has single large capacitance C1 between the second electrode lay 20 and the third electrode layer 30.Fig. 6 c show the 6th embodiment another change example, the difference of itself and Fig. 6 b is also to comprise between the second electrode lay 20 and the third electrode layer five kinds of capacitances.
Fig. 7 a shows the seventh embodiment of the present invention, and its first electrode layer 10 is plane electrode, and the second electrode lay 20 is all concaveconvex structure with third electrode layer 30, and be with the difference of the 6th embodiment: the concaveconvex structure of third electrode has smooth upper surface.Similarly, the second electrode lay 20 also can have the degree of depth and various variations highly with the concaveconvex structure of third electrode layer 30, shown in Fig. 7 b.
Capacitance structure of the present invention also can comprise the electrode layer more than three layers, shown in the 8th embodiment of Fig. 8 a, the 3rd dielectric layer 35 and the 4th electrode layer 40 also are set on third electrode layer 30, wherein the first, the 4th electrode layer 10,40 is plane electrode, and second, third electrode layer 20,30 is concaveconvex structure.Similarly, the second electrode lay 20 also can have the degree of depth and various variations highly with the concaveconvex structure of third electrode layer 30, shown in Fig. 8 b.In other embodiments, also can make the first electrode layer 10, the 4th electrode layer form concaveconvex structure, will not illustrate one by one at this.
Fig. 9 a to Fig. 9 f shows the manufacture method of the capacitance structure of the embodiment of the invention.At first, please refer to Fig. 9 a, electrode layer 100 is provided, have dielectric layer 200 on it.In an embodiment, the structure shown in Fig. 9 a can be gum Copper Foil (Resin Coated Copper, RCC).Then with etching or preferably utilize the mode of mould pressing to form the recess 300 of dielectric layer 200 ', shown in Fig. 9 b.See through the mould pressing and form recess, can reach cheaply target, advantage is not need to see through to electroplate to plate out concavo-convex metal structure at the ground floor conductor, except saving cost, also can improve the compatibility of subsequent technique.Dielectric layer 200 ' has the recess 300 that angle theta is.Angle theta can be greater than about 90 degree.In other embodiments, angle theta is about 90 degree (not shown)s.
Please refer to Fig. 9 c, then form electrode layer 102 in dielectric layer 200 ' top.Please refer to Fig. 9 d, then preferably above electrode layer 102, be coated with dielectric layer 202 with ink-jet method.Please refer to Fig. 9 e, above dielectric layer 202, form electrode layer 104.Please refer to Fig. 9 f, then above electrode layer 104, form dielectric layer 204, then above dielectric layer 204, form electrode layer 106.In an embodiment, be that the laminated board (laminate) that will comprise dielectric layer 204 and electrode layer 106 is formed on the electrode layer 104.In other embodiments, the formation step of capacitance structure still comprises the step (not shown) that forms guide hole (via) or wire (trace).It is noted that, in order to increase the adhesive force between electrode layer and the dielectric layer, optionally electrode layer or dielectric layer are carried out suitable surface treatment, or insert extra reinforcement material/layer (reinforcematerial/layer).
Figure 10 a to Figure 10 h shows the manufacture method of the capacitance structure of another embodiment of the present invention.At first, please refer to Figure 10 a, the top of dielectric layer 400 and below have respectively upper electrode layer 500A and lower electrode layer 500B.In an embodiment, the shown structure of Figure 10 a is the double-sided printed-circuit board (PCB) with thin dielectric layer 400 of high-dielectric coefficient.Upper electrode layer 500A and lower electrode layer 500B can have identical or different thickness.
Please refer to Figure 10 b, with wet type or dry etching method or utilize the mode of mould pressing to form the electrode layer 500A ' with at least one recess 600A.The angle theta of recess 600A is preferably greater than 90 degree.In other embodiments, the about 90 degree (not shown)s of the angle theta of recess.
Please refer to Figure 10 c, compliance forms upper dielectric layer 402A in upper electrode layer 500A ' top.Please refer to Figure 10 d, compliance forms upper electrode layer 502A above upper dielectric layer 402A.Please refer to Figure 10 e, fill up recess 600A fully with upper dielectric layer 404A.Upper dielectric layer 404A covers upper electrode layer 502A fully and has smooth upper surface.Then, above upper dielectric layer 404A, form upper electrode layer 504A.
Then, please refer to Figure 10 f, remove part lower electrode layer 500B to form lower electrode layer 500B '.Lower electrode layer 500B ' has at least one recess 600B, and the angle theta of recess 600B is preferably greater than 90 degree.In other embodiments, angle theta is about 90 degree (not shown)s.The shape of recess 600A and recess 600B can be identical or different.
Please refer to Figure 10 g, dielectric layer 402B under lower electrode layer 500B ' below forms.Then below lower dielectric layer 402B, form lower electrode layer 502B.Please refer to Figure 10 h, following dielectric layer 404B fills recess 600B.Lower dielectric layer 404B may extend to the lower surface of lower electrode layer 502B, and has smooth lower surface.Then below lower dielectric layer 404B, form lower electrode layer 504B.
In the shown embodiment of Figure 10 a to Figure 10 h, be to form capacitance structure prior to dielectric layer 400 tops, below dielectric layer 400, form again another capacitance structure.Yet in other embodiments, the capacitance structure that is positioned at dielectric layer 400 upper and lowers also can utilize identical technique to form simultaneously.Moreover the capacitance structure that is positioned at dielectric layer 400 upper and lowers can be asymmetrical, but for example up and down recess 600A, 600B misalignment, but arrange with interlace mode, perhaps recess 600A, 600B can have the different degree of depth up and down.Similarly, the formation step of capacitance structure still comprises the formation guide hole (via) of not demonstration or the step of wire (trace), and optionally electrode layer or dielectric layer are carried out suitable surface treatment with increase adhesive force, or insert extra reinforcement material/layer (reinforce material/layer).
Figure 11 a to Figure 11 f shows the manufacture method of the capacitance structure of further embodiment of this invention.At first, please refer to Figure 11 a, the top of dielectric layer 400 and below have respectively electrode layer 500A and 500B.In an embodiment, the shown structure of Figure 11 a is the double-sided printed-circuit board (PCB) with high-dielectric coefficient and thin dielectric layer 400.
Please refer to Figure 11 b, can utilize wet type or dry etching method to form and have the electrode layer 500A ' of recess 600A, and the electrode layer 500B ' with recess 600B.Recess 600A and recess 600B can form by one step simultaneously, or are separately formed by individual other step.Among the embodiment, recess 600A and recess 600B be the upper and lower surface of exposed dielectric layer 400 respectively therewith.In an embodiment, electrode layer 500A ' and electrode layer 500B ' are (that is dissymmetrical structure) (not shown)s that staggers, so design can make the mechanical strength of the dielectric layer 400 of thin and high-dielectric coefficient enough support follow-up technique, and can not produce the phenomenon of break (crack).
Please refer to Figure 11 c, after etching recess 600A, 600B, form electrode layer covers electrode layer 500A ', the 500B ' of compliance and dielectric layer 400 upper and lower surfaces of exposing, obtain indicating 500A among the figure ", 500B " electrode structure, electrode layer 500A wherein " be to consist of electrode layer 500B by electrode layer 500A ' with compliance electrode layer on it " be to be consisted of with compliance electrode layer on it by electrode layer 500B '.The electrode layer of this compliance can be electroplated the techniques such as the collocation seed metal electroless plating (seed metalelectro-less plating) of (plating) method or sputter (sputtering) and form.
Please refer to Figure 11 d, in recess 600A and recess 600B, form respectively dielectric layer 402A and the 402B of compliance.Please refer to Figure 11 e, can use the mode of printing (printing), sputter or plating, above dielectric layer 402A and 402B, form respectively electrode layer 502A and electrode layer 502B.
Please refer to Figure 11 f, with dielectric layer 404A and electrode layer 504A, and dielectric layer 404B and electrode layer 504B are respectively formed on recess 600A and the 600B.In an embodiment, pressing has dielectric layer 404A and electrode layer 504A, and the gum Copper Foil (ResinCoated Copper, RCC) with dielectric layer 404B and electrode layer 504B is to form the capacitance structure shown in Figure 11 f.
Capacitance structure of the present invention can be applicable in printed circuit board (PCB) (PCB), keyset (interposer), IC substrate or the integrated circuit package, in order to carry out the inhibition of noise.Figure 12 a to Figure 12 f shows the Application Example of capacitance structure of the present invention.Please refer to Figure 12 a, at first above the electrode layer 700 with recess 900, sequentially form dielectric layer 800 and electrode layer 702.Please refer to Figure 12 b, for example can use laser mode to remove segment electrode layer 702 to form electrode layer 702 '.Please refer to Figure 12 c, the gum Copper Foil (Resin Coated Copper, RCC) that will contain dielectric layer 802 and electrode layer 704 is pressure bonded on the structure of Figure 12 b.Then, remove the electrode layer 704,700 of part to form electrode layer 704 ', 700 ', shown in Figure 12 d with dry ecthing or wet etching.
Please refer to Figure 12 e, dielectric layer 802 and dielectric layer 800 are bored a hole, to form hole 950.Can machine drilling, laser beam perforation or photoetching process form hole 950.Please refer to Figure 12 f, fill hole 950 to form the first guide hole (Via) 705a, 705b and the second guide hole 706a, 706b with conductive layer.Number in the figure G, S, P represent respectively earth terminal (Ground), signal end (Signal), with power end (Power).By among the figure as can be known, the first guide hole 705a passes dielectric layer 802 connecting electrode layers 702 '.The first guide hole 705b passes dielectric layer 802,800 connecting electrode layers 700 '.So, the first guide hole 705a, 705b can be connected to electrode layer 702 ', 700 ' respectively outside electrical power end P and electrical earth terminal G.On the other hand, the second guide hole 706a, 706b pass dielectric layer 800,802 and run through whole capacitance structure, and the second guide hole 706a, 706b be not connected with electrode layer 702 ', 700 ', are the usefulness as the signal transmission.
With respect to parallel electrode plate, has the power end P of concaveconvex structure and the earth terminal G interference between can the barrier unlike signal.In this capacitance structure, signal end S can see through the second guide hole 706a, 706b penetrates the demand that whole capacitance structure reaches the signal transmission, the electromagnetic radiation as waves that this external signals transmission causes thus capacitance structure absorbs, shown in Figure 12 f, this capacitance structure can suitably design projective structure (dotted portion among the figure) between two signal end S, electrode layer 702 ' in this projective structure, 700 ' sees through the first guide hole 705a, 705b is connected to respectively power end P and earth terminal G, stop and the effect of absorption of electromagnetic radiation ripple that to reach this class formation is quite effective for suppressing the electromagnetic radiation as waves that high frequency and high speed signal transmittance process produce.
Figure 13 to Figure 16 shows other Application Example of capacitance structure of the present invention, wherein can reach serial or parallel connection between the capacitance structure by different conductive layers and guide hole connected mode, and persons skilled in the art are when can each conductive layer being connected to respectively power end, earth terminal or signal end according to the demand in the design.
Figure 13 shows the capacitance structure of ultra-thin nuclear plate (ultra-thin core) collocation wideband uncoupling (wide band decoupling).The capacitance structure of Figure 13 comprises electrode layer 3000,3002,3004,3006,3008,3010,3014 and 3016, and dielectric layer 4000,4002,4004 and 4006, its dielectric layer 4000 and 4006 is preferably the high-dielectric coefficient dielectric layer of the about 50um of thickness, dielectric layer 4000,4002 is the high-dielectric coefficient dielectric layer of compliance, electrode layer 3000 and 3008 is preferably Copper Foil, and the preferred about 60um of integrally-built thickness.In the application of general IC substrate, substrate size is usually comparatively speaking less, generally can be about 35mmx35mm, and the passive part of the master of carrying above is limited, what this type of substrate was worried most is the interference problem of Switching Noise (simultaneous switching noise, SSN).Capacitance structure of the present invention has many group capacitances, and the design of multi resonant vibration frequency point is provided, and the condensance frequency range is broadened, and reaches the SSN inhibition of wideband.Utilize the capacitance structure of ultra-thin nuclear plate collocation wideband uncoupling among the present invention, applicable to for example mobile phone, personal digital assistant (personal digitalassistant, PDA), the module board (module board) of mobile computer etc., and the product of microminiaturization and high density interconnect (High Density Interconnection, HDI) is used.
Figure 14 is the schematic diagram that the capacitance structure of Figure 13 is applied to encapsulating structure.Capacitance structure 9012 comprises electrode layer 7000,7002,7004,7006, reaches 7008, and dielectric layer 8000,8002 and 8006.Encapsulating structure can comprise guide hole 9051.As shown in FIG., guide hole 9051 can be formed in each layer laminated film of encapsulating structure to connect upper/lower electrode layer by layer and reach the in parallel or series connection of capacitance structure.Encapsulating structure comprises electrode layer 9003.Core layer 9002 between electrode layer 9001 and electrode layer 9003 can comprise printed circuit board (PCB) (PCB), silicon, pottery or glass.Comprise dielectric layer increase the layer (build-uplayer) 9053 and 9054 can be formed at respectively core layer 9002 tops and below.Electrode layer 9007 can be formed at and increase layer 9006 below.In this embodiment, capacitance structure 9012 is formed in the upper part that increases layer 9053, near chip (or having chip substrate thereon) 9010 or surface mount assembly (surfacemounted device, SMD) 9011, therefore providing quite effectively, Switching Noise (simultaneous switching noise, SSN) suppresses effect.Yet capacitance structure does not limit the position that is arranged at as shown in figure 14.In other embodiments, capacitance structure can be arranged at other suitable position in the encapsulating structure, for example is arranged in the lower part that increases layer 9053 or increases the upper of layer 9054 or lower part, or be positioned at the position of core layer 9002.In addition, the capacitance structure that is applied in the encapsulating structure is not limited to the shown structure of Figure 13, and also can be the capacitance structure of other embodiment.
Figure 15 is the schematic diagram that the capacitance structure of another embodiment of the present invention is applied to encapsulating structure.The Main Differences of Figure 15 and Figure 14 is that the capacitance structure 9012 of this embodiment is formed at the lower part that increases layer 9053A and increases in the upper part of layer 9054A.Moreover the upper part of encapsulating structure and lower part can be utilized by the formed articulamentum of high-k material (bonding layer) 9060 and be connected.In other embodiments, capacitance structure can be arranged in the encapsulating structure arbitrarily appropriate location (not shown), for example is arranged in the upper or part that increases layer 9053A, or is arranged in and increases layer 9054A's or lower part, or is positioned at the position of core layer 9002A.
Figure 16 is the schematic diagram that the capacitance structure of another embodiment of the present invention is applied to integrated circuit (IC) chip 9010.Conductive layer 9051 can be formed in the silicon through hole (through-siliconvia, TSV) that runs through integrated circuit (IC) chip 9010.Capacitance structure 9012 ' can be formed in the upper part of integrated circuit (IC) chip 9010.In other embodiments, capacitance structure can be arranged in the integrated circuit (IC) chip 9010 other arbitrarily appropriate location, for example chip back or front, and the signal of chip can see through earth terminal (G) in the capacitance structure, signal end (S), spread out of with the guide hole such as power end (P).In addition, be applied to that capacitance structure in the integrated circuit (IC) chip is not limited to the shown structure of Figure 13 and also can be the capacitance structure that other embodiment discloses.
In sum, embodiments of the invention are to utilize the jagged substrate of tool to form capacitance structure, therefore can be under the qualifications of fixing base area, has higher effective area, therefore and be formed on the thin dielectric layer between the electrode layer, higher capacitance can be provided and improve effect to noise suppressed.Moreover, utilize the shape of change dielectric layer, electrode layer and recess or the method for structure, make capacitance structure have the effect in parallel of more groups capacitance, thereby increase the impedance frequency range.When capacitance structure has thin dielectric layer simultaneously and can consist of the dielectric layer of the change thickness of organizing capacitances more, capacitance structure has the low-impedance characteristic of wideband, applicable to basic, normal, high frequency band, the for example application of decoupling capacitance (decoupling capacitor), and reach controlling consumption of the different frequency range noise of electronic circuit on decoupling capacitance.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention, any persons skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.
Claims (16)
1. capacitance structure comprises:
The first electrode layer;
The first dielectric layer is located on this first electrode layer;
The second electrode lay is located on this first dielectric layer,
The second dielectric layer is located on this second electrode lay; And
The third electrode layer is located on this second dielectric layer,
Wherein this first electrode layer and the second electrode lay at least one have concaveconvex structure, make between this first electrode layer and this second electrode lay and have at least two kinds of different distance, form the effect in parallel of at least two group capacitances, the thickness homogeneous of this second dielectric layer is between 0.1 μ m to 10 μ m.
2. capacitance structure as claimed in claim 1, wherein this first electrode layer has concaveconvex structure, and this second electrode lay is plane electrode.
3. capacitance structure as claimed in claim 1, wherein this first electrode layer is plane electrode, this second electrode lay has concaveconvex structure.
4. capacitance structure as claimed in claim 1, wherein this first electrode layer and this second electrode lay all have concaveconvex structure.
5. capacitance structure as claimed in claim 1, wherein this third electrode layer is plane electrode.
6. capacitance structure as claimed in claim 1, wherein this third electrode layer has concaveconvex structure.
7. capacitance structure as claimed in claim 1 also comprises:
The 3rd dielectric layer is located on this third electrode layer; And
The 4th electrode layer is located on the 3rd dielectric layer.
8. capacitance structure as claimed in claim 7, wherein this third electrode layer is plane electrode.
9. capacitance structure as claimed in claim 7, wherein this third electrode layer has concaveconvex structure.
10. capacitance structure as claimed in claim 1, wherein these two kinds of different distance are two kinds of different vertical distances.
11. such as the arbitrary described capacitance structure of claim 1-10, wherein this concaveconvex structure has the recess of the two or more degree of depth, makes between this first electrode layer and this second electrode lay to have two or more different distance.
12. such as the arbitrary described capacitance structure of claim 1-10, wherein this concaveconvex structure has the protuberance of two or more height, makes between this first electrode layer and this second electrode lay to have two or more different distance.
13. such as the arbitrary described capacitance structure of claim 1-10, wherein this concaveconvex structure has the protuberance of two or more height and the recess of the two or more degree of depth.
14. such as the arbitrary described capacitance structure of claim 1-10, also comprise at least one guide hole, link this capacitance structure to another capacitance structure in the serial or parallel connection mode.
15. a capacitance structure comprises:
The first electrode layer;
The first dielectric layer is located on this first electrode layer;
The second electrode lay is located on this first dielectric layer;
The second dielectric layer is located on this second electrode lay;
The third electrode layer is located on this second dielectric layer,
The first guide hole passes this first dielectric layer and connects this second electrode lay;
Another first guide hole passes this first dielectric layer and is connected the second dielectric layer and connects this third electrode layer;
Two the second guide holes pass this first dielectric layer and are not connected with this first electrode layer and the second electrode lay, in order to transmission of signal,
Wherein this first electrode layer and the second electrode lay at least one have concaveconvex structure, make between this first electrode layer and this second electrode lay and have at least two kinds of different distance, form the effect in parallel of at least two group capacitances, the thickness homogeneous of this second dielectric layer is between 0.1 μ m to 10 μ m;
Wherein this first guide hole and this another the first guide hole are connected to respectively outside electrical power end and electrical earth terminal with this second electrode lay and this third electrode layer;
The projection that wherein has this concaveconvex structure between these two second guide holes, and the first electrode layer of this projection and the second electrode lay are connected to respectively earth terminal and power end.
16. capacitance structure as claimed in claim 15, wherein these two kinds of different distance are two kinds of different vertical distances.
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| TWI510152B (en) * | 2013-07-10 | 2015-11-21 | Ind Tech Res Inst | Embedded capacitor module |
| TWI540739B (en) * | 2013-09-12 | 2016-07-01 | 璨圓光電股份有限公司 | Capacitor structure and stack-type capacitor structure |
| CN104701314A (en) * | 2015-03-24 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN108962880B (en) * | 2018-07-17 | 2024-05-03 | 昆山思特威集成电路有限公司 | High-density multilayer stacked MIM capacitor, pixel circuit and imaging device |
| CN110825273A (en) * | 2018-08-10 | 2020-02-21 | 无锡变格新材料科技有限公司 | Manufacturing process of double-sided process sputtering film capacitive touch sensor |
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| CN1403853A (en) * | 2002-09-05 | 2003-03-19 | 统宝光电股份有限公司 | Storing capacitance structure for planar display and its forming process |
| CN101527199A (en) * | 2008-02-29 | 2009-09-09 | 财团法人工业技术研究院 | Capacitor device and circuit |
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| CN1403853A (en) * | 2002-09-05 | 2003-03-19 | 统宝光电股份有限公司 | Storing capacitance structure for planar display and its forming process |
| CN101527199A (en) * | 2008-02-29 | 2009-09-09 | 财团法人工业技术研究院 | Capacitor device and circuit |
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